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Advanced Verification |
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Welcome to the November 2007 issue of FPGA Developer, too late for turkey, but no too late to avoid them. We complement Chip Design magazine by presenting PLD news -- including FPGAs and Structured ASICs -- opinions from industry experts, and technology articles. See below for subscribe and unsubscribe options. This Month's Table of Contents:
Exclusive Sponsor: Mentor Graphics Industry Announcements» Mentor Graphics Announces an Optimized FPGA Design Flow Between Precision Synthesis and MathWorks Simulink HDL Coder» Mentor Graphics Announces HDL Designer Series with SystemVerilog Support for Design-to-Verification Productivity» Elektrobit Corporation Selects Catapult C Synthesis to Design Next-Generation Wireless Hardware» Experience SystemC: Advanced SystemC Debug with Vista» Visit the new Precision family this holiday season | |
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Exclusive Sponsor: Mentor Graphics Customer Endorsements of new FPGA Synthesis Tool Come and read what our customers have to say about the new Mentor Graphics' FPGA Synthesis Tool , Precision RTL Plus. |
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1. Editor's NoteBeans, Barges and Captain Bligh (Part Two of Conserving Cowboys)By Jim Kobylecky, Editor
Championing all good choices is the role of the FPGA Developer. In this issue, Stacy Secatch of Xilinx finds a playful approach to verification in "Error Management as Easy as `Tag You're It.'" Then Michael Monkang Chu of DRC Computer considers PLDs from a highly logical perspective in "Challenges in High Speed Reconfigurable Computing." Next relax with our selected news briefs and consider our other regular features. You'll find a refreshing break from your holiday deadlines. Full Story » | |
2. Viewpoint – ExclusiveError Management as Easy as "Tag You're It"By Stacey Secatch, Staff Design Engineer, Xilinx
Modern EDA tools identify each detected failure with an error code and a message describing the problem. Errors are documented in detail to help engineers isolate the problem corresponding to a particular error code. Following the same principle, tagging every error check with a unique code along with a thorough description of the error message isolates any given failure to a specific "if" statement. This is more useful than merely lumping the error with other similar failures. Error tagging enables any user to track down the exact testbench check that flagged a failure without requiring a complete understanding of that testbench. Full Story » 3. Viewpoint – ExclusiveChallenges in High Speed Reconfigurable ComputingBy Michael Monkang Chu (mmchu@drccomputer.com), Manager, Application Engineering / DRC Computer Corporation
RPUs take CPU-bound problems and turn them into IO-bound problems. As programmers start putting more complicated algorithms in RPUs, the need for greater IO and memory bandwidth at lower latencies becomes apparent. This is well illustrated in two major industries being tackled by RPU vendors: oil & gas exploration and programmatic financial trading. Full Story » |
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Exclusive Sponsor: Mentor Graphics HDL Designer Accelerating Adoption of SystemVerilog SystemVerilog is a powerful language that enables tremendous improvements in both advanced design and verification methodologies. HDL Designer provides a solution to accelerate adoption and improve productivity of designers who wish to use SystemVerilog. Visit our website to learn more. |
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4. News: Battery Life Estimator Perks up Portable DesignsThe enhanced Libero Integrated Design Environment from Actel Corporation boasts new
features, such as power-driven layout, that help designers reduce dynamic power
consumption by as much as 30 percent for a typical design. With the analysis capabilities
of its SmartPower tool, the environment can help users understand power usage in all
functional modes of the design. The battery life estimation feature gives an accurate
calculation of battery life based on the FPGA design power profile. The new version
supports all of the company's low-power families, including the ultra low-power IGLOO
FPGAs and the mixed-signal Fusion Programmable System Chips (PSCs). |
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5. News: Low-Cost Starter Kit for CAP Customizable MicrocontrollerAtmel Corporation launched the Stratix FPGA-based AT91CAP9A-STK Starter Kit for
its CAP Customizable Microcontroller product family. The kit enables a low-cost, no-risk
evaluation of the customization capabilities of the CAP MCU. It maps application-
specific IP blocks into its FPGA that emulates the functionality of the CAP's embedded
Metal Programmable (MP) Block. It is built on a single PCB that includes the
microcontroller, 64M Bytes of SDRAM application memory, 512M Bytes of NAND
Flash and an optional DataFlash with up to 8M Bytes, together with external interfaces
for Ethernet, USB Host and Device, 1/4 VGA LCD Panel with Touch Screen, SD Card,
4 analog inputs and audio headphones. |
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Exclusive Sponsor: Mentor Graphics Introducing Precision RTL Plus for FPGA Synthesis The latest addition to the Precision Synthesis family which builds on Precision RTL by delivering an exciting vendor-independent solution for breakthrough productivity with three industry-first capabilities for every designer, regardless of level of expertise: 1. Physically aware synthesis to reach design goals faster, in fewer iterations 2. Incremental synthesis to minimize the impact of late cycle design changes 3. Resource manager to make efficient use of FPGA architectural blocks Download a technical paper or watch a demo on these three industry-first capabilities |
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6. News: Synthesis Tool Allows Direct HDL Code TransferMutual customers can now transfer VHDL and Verilog generated by the MathWorks
Simulink HDL Coder directly into Mentor Graphics' Precision Synthesis tool to generate
an optimized netlist implementation for FPGA designs. Both companies collaborated on
this flow to assure interoperability. The coder generates bit-true, cycle-accurate,
synthesizable Verilog and VHDL code from Simulink models, Embedded MATLAB
code, and Stateflow charts. The synthesis tool is a comprehensive vendor-independent
solution for FPGA design, and it is the only synthesis tool which offers true push button
multi-vendor physical synthesis. It features award-winning design analysis, allowing
designers to cross-probe between multiple views and perform interactive static timing
"what-if" analyses. |
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7. News: Front Side Bus FPGA HPC SolutionXilinx, Inc. has begun commercial licensing of the high-performance computing
industry's
first FPGA-based acceleration solution to interface with the Intel Front Side Bus (FSB).
Enabled by the high-performance 65nm Virtex-5 platform FPGA and Intel(R)
QuickAssist Technology, the Accelerated Computing Platform (ACP) M1 licensing
package supports implementations capable of full 1066MHz FSB performance. The ACP
M1 licensing package is available today to system integrators for developing solutions
that accelerate the performance of Intel processor-based server platforms while
minimizing power consumption and total cost of ownership. The ACP M1 hardware
reference design is pin compatible to an Intel Socket 604 Xeon processor and is targeted
for the new 7300 series multi-processor data center platform. |
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8. International News: Formal Verification Advances in JapanOneSpin Solutions KK expanded operations in Japan with a new sales and field
applications engineering office in Yokohama and added local field-application experts.
Earlier this year the company had launched the an equivalence checker for FPGAs –
OneSpin 360TM EC-FPGA – to support all sequential optimizations performed by FPGA
synthesis tools on large designs, enabling designers to meet functional, performance and
cost targets. Other products offer first-time-right, error-free operation and true
functional
sign-off for a broad range of digital modules and Intellectual Property (IP), such as
peripherals, processors and subsystems of up to a few hundred thousand lines of RTL
code. For more information please contact infojp@onespin-solutions.jp. |
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9. International News: Scottish FPGA Supercomputer Nominated for Industry AwardsA unique supercomputer called `Maxwell' – built in Scotland by the FHPCA Alliance
with the support of Scottish Enterprise – is in the running for two awards (Best Use
of
Green Technology Project Award and the BT Flagship Award for Innovation) at the
British Computer Society IT Industry Awards 2007. The nominations recognize
Maxwell's unique combination of innovation and energy-efficiency. Maxwell is over 100
times more energy efficient and up to 300 times faster than a conventional microprocessor
system. The system consists of a 32-way IBM BladeCentre chassis hosting 64 Xilinx
Virtex-4 FPGAs directly connected over high-speed RocketIO, allowing codes to be
parallelized across the FPGAs. |
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10. In-Depth Coverage LinksIn Michel Courtoy's view, Verification should attract creative engineers eager to
master
the complexity and to adopt new technologies. Yet quality verification engineers are
scarce and we're not training more of them. Consider the reasons in "Do Verification
Engineers Have the Odds Stacked Against Them?" First published in the Chip Designer
newsletter. Timing-exception constraints help designers get the most out of a given silicon device.
Without proper verification, however, constraints can cause systems to fail in subtle
ways.
Some companies won't even try them. Ralph Marczynski believes that we need a hybrid
formal technology to succeed. See if he's right on this time in "Will Timing-Exception
Verification Reach Its Full Potential? |
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11. Book ReviewASIC and FPGA Verification: A Guide to Component Modeling The author begins with an overview of board-level verification and progressing to
component modeling and testbenches. It was one of the first books to show how to create
and use simulation models to verify ASIC and FPGA designs and board-level designs
that use off-the-shelf digital components. The models are based on the VHDL/VITAL
standard, which include timing constraints and propagation delays. The book is designed
for both system designers and for short courses on component modeling. Kind of a
classic. | |
12. Happenings – ConferencesIP Based Electronic System Conference (IP2007) SEMICON Japan 2007 2007 IEEE International Electron Devices Meeting International Conf, on Field-Programmable Technology 2007 International Conference on Microelectronics (ICM 2007) 2008 International CES International Solid-State Circuits Conference 2008 DesignCon 2008 DVCon 2008 FPGA 2008 International Symposium on Quality Electronic Design (ISQED'08) |
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FPGA DEVELOPER e-NEWSLETTER CONTACTS
Editor: Jim Kobylecky, jkobylecky@extensionmedia.com Advertising/Sponsorship Opportunities: Karen Popp, Read past issues of Chip Designer, FPGA Developer, IP Designer & Integrator, and Wireless Chip Designer: www.chipdesignmag.com/enewsletters To subscribe, or change your profile, visit: Visit Chip Design:
Copyright © 2007 Extension Media, Inc. All rights reserved. |
Last issue I took the easy way out. I defended the worth of difficult, but highly
creative
engineers – the genius cowboys who never learned to play well with others. How could
anyone object? Well, out loud anyway. Now, I did concede that a few might need a little
polish. Say eight months at an Etiquette and Empathy Boot Camp – surrounded by gentle
guides such as attack dogs, barbed wire, and seven-foot nanny/DI's called "Arnold" and
"The Countess" ("YOU CALL THAT A CAVEAT, SOLDIER!"). Sometimes, though,
championing genius is just a cowardly way to avoid business reality.
The ultimate purpose of a verification environment is to ensure the proper
functionality of
a device prior to release. In addition, that same environment usually serves the equally
important but less visible role of enabling the bring-up of a design. By starting system-
level testing as soon as possible on available functionality and systematically ignoring
known failures, specific features can be turned on before the entire design is available
for
testing. All that's needed is a minimal amount of up-front error handling and error
classification planning to significantly improve testbench usability during the early
stages
of the design cycle—for both design and verification engineers.
Reconfigurable processing units (RPUs) provide amazing opportunities for acceleration
over traditional microprocessors. RPUs allow programmers to create circuits tailored to
the specific computational problem. However, as RPUs become more popular in high
performance computing, programmers face challenges in achieving the desired
performance. These challenges range from increasing demands for more bandwidth at
lower latencies to dealing with non-parallelism inherent in certain algorithms. We discuss
several of these challenges and see how they are addressed by modern commercial RPUs,
such as DRC's RPU110-L200.