by Peggy Aycinena

September 14, 2004

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History & Geography — "John Sanguinetti - A Profile"
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Editorís Note

The September 2004 issue of EDA Nation includes a challenge. The lead article is extremely lengthy, but if you can give it the time, the read is well worth the effort. John Sanguinetti is a household name in the EDA industry and this is his profile.

Currently, John is serving as the industry's poster child for Multiple Myeloma, a rare blood cancer and the subject of a lot of intense medical research. As such, John will be the guest of honor at an industry fund-raiser in San Jose, California, on September 15, 2004.

However, that's not what makes John's story here compelling. The reason you should rise to the challenge and read this thing in its entirety is because John Sanguinetti is more appropriately the poster child for EDA - a Ph.D. technologist, an entrepreneur, a long-time player in Silicon Valley, and someone who has influenced and been influenced by the trends and characteristics unique to the EDA industry.

If you're involved in the EDA industry, this is more than John Sanguinetti's story. This is your story.

Peggy Aycinena
September 2004

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History & Geography

"John Sanguinetti - A Profile"

Prologue - The trombone

This article is the result of several conversations that I had with John Sanguinetti over the course of a week in August 2004, during which he talked about his lengthy career and the many observations and conclusions he has drawn from his complex experiences. Our conversation concluded with a discussion of his diagnosis and treatment for Multiple Myeloma.

John Sanguinetti was born and raised in Maryland, where he began to play the trombone early on. That fact ended up having a lasting impact in EDA because in choosing a college, John looked for a school with a great college band and a spectacular music program. That turned out to be the University of Michigan, a place that John discovered also had a pretty good engineering program as well.

John spent 4 years in the Michigan marching band - even today he goes back now and then to attend football games - but he left the trombone behind during his graduate school years. Today however, John’s an active participant in the Peninsula Symphony Orchestra where he’s been a member of the brass section for over 20 years.

Chapter 1 - 1966 to 1977

My intention was to only spend 4 years in Ann Arbor and then to move on, but it didn’t work out that way. After I got my BSE in Applied Math, I applied to some of the top schools in Computer Science for graduate school. I got into Berkeley and Michigan among other places, but chose Michigan because they promised the doctorate would only take me 3 years - Berkeley promised 4 years. As it turned out, it ended up taking me 7 years at Michigan.

During those 7 years, I spent a lot of time working at the Computer Center on the Michigan campus, and it was there that I developed an interest in operating systems and design methodologies. I subscribed to top-down design philosophies and discovered there had only been a handful of operating system design projects reported up until then done in that style. That was back in the late 1960’s and early 1970’s, and operating systems were not as complicated as they are today. The hardware was much simpler and operating system design methodology was simpler as well.

My advisor at Michigan had come up with a formal modeling language for systems that could handle concurrent processes. Essentially, the language was an extension of regular expressions to determine if things would deadlock given certain circumstances. My thesis work entailed adding some features to the language, so that you could predict the performance of the operating system.

My scheme produced a sequence of messages that could be instrumented to determine in advance how long it would take to get from one state to another - it was kind of esoteric. Along the way, I wrote a compiler and a simulation run time library for this language, which was in essence a process-oriented simulation language. Overall, my graduate research work ended up accomplishing its objective - I got my degree, but it wasn’t terribly significant, or so I thought at the time. I was convinced that there would never be any practical application for my work.

Chapter 2 - 1977 to 1982

So I ended up staying for 11 years at Michigan and at the end of that time, I had a Ph.D. and a wife - not necessarily in that order. As I was finishing up my Ph.D., my wife was finishing medical school at Wayne State in Detroit. Following on that, she accepted an internship in Boston and I accepted a job working for DEC [Digital Equipment Corp.] on Route 128 outside of Boston. I arrived at DEC just a few months before the company’s first VAX shipped in September 1977. My job at DEC was to do performance analysis for them, primarily on their existing PDP-11 product line.

In one instance, the company was going to build an algorithm into the controller to optimize disk head movement, but my simulation model, in Simula, showed that effort was unnecessary. That work was significant because it would have cost them about half a million dollars at the time to do that controller. In any case, nobody at DEC really thought of me as a software guy. I was doing a lot of formal analysis about head seeking and was closely associated with the hardware guys in the company. That was my first close association with hardware designers.

Two years after we arrived in Boston, my wife finished her internship at Tufts in Boston, I left DEC, and we went back to Detroit where she did her residency in Ob-gyn. I returned to the university and took a job in the Computing Center in Ann Arbor, and that’s where we stayed for the next three years.

Chapter 3 - 1982 to 1986

My wife and I had made a deal after moving back to Michigan from Boston, that the next time we moved it would be my turn to decide where we landed. At that time, I had just read a paper in Computing Surveys by Mac MacDougal at Amdahl, who was one of the first people to do extensive simulation of computing systems at Control Data. Mac had gone to Amdahl in the mid 1970’s and was somebody I felt I could really learn from.

So after my wife finished her residency, we came to California and my wife set up one of the first all-women-doctor Ob-gyn practices in the Bay Area. Things have really changed since then - more than half of the OB-Gyns in the Bay Area are women today - but there were very few in 1982.

I started at Amdahl and began by doing performance analysis once again, trying to determine how fast the new machine would go - working usually in conjunction with the architecture group at the company. At Amdahl, performance was everything, and of course things had to be completely IBM 370 compatible. Incidentally, in those days, PC meant “Plug Compatible.”

Nobody was going to buy an Amdahl machine unless it was faster than an IBM. My group was creating benchmarks that were representative of customer workloads - it was before there were standard benchmarks in the industry - and analyzing the results.

Those were pretty heady times and the group that I was in was really quite good. Amazingly enough, some of the people in that group ended up staying at Amdahl for 20 years - even after the company became Fujitsu - but I only stayed for 2 years.

When I got to Amdahl in 1982, Silicon Valley was buzzing with talk of start-up companies. It was just after the first IBM PC had been announced and everybody and his brother were making an ‘almost-compatible’ PC. That was before the BIOS was cloned, making true compatible machines possible. I made some good friends at Amdahl, including one who was leaving to join a start-up. I had no idea how to go about it, but I wanted to join a start-up as well.

It was at that time in 1983 that I joined the Peninsula Symphony Orchestra as a trombone player. There was another trombone player in the brass section named Jim Jaffe, who was one of 8 founders of a company called Elxsi. Other founders included Joe Rizzi, who later became a partner at Matrix, and Thampy Thomas who went on to found NextGen after Elxsi.

Elxsi was making a super minicomputer to compete with the VAX from DEC and had about 300 employees. Unfortunately, although it looked like a start-up to me, it really wasn’t - it had been going for five years. The company was in that stage of having to do market development and getting product out into the hands of customers and it wasn’t succeeding. It was a zombie - not really alive, but not dead either.

In any case, I joined Elxsi and essentially did the same thing I had been doing at Amdahl. Eventually, I ended up doing both performance analysis and architecture at the company. Over time, however, I realized that Elxsi was a failed start-up and so I left after only 2 years - but not before I saw the folly of having a company name that nobody could pronounce or spell.

Chapter 4 - 1986 to 1990

In 1986, a headhunter told me about The Dana Group, which eventually became Ardent Computer, and then Stardent Computer - a company that was going to make a mini-supercomputer. In the mid 1980’s, this machine would target 8 megaflops on Linpack and a few hundred thousand triangles-per-second graphics performance. It would have computational processing applications and use a graphics subsystem to draw the results. Using the Ardent computer as a graphics supercomputer that rendered locally, meant you wouldn’t need to buy a Cray to get that kind of compute power and you didn’t need to buy an SGI workstation to render the results.

Even though Ardent didn’t last, it was a really heady experience to be involved with a real start-up of that size. I was the 24th employee to join the company and it was completely different from anything else I’d done up to that point.

While at Ardent, I did some modeling of the bus protocols to get the throughput we needed. Then, after just two months, they started parceling out the tasks involved in product development - designing the interface chip, the memory chips, the vector unit chips, etc. They asked me what I was going to do, and I said, “Well, what do you need me to do?” They said they needed design verification and I accepted the task.

My first job was to select the language. At the time it was Endot versus Verilog - VHDL wasn’t on the market. I did an evaluation of the two languages and chose Verilog because I liked it better. I knew we would need to write a translator from the netlists in the Valid format - Daisy, Mentor, and Valid were up and running in those days - and that’s how I got into design verification. I wrote behavioral models of the whole system - we could run an entire system simulation with my models.

I consulted the spec and the design engineers to write the behavioral models before we plugged in the netlist models. It was top-down design the hard way. At the time, people at Gateway told me that we were doing more sophisticated and complete modeling than any of their other customers even though the entire effort at Ardent consisted of just a couple of other guys and me. I never did know if they told that to all of their customers or not. That was in 1986 and ‘87.

The whole process was very interesting for me because it was starting to look remarkably similar to the software design methodology I had worked on in my dissertation back at Michigan. I knew that over the years that method had never gone anywhere in the software world, that people had talked about top-down design for software systems, but it had never really worked. However, here we were at Ardent doing exactly that with hardware design. In fact, Verilog was just a process-oriented simulation language, not all that different fundamentally from the language I had used in my dissertation.

I was writing a lot of Verilog in those days - we were all working on Sun workstations at that time. When we got our own machine working, anything that had been ported onto a MIPS platform, including VerilogXL, could be run on our machine. We were running other tools as well, of course.

Synopsys had come out in 1988, and we started to use Design Compiler. We got a beta of the product from Synopsys on a 1/4-inch tape. I just stuck it into the machine and ran it a couple of times. I wasn’t a hardware designer, so I didn’t actually use it, but I did install it and told everyone where it was on the system.

The excitement about Design Compiler was pretty high. Our group accepted it right away and was quite confident that it was the right thing to do. Like a lot of people, we knew that Design Compiler was a significant product. It was exciting to see that top-down design methodology for hardware was becoming a reality with a translation tool that could go from RTL to a netlist in a way that didn’t have to be done by hand.

Meanwhile, even beyond the technology, my experience at Ardent was really a life-changing one. I went from working 40 hours per week at Elxsi, to working 60-to-70 hours per week at Ardent. When I had interviewed at Ardent in 1986, my wife was on call with her Ob-gyn practice every other night and every other weekend. We had a 6-year-old at the time and I had to be at home with her when my wife was at the hospital.

So I told the Ardent guys during my initial interview that I couldn’t work on Saturdays. They grumbled a bit, but agreed. The first week I was at the company, Ben Wegbreit, the engineering VP, asked me to come in on Saturday just to show him what I’d been doing. So I did and I brought my daughter in with me. When I got there and looked around, absolutely everybody else was there working. I was amazed.

The next Saturday, I ended up coming in again, and as it worked out, I was there for 44 out of the next 52 Saturdays. A lot of that time, my wife was busy at the hospital delivering babies, so my daughter spent a lot of time at work with me. The whole thing was a complete culture shock to me.

People really worked hard at Ardent - Gordon Bell was there, Allen Michels was CEO, Ben Wegbreit was VP of engineering, and Jon Rubinstein was chief engineer. Richard Lowenthal, one of the best engineering managers I’ve ever met, was recently mayor of Cupertino. Steve Johnson who had written the Portable C Compiler at Bell Labs was there, as well. And Steve Blank, one of the most creative guys in the Valley, was VP of marketing.

We had a collection of extremely high-powered people at Ardent, all working 70 hours a week or more. Despite that, however, the company utterly failed. The machine was too complicated and too expensive. It was clear by 1989 that Ardent wasn’t going to make it, and when that situation became obvious, it was a downer for everybody.

From Ardent, I went to NeXT along with Jon Rubinstein even though I knew it wasn’t the place I ultimately wanted to be. The NeXT operating system was really nice (it turned into Mac OS X) and the machine was okay, but the company had 400 people, which was the wrong direction for me.

By then, I had figured out that over the course of my career, each company I had joined was an order of magnitude smaller than the previous one. When I was at DEC, they had 50,000 employees. Amdahl had 4000 employees, Elxsi had 300, and Ardent only had 24. NeXT was going in the wrong direction for me with 400 employees. I’d realized that my next company would have to be just me and one other person.

For that reason alone, I knew it wasn’t going to be a long-term proposition for me at NeXT. I wanted to be in an environment like at Ardent, but at a company even smaller than Ardent. Now I had to figure out how to get there.

Chapter 5 - 1990 to 1993

I was reading EE Times one day in September of 1990, and saw a 2-paragraph article that said a meeting of OVI [Open Verilog International] had been postponed. OVI had been established in May of that year by Cadence in order to put the Verilog specs out in the public domain. Seeing that article was the first I heard of OVI or that Verilog might be made public. Before that, the specs for the language were a Cadence trade secret and it was illegal for anyone else to sell a Verilog simulator.

Within 5 seconds of reading that article, I knew that this was the opportunity I’d been looking for. I’d been using Verilog for 5 years at that point and was really an expert with the language. In addition, I had a very low opinion of Cadence’s simulator, VerilogXL, because it was so slow running the behavioral models I wrote.

I had written a simulator for my dissertation and knew that an interpreter was nearly always 10 times slower than a compiler. I knew this was my opportunity to create a product to compete with VerilogXL. In fact, I felt that anyone with a reasonable education could do a better job of producing a Verilog simulator, but I also knew that if I tried and failed it would be beyond embarrassing. It was time to put up or shut up.

So I spent the next 8 months getting ready to start Chronologic Simulation based on my idea. While I was still working at NeXT, I wrote a prototype simulator at home from 11 PM to 1 AM every night for two months. When I finally got something that worked, I started trying to recruit people to join me in a new company based on the idea.

Through that process, I learned a lot about starting a company. At first we had three guys, but just before we incorporated in May 1991 one dropped out. That left Peter Eichenberger and me, but as far as I was concerned, this was going in exactly the right direction. A company with just two people.

It was just really exciting to start a company. We rented a little office in Los Altos - the office didn’t have any insulation and barely had any heat - and we worked there on our Verilog compiler. We were delighted when it began running and ran models 10 times faster than VerilogXL, sometimes as much as 50 times faster.

All of this was definitely a life-changing experience for me. I became a CEO and we had a product, VCS, all in about 17 months from the start of the project to our first customer ship. I had made a bet that I could make a real product, and had pulled it off. The fact that it was self-funded added to the sense of accomplishment.

At the time, nobody actually believed that Verilog had a future. Everybody thought that VHDL would take over, except the Verilog users. I was a user and I knew full well that nobody using Verilog was going to switch to VHDL unless he had to - Verilog was easier to use and there was no advantage to VHDL.

Still, I can’t tell you how many people told me to make a simulator for VHDL and not for Verilog. Andy Rappaport and Ron Collett both told me that point blank - do it for VHDL instead of Verilog because that’s where the future is.

Anyway, I tried to get advice from everyone that I knew as we started the company. I had lunch with a guy I had known at Ardent who was then a partner at Sequoia Capital. He was very helpful and when I told him about the company, he said I was right, they would never fund something like that. He also told me that they had just funded Redwood Design Automation and that Redwood had told him they’d be doing $100 million worth of revenue in 3 years - that’s how much market potential they had.

Well, by chance, I had an appointment with the VP of engineering from Redwood that very day, right after my lunch with the guy from Sequoia. I drove to San Jose for that appointment and had a nice talk with him. I asked him if he had really told the VC that they’d have revenues of $100 million within 3 years. He said yes, but that in reality they thought it would only be $50 million. When I heard that, I decided to be wary of Redwood Design.

It was such a telling moment to hear of someone giving a VC a number that was double what they actually expected to make. As it turned out, Redwood Design had a number of problems and we always loved to compete with them, because we beat them every time.

In any case, we never tried to get VC funding for Chronologic and so we were entirely self-funded. No one got paid for the first 15 months. But again, with my wife practicing medicine, I was okay. I have always said that my wife was the Chronologic VC.

Over all, we had 5 people at Chronologic who worked for absolutely nothing for a non-trivial amount of time - you really can’t do that anymore - but it paid off in the end because when we finally started making money with the company, we owned all of the equity. I was president and there was never any issue of external investors telling us what to do. As it turned out, that was a mixed blessing. It also gave the founders what I called “moral authority”. We had the right to make decisions about the company because it was our creation. We couldn’t be second-guessed, except by ourselves.

We released our product, VCS, in November 1992 after having had 3 beta customers for the product up to that point and it just took off!

We made $1 million in the first 2 months, paid out in just 5 checks from 5 customers including NeXT, SUN, Supermac, BBN, and Kubota Pacific. Our customers were mostly people that I knew - BBN was the only customer that didn’t have somebody there that we knew. We’d been living on a shoestring for so long that when I went to pay the bills for the company in the first week of January in 1993, the company account was down below $1000. A day later we got a check for $500,000 from Cyrix, and another million and a half arrived in January and February 1993. It was very exciting.

In any case, although we were seeing fairly big sales numbers at the outset, they represented a small number of transactions. So although for the first 4 or 5 months, we were doing pretty well, things then slowed down. We did have a sales guy and then started to build up a sales pipeline, but that took an additional 4 or 5 months to accomplish.

Chapter 6 - 1993

Most of the people that I knew through previous employers were in the design business, so at the beginning of Chronologic I was pretty naïve about the EDA industry. That situation turned out to play a big role in what happened next. As I didn’t have many contacts in EDA, I decided to join the OVI board of directors in mid 1993 - after being active on one of the technology committees of the organization, something I had done just to keep an eye on things.

However, I didn’t run for the board until I was absolutely certain I would be elected. There were usually the same number of board seats, or sometimes one less, as there were companies paying the full membership. Board members were determined by an election. There was a certain element of “popularity contest” in these elections, so there were people who would have been good to have on the board who were never elected, though this happened rarely. That’s probably the same in most organizations.

So in 1993, when I was confident of the outcome, I wrote a check to OVI for $10,000 and made an election speech - probably the first one ever given at OVI. Previously, OVI had made politically correct statements to the effect that Verilog was not in a language war with VHDL. Each language had its own place in the scheme of things. However, I got up and said I didn’t believe any of that. Verilog was superior, there was a language war going on, and I was on the Verilog side. After the election, Venk Shukla said, “It’s good to have a real Verilog bigot on the board.” I wore that title proudly.

Nonetheless, virtually all the analysts were still saying VHDL was it, that Verilog would die out. They were still sure that everyone would be switching over. I couldn’t convince anyone that it wasn’t going to happen, and they just kept asking me what I was going to do with VCS when VHDL dominated.

I had a particularly memorable interview with Gisela Wilson of IDC - who told me flat out that she didn’t believe our efforts had any future whatsoever. “You’re selling a fast Verilog simulator,” she told me. “But if all you have is speed what are you going to do when Cadence catches up?” I told her that I didn’t think Cadence would catch up. She wasn’t impressed.

In any case, by June of 1993 we had a repeatable sales cycle and we went to our first DAC. When you’re a company of 13 people, everybody goes to DAC and it was an exciting time.

DAC was in Dallas that year. When we got there and looked around, we saw for the first time that we really had a company and should start acting like one - not like an engineering group. The Chronologic board at that time consisted of Peter, Gordon Bell, and me - we had all met at Ardent. I talked to Gordon after DAC and he said we definitely needed some business help to grow the company.

So I called Allen Michels, the former CEO at Ardent, and asked him if he would be interested in being on my board. He said he’d come up from Phoenix and see what he thought about the company. He visited us for a day in Los Altos, and told me that the first thing we needed was a VP of sales. So we brought in a candidate to interview.

After the interview, Allen told me not to hire that guy, but to hire him. When I got over the shock, I made Allen COO for Chronologic, and while I still managed product development, marketing, and administration, Allen managed the sales people. I’d already hired Simon Davidmann to handle our European sales and we had a distributor in Taiwan and Israel, though not Japan. When Allen joined Chronologic in August 1993, he hired a sales guy in Massachusetts and two more in Silicon Valley.

He also hired a marketing director, Lisa Schmidt, signed up a Japanese distributor, and overall brought discipline to the sales process. Of course, given that it was Allen, it wasn’t a whole lot of discipline, but Allen knows how to handle people and how to handle a sales organization. By the end of 1993, we had about $5 million in sales, almost $2 million in the last quarter alone.

Still there were people who were sure that Verilog was going to fall into disuse - people like Dataquest and others who were doing surveys and talking to the management of EDA companies. But when we talked to the engineers directly, they didn’t say they were going to switch to VHDL at all. So even though we didn’t get much respect from the industry, the Chronologic business was doing just fine. VCS really was 10x faster than VerilogXL and 20x faster than the fastest VHDL simulator on the market.

Joe Costello was head of Cadence when Chronologic announced our first product. People thought that Cadence would respond by speeding up their own product, which of course they did. I actually went to a Cadence shareholder meeting after mailing a poster-sized copy of our first VCS ad to Joe Costello and went up to him afterwards to introduce myself. He was pretty cordial although he definitely knew about my product. He said the poster would be good motivation for his engineers. That’s something I doubt I would ever do again.

Lucio Lanza was on the board of Cadence at the time, and he told me later that he had recommended that Cadence acquire Chronologic. I didn’t believe the industry would have allowed them to, in reality, because it would have convinced everybody that Verilog wasn’t really an open language. That would have had the affect of Cadence being the only vendor with a Verilog simulator. I personally felt that we would always be competing with Cadence.

Chapter 7 - 1994

By the beginning of 1994, we were becoming relatively well known. We had done some advertising and established the fact that VCS was the fastest simulator on the market. That’s when people started believing that we really did have a future. Not only was there no reason to switch to VHDL, now there was a good reason not to leave Verilog.

As an aside, the DOD had mandated the use of VHDL back in the late 1980’s. Europe has always liked to follow standards - particularly back then - so when the DOD declared VHDL to be the standard, Europe pretty much embraced it. Europe was dominated by a few large companies and it was pretty easy for them to make policy for the region and enforce it. Even today, Europe is the last bastion of VHDL use. The same was true in Japan, although to a much lesser extent.

In any case, it took until the IEEE Verilog standard came out in 1995 to say that the tide had really turned in favor of Verilog over VHDL. OVI had launched its standardization process in 1994 and we participated actively in the committee that did the work. That standardization was OVI’s biggest achievement.

People continue to have a misconception about how IEEE standardization actually occurs, believing that it’s some kind of remote process. But that’s not true at all. You get approval to form a standard committee within IEEE and then you go about doing the work. In the mid 90’s, the IEEE 1364 Verilog committee looked just like the OVI language committee, same people but with different rules and the only ones participating were the ones with an interest in the future of Verilog.

For us at Chronologic, we had a vested interest in making sure that the undefined behavior of the language remained undefined. We didn’t want to have any behavior defined in the standard that would limit our implementation options. Race conditions result from a lack of event order specification in the language and typically we were doing those events in a different order in VCS than in VerilogXL. So we spent a lot of effort on what should be defined and what shouldn’t in the IEEE standard. The Cadence people didn’t seem to care - no one from Cadence joined the IEEE committee or regularly attended the meetings. The only real push back we ever got on that committee was from someone who wanted to clone VerilogXL and didn’t understand how you could do things differently from Cadence.

It was becoming apparent by 1994 that a significant change was occurring in the industry, and we started getting feelers about an acquisition. We got a low-ball offer from Synopsys, which we didn’t have any trouble turning down. A month later, we got a better offer from Viewlogic - that one was also not great - and we turned it down as well.

When Allen Michels joined the company, he didn’t know anything about EDA, so he called his brother-in-law, a stockbroker, to do research into the industry. The brother-in-law knew about Cadence, Synopsys, Mentor, Viewlogic, and Quickturn - the public companies. Allen came back to me and said, “EDA is a lousy industry. Each company has its day in the sun and then it’s done. You better make hay while the sun shines. The sun is shining now, so we either need to go public or be sold.”

We felt we were on a roll, but had no guarantee that it would continue. Allen was still hearing from all of the opinion makers that VHDL would overtake Verilog, and thought that within a year there was a good chance we would peak and then decline. So we started the IPO process for Chronologic at the beginning of 1994. We contacted an investment banker, I wrote a prospectus, we consulted with lawyers, and then we started getting the offers. Allen felt at the time that we would probably be acquired before going public. And, he felt that given a choice between going public or selling, getting acquired was the superior option.

In hindsight, had I known more about the industry myself I would have known it’s far better to go public before you get acquired. I can’t blame Allen - his advice was valid for a lot of EDA start-ups. He was an influential guy, but I should have been able to say, “No. Let’s not hurry.”

So we ended up telling Viewlogic we would accept their offer of $25 million in March 1994 and that’s when things got interesting. Later that day, we got a frantic call from Synopsys. We met with them on a Sunday morning and the meeting included about 11 people on the Synopsys side of the table and 3 of us on our side. We told them what Viewlogic had offered and said, “If you offer us $30 million, we’ll accept on the spot.”

It seemed like pure arrogance when they offered us the same $25 million that Viewlogic had offered. Synopsys hadn’t made a lot of acquisitions back then, and they had a reputation for being a day late and a dollar short. The fact that they offered the same amount as Viewlogic was a real problem for us, so we went back to our office, talked it over, and chose Viewlogic.

The deciding factor was that Viewlogic told us that we would continue to be an independent operating subsidiary. We’d remain in our same offices and there’d be no changes. The truth is that Synopsys was more honest with us. They told us that we’d become Synopsys, we’d be moving over to their offices and Chronologic would cease to exist. I felt afterwards that Aart de Geus [Synopsys CEO] had been much more honest with me at the time than Viewlogic was because that’s what actually happens in an acquisition. The acquired company ceases to exist - it’s only a matter of time - but I didn’t know that in 1994.

In any case, we signed a letter of intent with Viewlogic, as well as a ‘no-shop’ agreement. When I told Aart that we had signed with Viewlogic, he still wanted to talk although I couldn’t. A couple of days later Synopsys sent us an offer that was substantially better than their first offer.

My lawyer said to tell Viewlogic that, as a result, the deal with them was off completely - to tell them that’s just how business goes. Instead, when we informed Viewlogic of the situation during a phone call with Alain Hanover, CEO at Viewlogic. His response was to say that he’d sue each of us “personally for every penny you have” if we backed out of the deal.

Remember that at the time, both Gorden Bell and Allen Michels were on the Chronologic board of directors and both of them were really shy of lawsuits, having been through some unpleasant ones. They told me they didn’t want to be involved in any lawsuits, even though I didn’t really think it would come to that and neither did my lawyer. But I wasn’t very adventuresome either, so we decided to just go ahead and go through with the deal with Viewlogic. That, in turn, was the subtext of the next year that I ended up spending at Viewlogic.

You could ask, how often does someone find themselves in the position of starting a company, which becomes dramatically successful, negotiating with various people offering to buy the company, and eventually living through an acquisition? It’s not that unique, but it seldom happens to one person more than once. All told, the aftermath of the acquisition turned out to be the worst experience of my life.

By 1994, Viewlogic wasn’t growing the way they had been growing in the years prior to acquiring Chronologic. They knew that they were topping out, although we didn’t. Meanwhile nobody - including us - could see how great VCS’ growth potential was.

There were other problems. I realized only after the Viewlogic deal was over that in most acquisitions, the founder of the company being acquired or the guy who created the acquired tool rarely sticks around. Usually, that’s by mutual agreement. The person who has sold his company says it’s time to move on and the acquiring company wants him out of the way.

My situation at Viewlogic was more unusual. The whole reason we had chosen Viewlogic over Synopsys was because we believed we could continue on at Chronologic the way things had been before. I really wanted to keep doing what I was doing, I was happy doing it. As I say, that was the rare situation in EDA mergers.

Viewlogic, however - with Hanover and Gene Robinson, VP of sales, running the company - really didn’t want me there. Given a choice, they would have preferred that I leave. So I never knew at the time if the things they were doing were consciously done with the thought of driving me away or not.

I was definitely under stress while I was there. The notebooks that I kept at the time have an entry that says that the Viewlogic purchase was an okay deal - could have been better - but it was all right. But, it rapidly became apparent that it was not an okay deal.

It turns out that most of my battles with Viewlogic over the next year, following the acquisition, had to do with their sales people. We only had 6 people in sales and Viewlogic couldn’t see how those 6 could make any difference compared to their 80 sales people. But our 6 people sold more than all of their 80, because they focused only on VCS and knew the customers.

In addition, Viewlogic didn’t have any products in their portfolio that were as expensive as VCS was. A single license for VCS was $40,000, while Viewlogic’s most costly product at that time was only $20,000. The sales process for VCS was different from the other Viewlogic products.

Overall in marketing and sales, Viewlogic management didn’t want to do anything that didn’t have pay-off other than consolidating their power. Hanover was absolutely behind Gene Robinson and neither of them liked the idea of our having any autonomy at all.

Had I known more about EDA, none of this would have happened. I would have known that in EDA, there’s no such thing as an independent subsidiary. I would have seen that Aart de Geus was being honest in his dealings with us regarding that, and I would have known that Viewlogic did not have the potential that Synopsys did. Also, I would have realized that Chronologic was worth far more than $25 million.

But of course, it would have taken until the end of 1994 to do an IPO. We had projected our sales for 1994 at $10 million, but in fact we generated $16 million. So as it turns out by the end of 1994 we would have had enough revenue to do a credible IPO. We really were in that year 3 revenue “hockey stick” in 1994 where revenue takes off dramatically. It was a lost opportunity all the way around.

I’m pretty certain any IPO we attempted would have been pre-empted by a purchase by Synopsys. We would have been able to get at least double what we got for the company, particularly as we would have seen the spurt in revenue growth. I have a good friend who’s a VC and when I first started Chronologic, I told him my business plan for the company was to write a simulator and sell to Synopsys. It took a circuitous path for that to come to fruition, but that was the conclusion that was inevitable.

So 1994 was a pretty heady year and a terrible year at the same time. Just one month after the acquisition, it became apparent that I had made a terrible mistake. Viewlogic’s overall business was stagnating, just as we were beginning to gather steam. Their response was to try to consolidate more control over us, the response of an insecure management. By early 1995, Viewlogic had missed their Q4 numbers, their stock had plummeted and the company management was in disarray.

Chapter 8 - 1995 to 1998

By 1995, things were bad. At this point, everybody at Chronologic felt we’d been lied to and mistreated. Allen Michels left at the time of acquisition. I called him and asked him what to do and he sent me to see a lawyer in L.A. who told me I had a case.

We had a meeting of all of the management at Chronologic. The lawyer told us, “If you file a lawsuit against Viewlogic, the remedy will be to nullify the acquisition.”

So we notified Viewlogic that we wanted changes. Then things went from bad to worse. In May ‘95, Viewlogic filed a lawsuit against me personally, then we filed our lawsuit. Then they added to their lawsuit everybody at Chronologic who was a plaintiff in our lawsuit against them. When that happened, the entire management of Chronologic, short of Peter, left within a single week.

At any rate, our lawsuit wasn’t a good idea and it didn’t get very far in court. It turns out there was a clause in the acquisition agreement that said any representations by Viewlogic not included in the acquisition agreement had no effect. That’s a standard clause in these things and we couldn’t get around it.

Even today, it’s still annoying that someone can misrepresent things legally. My advice to anyone in a similar situation would be to get all your understanding in writing in the acquisition agreement, but that’s easier said than done. At the time, I never thought I’d have the opportunity to take advantage of these lessons, however I have told other people who have benefited from our experience.

In any case, as part of the acquisition, Viewlogic wanted me to sign a 4-year non-compete agreement and I said this one’s not worth fighting about.

By 1995, I regretted signing the non-compete. I definitely felt that there was an element of coercion in the non-compete agreement that I had agreed to. I should never have signed it. In fact, if I had challenged it in court, it would not have held up because the time span was so much longer than the norm. But I didn’t mind too much at the time because I wanted to try some other things and I didn’t think I wanted to be in the EDA business again anyway. Even then, I didn’t consider myself an EDA guy. I’d been an EDA guy at that point for not quite 3 years. After that, it took me a long time to decide that EDA really was the industry I wanted to be in.

The years after my departure from Chronologic were more difficult than I could have imagined - they were just really hard. At first, those of us who left Chronologic formed a consulting company in trying to move forward. We rented a little office down the street in Los Altos from where we had been in business as Chronologic, and we worked doing verification projects for various people.

Eventually, however, Mike McNamara, Todd Massey and Chong Guan Tan went off and founded SureFire, at which point we closed the consulting company.

The web was beginning to blossom at that time, so I thought I’d write an on-line Verilog course. I was of the opinion at the time that that was the modern way to write a book. I ended up spending about 6 months writing the HTML-based training course, thinking I would sell on-line access to it. Although the commercial aspects never amounted to anything, it was a pretty decent effort. It was hosted for a long time on the ISD Magazine website, but they gave it back to me when the magazine folded. Today I pay the hosting fees, the course is free, and it still lives on-line. Surprisingly enough, it still gets about 600 registrations per month.

Meanwhile, I was only 47 and still fairly energetic - I certainly wasn’t ready to retire. So I went off with a guy I knew from the Ardent days. He was an ME and we started a company together doing MCAD software. His idea was that there was no MCAD language comparable to Verilog as a description language. But after two years of effort, we decided the idea was just a research project and not a business proposition. It was a good distraction for two years, but the biggest benefit I got from it was the realization that I wanted to go back to EDA.

During the Chronologic years, I had driven my daughter to school every day as she moved through the 5th, 6th, and 7th grade. Our conversations were usually about the company. She and my wife knew all about the company as it was growing and were deeply involved. Our family dinner table conversation was all about the growing business. After it all ended, and despite the MCAD project, I went into a really deep funk and my family knew it.

Finally, my wife said that anything would be better than what had been going on with respect to my attitude about things. I said I couldn’t just pull a switch and change my mood, so she said I should start another company if that’s what it would take - it was either that or move out. The non-compete agreement I had signed with Viewlogic was about to expire, so with my home life as motivation, I decided it was time to start CynApps [Cynthesis Applications, Inc.].

Chapter 9 - 1998 through the boom

CynApps changed everything. I didn’t want to write another Verilog simulator, nor to start another company like Chronologic, but I did want to try again. I really wanted to be a significant player in the industry, raise my sights, and do something more dramatic than Chronologic.

Andy Goodrich was a friend from Michigan and a graphics chip designer. He showed me a C++ class library he had written to use for hardware design. I thought this had promise, so I spent a couple of months in the beginning of 1998 experimenting with it to decide if it was really viable.

I needed access to some real hardware models, so I asked Jon Rubinstein - who was by then the VP of engineering at Apple - if he could help. Apple had just laid off a large part of their engineering staff and had plenty of spare workstations and cubes, so he gave me a contractor’s badge and access to their design group. It was their darkest time, just before the iMac was introduced and the company turned the corner, but it was quite pleasant for me. I convinced myself that you could design real hardware in C++ and this was worth pursuing.

Andy was up for a new venture, so I then talked to Randy Allen about the idea. He said we could get rights to the Kubota C Compiler, which he had received personally when Ardent folded. He said we could turn the compiler into a high-level synthesizer and combine it with the C++ class library. And that’s what we did.

The three of us founded the company - Andy Goodrich, Randy Allen and myself. I’d known Randy from Ardent and Chronologic. He’d been hired by Synopsys, after his time at Chronologic, to develop a VCS clone - which was legal because he’d never been asked to sign a non-compete agreement. That project ended when Synopsys acquired Viewlogic and got VCS. Randy became our VP of engineering at CynApps. He’s now the CEO of Catalytic Compilers.

So the tale of CynApps unfolded. We could see that designing at a higher level of abstraction, in C++, was going to succeed eventually, so we oriented our activities at CynApps around that concept. To do that, we needed to have enough products to be the dominant player in the front end of the design flow. Doing a single point tool like we’d done at Chronologic was interesting, but I wanted a product family that we could build a franchise around - a whole new design methodology.

I used to be fond of saying that if you wanted to create a significant EDA company, there was the Synopsys model and the Cadence model. You can plan to do a Cadence-type business model, but you can’t plan to do a Synopsys-type business model. In the Synopsys model, you had to develop a tool that’s key to the design flow and become a monopoly. In the Cadence model, you had to collect enough components of the design flow to be a major player. My goal with CynApps was to make a new Cadence - I wanted to do the acquiring this time.

To do that, I knew we needed to do things differently than at Chronologic. First of all, this time I took investment money. That had become a necessity by 1998 - people’s attitudes about start-ups had changed and you couldn’t get people to work for nothing at that point. Also, although my situation was different because my wife continued to grow her medical practice and provide household support, my co-founders at CynApps couldn’t afford to live on nothing.

We also needed to add people quickly, but people wanted stock in the company and they wanted to be paid as well. Those were the rules of the game in 1998. So, I had to look for investors. There were two investors high on my list, Prabhu Goel, the founder of Gateway, and Lucio Lanza, a partner at USVP. Prabhu wasn’t interested, but Lucio was - USVP became our VC for the first round of funding.

Actually, raising money isn’t hard if you’ve had a success before. I got a number of angel investors along with Lucio and USVP, and Lucio joined the board. So we started with one institutional investor and 7 private investors. Altogether we got $1.8 million, which seemed like a lot compared to the zero dollars we started with at Chronologic.

Lucio and all of the subsequent investors were very supportive. Contrary to the popular conception of VCs being controlling and rapacious, I never had that experience. We were lucky to have matched our business with VCs who understood the EDA industry. Lucio had been an early EDA participant at Daisy and then Cadence, and he was always sympathetic to our efforts. He understood our development needs and never lost faith that, if we succeeded, there would be a big payoff.

When we were ready to get an office and get started, we got help from Nvidia. I had known Chris Malachowsky, one of the founders of Nvidia, from my Chronologic days. When Chronologic was up and running, I had gotten a call from Jen-Hsun Huang, the founder of Nvidia, who said if I would give them some Verilog licenses, they’d pay me later when they got their funding. Cadence wouldn’t give them a break, but I did, and true to their word, 6 months later they paid me. They became a great customer.

Nvidia was the first all-VCS shop. Jen-Hsun and Chris were really grateful for my help at that time and we were always friendly afterwards. In 1998, they offered to give us free office space for CynApps in the Nvidia building. I’ve always thought that was one of the striking things about the Valley. The good things you do often come back to you.

We stayed at Nvidia for about 5 months, but they were growing so fast, they eventually needed the space. So, we went off to an office over on Mission College Blvd. in Santa Clara in 1999. We got a fairly nice office at a reasonable price and repeated a theme that you often saw in the Valley, a bigger office than was necessary at the time with unused space. In our new offices, we gave space to a company that USVP was funding. Procket was a 2-man, next-generation router company that ended up being a really high flyer during the boom. Procket turned into our first customer at CynApps.

I’m quite sure that this sort of thing can only happen in the Valley - not in North Carolina or Texas.

Initially, we thought we’d sell the Cynlib library for $1000 a license. Then the open source movement caught on and we decided that in the era of open source, selling Cynlib at that price just wasn’t worth it. So, we made Cynlib, our C++ library, open source. We released Cynlib in September of 1999. I told Synopsys we were going to release it under an open source license, but they weren’t interested in doing that with SystemC, which was very similar to Cynlib.

Our release of Cynlib may have been the first open source EDA product released by an EDA company, and it did have an impact on SystemC. Synopsys talked to us about joining the SystemC effort about two months before we released Cynlib, but there were personality issues with the people who would have had to work together and we decided to go our own way. In hindsight, this was a mistake.

In October 1999, Synopsys released SystemC under a community source license, not open source. Eventually Synopsys did release a true open source license for SystemC, but only after a lot of sturm and drang.

We had several other products, aside from the free class library, including a translator from Verilog to C++. We knew we wouldn’t make a lot of money selling these products, but until the synthesis product was ready, this was what we had to sell. Meanwhile, a few customers were buying our methodology and we would say, “For your project, we’ll charge you $100,000 and give you all the software we have.”

It turns out the most useful of the products was the free Cynlib library. However, none of the customers complained. They were buying methodology, and actually got their money’s worth.

So at that point was CynApps a product or a services company? I think calling yourself a product company at a certain phase in the life of a company is really a statement of intent more than anything else. I always used to say that when you don’t have a product, you sell services.

Verisity had gotten started selling methodology and so had CoWare. They got paid to have their AEs go into a customer’s site and stay there, but it wasn’t for several more years before their software was robust enough to sell without the AEs. I used to be critical of this model, but it’s a valid way to get a business started.

Lucio and Gordon, who was again on my board, urged us to acquire a small behavioral synthesis company in Pittsburgh called Dasys at about the same time as we raised a second round of financing. This added some of the best behavioral synthesis experts in the world to our engineering team. Sam Lee from Infinity Capital led the second round. He’s another VC who really understands the EDA industry, having been a user himself at LSI and then the first VC at Ambit.

Lucio and Sam stuck with us through thick and thin. That is what led us to our eventual merger with Chronology [not to be confused with Chronologic] which Lucio himself engineered. The merger was a good thing for the company, and importantly allowed us to get additional financing. Also through the merger, we got some very good people. The disappointment of the merger was that the Chronology verification products, which we thought would provide a strong revenue stream, didn’t survive the bust.

Meanwhile, as it turned out, the high-level synthesis and technology part was much harder to do than we had thought. The synthesis development effort took much more time and resources than we had anticipated and our plans for the other products in our suite of tools had to be pared down. Without high-level synthesis, design in C++ isn’t very compelling, and the other products couldn’t stand on their own.

By 2001, we were selling methodology, but not much. We were working on the synthesis product, but it was still a long way from customer-ready. With the merger with Chronology in 2001, we were now Forte and we had verification products to add to our methodology sale. We had also added a new CEO, Jacob Jacobsson. Then the bust hit.

Chapter 10 - From boom to bust and back

With the merger of Chronology and CynApps we had about 65 employees, but after the bust it was apparent we couldn’t support that many people. We went down to about 30. Meanwhile, sales of the lower priced verification products were falling off, while our more expensive methodology sales were going to zero.

At the height of the boom in the summer of 2000, we had moved into offices on Technology Drive. At that point, we were paying top dollar for a lot more space than we needed, but our expected growth didn’t happen. In 2002, we told the landlord that we would go broke if we had to keep paying rent at the agreed to rate. Our landlord said, “Tough.”

So we just stopped paying the rent and basically got kicked out. We were given three days to vacate and in those three days, Jacob, our CEO, found better quality office space three blocks away and ended up paying less than a third of what we had been paying. It may not be as much of a fire sale today as it was then, but ours was a typical story in the Valley in 2002.

When you’re in product development, it’s not so bad to live through a downturn. Nobody’s buying anything, but it doesn’t matter, because you don’t have anything to sell. We had expected to make sales from other things than the synthesizer, but because of the downturn our existing products simply stopped selling.

By the middle of 2002, we weren’t selling any of our existing products, and the synthesizer was clearly where our future was. So we cut everything else off and concentrated on that. The value of focus is something you learn over and over again in this industry.

Importantly in 2002, we were able to raise another round of funding, which we did by saying the money was just going to the development of the synthesizer. And that’s when we really started turning the corner. By Q4 of 2002, we got a purchase order from Sony and then things started to look up. The product, which was now called Cynthesizer, was still very immature, but we were getting to the point where it worked.

Today the Cynthesizer really works, we have 38 employees, and we are still relatively careful with hiring. We would be even smaller except for all of our customers in Japan. Innotech told us last year they were going to stop distributing non-Cadence products, so we hired some AEs and the Innotech sales guy and formed a KK. As a result, we have more guys in Japan at this point than a company at our stage normally would.

What’s coming up over the next 18 months? Well, it looks to me like consumer electronics is going to continue to do well, and most consumer electronics is done in Japan. Having said that, there’s competition for the Japanese coming out of Korea and Europe. We have customer engagements in all those places. We don’t yet have any customers in China.

The U.S. market is somewhat softer in C-based design as yet, because the U.S. isn’t doing designs in general that are as algorithm intensive. The design organizations in the U.S. that are doing algorithm intensive designs developed their own C-oriented design methodologies several years ago, and aren’t ready to change over to a standardized one. They don’t yet see the value, but they will. Are the existing EDA companies working to inhibit that move? I doubt it. I don’t believe in conspiracy theories - people in this industry generally don’t do that.

There is one last portion of my story to tell. Right after Viewlogic acquired Chronologic, Joel Paston introduced me to Rajeev Madhavan. Joel had met Rajeev on one of the OVI committees. Rajeev told me that what Chronologic did to Cadence, he could do to Synopsys. He had access to code from BNR and needed some funding to make a synthesis product to compete with Design Compiler. So I introduced Rajeev to Allen Michels and Gordon Bell, and we put together the first seed round for Ambit. I stayed in contact over the next year with Rajeev and went with him to various fund-raising meetings. Rajeev had to spend an inordinate amount of time raising money to keep the company going. We got to be good friends.

When Rajeev left Ambit, it was another one of those contentious events. I ended up trying to mediate between the two parties for several months. Eventually Rajeev sued and Ambit counter sued. So much for my political skills. When Rajeev started Magma I encouraged him because I thought that getting on with his life was the best thing for him to do. Another lesson from Chronologic.

Epilogue - Multiple Myeloma

I was diagnosed with Multiple Myeloma in the fall of 2001 by way of a blood test, which showed elevated protein with a monoclonal protein spike. The web said at the time that the median prognosis for the disease is 33 months from time of diagnosis. That prompted me, among other things, to start writing my memoirs, which will cover the 1980’s, and 1990’s in Silicon Valley. I’ve heard a number of things said about that era that I know to be incorrect and many of the details of the story are beginning to be lost. I want to get this stuff written down, so that the part of the record that I know about is recorded accurately.

I had a bone marrow transplant last fall because even though at that point I wasn’t symptomatic, the cancer level was dangerously high. A transplant is the normal treatment if you’re healthy enough to go through it. It takes 4 or 5 months to prepare by taking various drugs, and then you have the transplant followed by stem cell re-infusion. It’s pretty amazing that it works, but is a blunt instrument at best and only produces a remission of a few years.

The transplant was done at City of Hope National Cancer Center in Duarte, in Southern California. They’ve got a nice program there with a set of apartments on the grounds. The whole treatment was done as an outpatient procedure, where I walked over from the apartment each day for the 4 or 5 hours it took per session. I had a Hickman catheter inserted in my chest, which I found to be the most annoying part of the whole thing. With my wife taking care of me, I made it through the transplant with no complications and no infections, which is relatively rare. It took me about four months to fully recover from the transplant.

I exercise regularly, riding a bike once a week - I actually started riding in the 1980’s - and work out several times a week. I’m probably in better shape now than I’ve ever been.

When we were researching options with respect to Multiple Myeloma, my wife looked around for an oncologist. The one we went with had another patient who was the chief scientist at Finisar, a local optical component company. He was only 39 when he was diagnosed - just after the company had gone public - and he decided he would start a fund to raise money for Myeloma research.

He got $750,000 per year for 3 years to fund three different research organizations looking for treatments for the disease. He raised money primarily from a few of the winners from the Finisar IPO. I told him I knew some winners too, and that perhaps I could raise some additional funds. So I started working on that project around the end of 2001. The Myeloma Research Fund, the MRF, has been administered since its inception in 2001 by the Peninsula Community Foundation. It’s an extremely efficient way to fund cancer research.

There are three groups being funded by the MRF - Dr. Ken Anderson at the Dana-Farber Cancer Center in Boston, which is associated with Harvard, Dr. Bill Dalton’s group at the H. Lee Moffett Cancer Center in Tampa, and Dr. Jim Berenson, at Cedars-Sinai and UCLA, who has recently established the Myeloma and Bone Cancer Research Institute in L.A. The fund-raiser being hosted by the EDA community on September 15th in San Jose will go toward the research those three groups do. The idea for the September event was Venk Shukla’s from Magma.

I’ll be at the event and it may be a little awkward because I look pretty healthy. I’m afraid I won’t look like a very good poster child for cancer research. People who know me will only notice a difference in that my hair is now curly. It grew back that way after the transplant. Otherwise, I look perfectly normal.

There are a lot of new drug treatments being researched right now for Multiple Myeloma including drug cocktails that involve thalidomide and dexamethasone in lieu of chemotherapy. They’re effective, but have a limited duration of effectiveness. They have their share of side effects, but they have fewer global side effects than chemotherapy drugs.

There are other drugs as well, including Velcade, a proteazome inhibitor to which about 75 percent of patients respond. None of these drugs remain effective for a long time, but while they are, the results are encouraging. I’m convinced that these new types of drugs are the future of cancer therapy.

My wife and daughter have been very supportive through all of this. It’s been a tremendous benefit to me that my wife is a doctor. I turn to her for advice and information, and her ability to navigate the health care system has certainly been a benefit for me. It hasn’t been easy for her, though, since she knows all the bad things that can happen and has a tendency to assume that they all will. I just trust in research and hope I’ll be one of those who outlives the distribution curve.

I’ve been about as lucky as you can be with my family in all aspects of my life.

[Editor’s Note: My conversations with John Sanguinetti have been among the most interesting I’ve ever participated in. I appreciated his candor, and wish him continued success in his battle with Multiple Myeloma.]

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Commerce & Industry

3Plus1 Technology Inc. announced details of the company and a multiprocessor architecture for next-generation hand-held systems, which has been used as the basis for a series of CoolProcessor devices for low-power mobile-system manufacturers. The architecture is in a sub-100mw processor implemented in a standard 130-nanometer low-power CMOS process. Jan Rabaey, professor at U.C. Berkeley and director of the Berkeley Wireless Research Center and the MARCO Gigascale System Research Center, is serving as a technical advisor to 3Plus1. The company also announced it has joined the ARM Connected Community, is working with CoWare Inc. to demonstrate the CoolProcessor in the CoWare simulation environment, is working with Hellosoft Inc. towards its first silicon, and is working with Sonics Inc. towards the implementation of complex IP.

Actel Corp. and Mentor Graphics Corp. announced that the new version of Mentor Graphics’ Precision RTL Synthesis tool is producing “significantly higher performance” on designs that use Actel’s ProASIC Plus FPGA family, including designs with up to 30,000 logic tiles. The companies are reporting that customers using Precision should expect, on average, an 18-percent improvement in clock frequency over previous versions of the software. The Precision RTL Synthesis tool is integrated into Actel’s Libero 6.0 IDE.

Agilent Technologies Inc. announced new wireless testbenches, sources, and measurement capabilities for its Advanced Design System (ADS) 2004A EDA software. Per the Press Release: “Traditionally, nonlinear and distortion analysis and measurements rely only on discrete-tone figures of merit. Discrete-tone stimuli and measurements may prove inadequate since real-world sources have different signal characteristics such as power statistics. For accurate verification, designers must validate the performance of their circuit under real-world stimuli and with the system measurements that current standards require. The new ADS 2004A capabilities include configurable DSP-based modulated sources with RF and baseband outputs, a set of measurement expressions and a range of wireless testbenches for 3GPP, WLAN and TD-SCDMA technologies.”

Airgo Networks announced a tapeout using Sequence Design’s PowerTheater to automate the power analysis for Airgo’s new 802.11g chips. Derrick Lin, Senior Director of ASIC Engineering at Airgo Networks, is quoted: “PowerTheater predicted power usage within 10% of silicon for our AGN100BB chip. We achieved this level of accuracy by leveraging PowerTheater’s innovative RTL and gate-level analysis capabilities. Since switching to PowerTheater’s accurate and automated RTL power estimation, Airgo designers have minimized power early in the design cycle and verified that power budgets are met.”

Aldec, Inc. announced the release of Riviera 2004.08 with a direct simulation kernel connection with SystemC, which the company says creates an efficient system-level co-simulation environment for next generation design and verification methods. Eric Seabrook, Product Marketing Manager at Aldec, is quoted in the Press Release: “Traditionally, only early adopters have had the advantage of designing with the latest methodologies offered to the market. Aldec aims to change that with its release of Riviera 2004.08 by offering a completely integrated, mixed-HDL and SystemC solution at an affordable price.”

Ansoft Corp. announced availability of SIwave v2. The product is a full-wave electromagnetic field simulator, which analyzes signal-integrity and power-integrity effects in PCBs and IC packages. The new release includes: power plane impedance, signal net analysis, resonant mode analysis, Spice export, robust meshing, automated geometry cleanup, unlimited undo and redo, a decoupling capacitor model library, and a frequency-dependent model for dielectric. Per the Press Release: “SIwave’s proprietary full-wave, finite-element technique allows designers to characterize simultaneous switching noise (SSN), inter-symbol interference, power and ground bounce, resonances, reflections and coupling between traces and power/ground planes.”

Apache Design Solutions announced that ATI Technologies Inc. has adopted Apache’s full-chip dynamic physical power integrity flow. ATI says it is using Apache’s RedHawk-SDL for cell-based dynamic voltage drop analysis and NSPICE-PI for global I/O simultaneous switching output (SSO) verification. Per the Press Release: “ATI found traditional methods of static-only IR-drop analysis to be inadequate for their high-performance graphics processor designs. They saw that Apache’s ability to perform full-chip dynamic power analysis, including the effectiveness of decoupling capacitance, and the verification of global I/O SSO, was important for their current and future designs.”

ARC International announced that SanDisk Corp. has licensed the ARC 600 RISC processor core and MetaWare development tools for use in their next-generation flash storage products. Yoram Cedar, Senior Vice President of Engineering at SanDisk, is quoted in the Press Release: “In planning for our next-generation product lines, we had very strict size and performance requirements. After seeing that the ARC 600 core could be configured to optimally meet our size, area and performance needs, the choice was easy.”

Applied Wave Research, Inc. announced the integration of Analog Devices’ analog-to-digital converter models (ADIsimADC) with AWR’s Visual System Simulator 2004 (VSS) design system. The companies say the combination of capabilities will allow RF and baseband design engineers using VSS software to develop wireless communications systems by modeling the actual performance of Analog Devices’ ADCs in a system block diagram. Brad Brannon, Staff Applications Engineer in the High-speed Converter Group at Analog Devices, is quoted in the Press Release: “Every converter genre exhibits unique ‘real world’ behavior patterns, and this tool helps minimize the design surprises that tend to result from basing performance assumptions strictly on data sheet specs.”

Applied Wave Research also announced the Microwave Office 2004 design suite for next-generation RF and microwave circuit designs. The design suite integrates 3D planar EM simulation with circuit simulation and layout tools, permitting arbitrary physical structures to be embedded within linear and nonlinear circuit simulations. James Spoto, AWR President and CEO, is quoted: “The layout process for RF and microwave design drives overall circuit performance and must be closely connected to electromagnetic simulation tools. The Microwave Office solution … provides everything designers need to take an idea from concept through simulation and directly into physical implementation.”

Cadence Design Systems, Inc. announced new PSpice-based simulation technology for the company’s OrCAD product line. The technology integrates Cadence PSpice with MATLAB and Simulink products from The MathWorks. The company says the new PSpice SLPS interface, co-developed by Cadence and Cybernet Systems in Japan, allows co-simulation of electrical and mechanical systems.

Meanwhile, Cadence Design Systems and the Shanghai Research Center for Integrated Circuit Design (ICC), founded by China’s Ministry of Science and Technology, announced the availability of the ICC-Cadence CPU/DSP SoC reference methodology. The methodology includes the Cadence Encounter digital implementation platform, Incisive functional verification platform, and CoWare software tools for ESL design and verification.

Cadence Design Systems also announced that ATI Technologies Inc. selected the Cadence Incisive Palladium acceleration and emulation system to verify some of its highly complex designs. Dave DiOrio, Vice President of Engineering at ATI, is quoted in the Press Release: “ The Palladium system provided the features we needed to meet stringent product delivery schedules and increased our ability to test our ASICs and application-level software.”

As well, Cadence Design Systems announced that NVIDIA used Cadence’s Incisive Palladium system to “significantly reduce” its verification time for NVIDIA’s new GeForce 6800 graphics processor. Brian Kelleher, Vice President of Hardware Engineering at NVIDIA, is quoted in the Press Release: “Previously, our verification process would take about two to three days per turn - the cycle for bug detection, identification and the repair process. With Palladium, we average two to three turns per day.”

And, Cadence announced that TelASIC Communications, Inc. got a 10x simulation performance increase in the course of developing the “world’s fastest analog/digital converter.” Cadence said that TelASIC used its Virtuoso UltraSim FastSPICE simulator to verify TelASIC’s TC1410 ADC. Don Devendorf, CTO at TelASIC, is quoted in the Press Release: “Using Virtuoso UltraSim, our designers were able to run multiple simulations on the entire ADC circuit in a few hours, producing accurate results and reducing our verification cycle from weeks to days.”

Finally, Cadence Design Systems announced it has helped enable Stretch Inc. to meet an “aggressive time-to-market goal for a high-performance software-configurable processor design.” Stretch says it benefited from the Cadence Digital IC design flow and libraries from TSMC.

Carbon Design Systems announced it has joined 0-In Design Automation’s Check-In Partner Program. The companies say that the assertion synthesis capability of 0-In’s Archer Verification System, when coupled with Carbon’s DesignPlayer engine, will provide “design bug identification without sacrificing runtime performance.”

Carbon Design Systems also announced it has integrated its DesignPlayer engine with Virtutech’s Simics Instruction Set Simulator, which the companies say will enable customers with processor-based designs to execute operating systems and application-level software “on a fast and accurate model of a chip or system.” The companies are also announcing that this integration allowed Sun Microsystems to boot its Solaris operating system on a Simics-DesignPlayer model of their design.

Per the Press Release: “DesignPlayer is a soft model that is accurate to the hardware-cycle and register accurate. Unlike behavioral models or C models generated from an ideal specification, DesignPlayer behaves exactly like the hardware with all its errata. Hardware designers now have the cycles they need to run complete regression suites before chip tapeout. Software designers can finally test and debug their code on a high performance, cycle accurate, linkable model. Customers get an executable specification that contains the silicon errata for system integration and test.”

Denali Software Inc. and Mentor Graphics Corp. announced a collaboration whereby Mentor Graphics will use Denali’s PureSpec verification IP product to confirm its PCI Express IP core is compliant with the PCI Express and Advanced Switching Interconnect interface standards, and interoperable with other system designs as well.

Denali Software also announced that Cray Inc. has selected Denali’s Databahn memory controller IP cores and MMAV verification IP software for Cray supercomputer product development. Cray says it plans to use Denali’s Databahn IP in the design of the DDR-SDRAM memory system, and will use Denali’s MMAV product for modeling and simulating the interactions between chips and external memory devices for design verification and performance analysis.

eInfochips Inc. announced the availability of a high-performance DSP-based keyboard, video, mouse (KVM) interface product, which the company says is designed to be scalable and customizable. The KVM product supports all major server platforms, provides remote access to servers using standard IP connections, and enables management of servers from the boot-up process as if the network administrator was sitting next to the managed device. The product also features a frame compare and image compression algorithm with techniques for noise filtering and video compression implemented on the DSP, browser-based control, field upgradeable design, and compatibility with standard KVM.

Forte Design Systems announced that Sanyo Electric Co., LTD has adopted Forte’s Cynthesizer SystemC behavioral synthesis tool for the implementation of Sanyo’s designs for consumer semiconductor devices. Fumiaki Nagao, Senior Staff member at Sanyo Electronic, is quoted in the Press Release: “Forte’s Cynthesizer has demonstrated its ability to quickly synthesize high-quality RTL from complex algorithms without sacrificing quality of results. We expect Cynthesizer to help cut months off our design cycle, while providing us with a complete and automated verification flow.”

HDL Works announced the release of version 5.2 of EASE, the company’s design entry environment for VHDL, Verilog, and mixed-language designs for FPGA and ASIC. Per the Press Release: “Synthesis and simulation tool independency enables the user to select his most favorite tools while setting-up a complete design flow … Many improvements have been made in this new version. These changes include Tcl driven version management with support for ClearCase, RCS and Synchronicity Design Sync, Verilog 2001 support and a new project browser. “

LogicVision, Inc. announced that the company is aligning with UMC to provide UMC customers with access to LogicVision’s wafer yield product. Frank Wen, UMC President, is quoted in the Press Release: “We believe this alliance will establish a new standard for rapid diagnosis of process issues associated with the increased design and process complexities of advanced technologies, allowing a faster ramp to full silicon yield.” From the Press Release, as well: “Because UMC is already shipping 90-nanometer silicon with good yields to customers, it was LogicVision’s leading foundry of choice for implementing this new program.”

Mentor Graphics Corp. announced that its ATPG tool, FastScan, has been selected for UMC’s 130 and 90-nanometer digital reference flow. Ken Liou, Director of the Design Support Division at UMC, is quoted in the Press Release: “We worked closely with Mentor Graphics to develop the ATPG portion of our reference flow. Using FastScan, we are able to achieve excellent test coverage which ensures we are providing our customers with high-test quality for their designs.”

Mentor Graphics also announced availability of the Capital Harness Systems product suite release 2004.1. The company says the new release includes: dynamic electrical simulation, which provides real-time feedback to design engineers; design abstraction, which allows engineers to visualize electrical designs at various levels of detail; design comparison, which provides graphical representation of connectivity or properties differences between related designs; enhanced harness drawing features, such as display of composite wire tables, display of terminal materials and display of nested dimensions for complex bundle configurations; and new integrations with third-party MCAD tools.

Optimal Corp. and Applied Wave Research, Inc. (AWR) announced what the companies are calling “the first commercially-available three-dimensional (3-D) full-wave EM extraction design flow.” The AWR-Optimal methodology is intended to assist with signaling issues characteristic to wireless communications designs operating from 1 to 50+ GHz, and combines Optimal’s O-Wave product with AWR’s Microwave Office and Analog Office design suites through the AWR EM Socket interface.

Len Perham, Chairman and CEO of Optimal, is quoted: “As technology alliance partners, AWR and Optimal demonstrate the ability of two vendors with leading-edge technology to collaborate successfully in order to provide intrinsic value to the customer, in this case, the microwave and RFIC designers who are encountering increasingly challenging circuit problems at the advanced semiconductor technology nodes.”

Silicon Canvas, Inc. announced the release of Laker-AMS version 6.1. Highlights of the release include: the new licensing scheme transition from Rainbow to FlexLM, improved hierarchy navigator usage, added Tcl/Tk scripting language support, a streamlined Spice-out procedure, and a new interface to the Laker full-custom layout tool. Per the Press Release: “Greatly increased interest and a desire to shift from a traditional polygon pushing methodology to the schematic driven layout flow methodology make the new release attractive to a broad range of existing customers and new prospects.”

Synopsys, Inc. announced that IPCore Technologies Corp., described as “China’s pioneer pure design foundry”, has signed an agreement to adopt Synopsys’ Galaxy Design and Discovery Verification platforms, and the company’s DesignWare IP portfolio as IPCore’s primary internal design flow. Under the terms of the agreement, Synopsys Professional Services will expand its delivery capability in China by selectively utilizing IPCore on a subcontracting basis.

Synopsys also announced that Samsung Electronics Co. Ltd. has signed a multi-year license agreement for Synopsys’ DesignWare IP. Under the terms of the agreement, Samsung is licensing the DesignWare Cores IP portfolio, which includes the PCI Express and USB families of digital cores and analog PHYs. K.H. Kim, Vice President of ASIC Business at the System LSI Division of Samsung Electronics, is quoted in the Press Release: “Outsourcing select IP lets our engineers focus on the value-added portions of the design such as quality, features and performance. This agreement with Synopsys will add industry-leading PCI Express and USB technology to the variety of proven IP cores provided by Samsung’s ASIC business.”

Finally, Synopsys announced the availability of the DesignWare USB 2.0 On-The-Go (OTG) PHY (Physical Layer) Core targeted to TSMC’s 90-nanometer, 130-nanometer, and 180-nanometer processes as well as an extension of the Hi-Speed USB 2.0 PHY Core product line to the 90-nanometer process node. The new OTG PHY handles HNP (host negotiation protocol) and SRP (session request protocol), which are the OTG-specific differences between the Hi-Speed 2.0 and the new OTG standard. Synopsys says DesignWare USB 2.0 OTG PHY is “the industry’s first 90-nanometer USB OTG PHY Core … is interoperability tested and jointly certified with Synopsys industry leading digital USB cores, thus providing a complete drop-in solution with lower cost, form factor and risk.”

Tharas Systems Inc. announced the Tharas Flexible On-demand Rental Collaborative Environment, T-FORCE, which is an on-site subscription verification program.

Per the Press Release: “T-FORCE, with subscription rates starting at $10,000 per month, is the most cost-effective subscription program on the market for accelerated functional verification of complex ASIC and system designs. T-FORCE, developed for customers with flexible verification needs, provides best-in-class accelerated verification at an affordable price. Projects with fluctuating verification capacity needs can increase or decrease hardware-assisted verification as necessary. The entry level of the program gives a customer the ability to verify up to 4-million gates ... Purchasing hardware-assisted verification technology is a huge capital expense that carries the very real possibility of obsolescing that investment every other year. T-FORCE virtually eliminates the fiduciary concern with on-demand access to capacity and performance throughput at an affordable price. The on-site subscription model builds acquisition credits towards future purchases.”

TriCN announced that it has released an area-efficient single lane (x1) PCI Express PHY. Currently the product is available in the TSMC 130-nanometer process. Per the Press Release: “TriCN’s PCI Express PHY x1 is the first to achieve a size of only 0.68 sq. mm for the PIPE core.”

Ron Nikel, Co-founder and CTO at TriCN, is quoted in the Press Release: “While today’s announcement marks another significant ‘industry first’ for TriCN, it represents an even bigger win for semiconductor designers who are constantly seeking to reduce area consumption, especially in consumer applications ... Based on our analysis of the market, we believe our single lane PCI Express PHY is nearly 40 percent smaller than the nearest competitor.”

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Economics & Finance

EDAC’s Numbers - The EDA Consortium’s Market Statistics Service (MSS) announced that EDA industry revenue for Q1 of 2004 was $995 million, a 6-percent increase over Q1 2003. * Services revenue increased to $76 million, a 31-percent increase over Q1 2003. * Semiconductor intellectual property was $78 million, a 15-percent increase over Q1 2003. * EDA license and maintenance revenue was $840 million in Q1 2004, a 3-percent increase over Q1 2003, and 84 percent of the total reported revenue. * Computer-aided engineering generated revenue of $470 million in Q1 2004, a 6-percent increase over Q1 2003. * PCB and multi-chip module layout revenue was $85 million in Q1 2004, a 5-percent increase over Q1 2003. * IC physical design and verification revenue of $285 million was down slightly from $288 million in Q1 2003.

Synopsys Inc. reported revenue of $281.7 million for the third quarter of fiscal 2004, a 6-percent decrease compared to revenue of $300.4 million for the third quarter of fiscal 2003. For the 9-month period ended July 31, 2004, revenue was $861.5 million compared to revenue of $860.5 million for the same period in 2003. On a GAAP basis, third quarter of fiscal 2004 produced a net income of $41.8 million, and GAAP net income for the 9-month period ended July 31, 2004 was $102.7 million, compared to $105.1 million for the same period in fiscal 2003.

ARM Holdings plc and Artisan Components, Inc. announced that the companies have entered into a definitive agreement under which ARM will acquire Artisan. Details include:

* Warren East, CEO of ARM will continue as CEO of the combined companies, with Lucio Lanza, Chairman of Artisan, and Mark Templeton, President and CEO of Artisan, joining the Board of Directors of ARM as a non-executive director and an executive director, respectively. Templeton is expected to enter into a service contract with the company with effect from completion of the transaction.

* The completion of the transaction is expected to occur in Q4 2004 and is subject to ARM and Artisan stockholder and regulatory approvals and other customary closing conditions.

* Based on closing prices for ARM’s ADSs as of August 20, 2004, the implied value is $33.89 per Artisan share, representing an aggregate consideration of approximately $913 million.

* As of June 30, 2004, under U.S. GAAP, Artisan had revenues and profits after taxes in the previous 12 months of $82.9 million and $17.3 million, respectively, and had net asset value of $205.1 million, of which $140.4 million was cash, cash equivalents and marketable securities.

* ARM has agreed to pay a break-up fee to Artisan of approximately $18 million payable upon certain termination events under the transaction agreement. Alternatively, Artisan has agreed to pay a break-up fee to ARM of approximately $31 million or $18 million, depending on the nature of the termination event, payable under the transaction agreement upon certain termination events.

EMA Design Automation announced the formation of the EMA Consulting Services Group to “make available high quality, enterprise-wide OrCAD Capture CIS implementations. Key factors are library data management and interfaces into the customer’s MRP system to leverage items such as cost information, parts availability, and preferred part lists. The EMA Consulting Services Group also provides web-based CIS deployments.”

FishTail Design Automation, Inc. announced the signing of exclusive distribution agreements with both Saros Technology Ltd. in Europe and Advinno Technologies in Southeast Asia. The company says the distributors will provide sales and support to customers in their regions.

Fujitsu Ltd. and Cadence Design Systems announced a “Premier Design Partner” agreement, under which the companies say they will create advanced SoC design environments. The worldwide Fujitsu Group and all of its design centers will have access to tens of thousands of licenses covered by the agreement. In addition, Cadence will provide personnel support to the Fujitsu Group, Fujitsu and Cadence will jointly develop methodologies that merge design and process technologies, and the companies plan to jointly expand their global business collaboration to markets such as in the U.S. and China.

Kilopass Technology, Inc. announced that Global UniChip Corp. (UniChip) has signed a corporate agreement to add Kilopass’ embedded non-volatile memory (NVM) technology, XPM, to UniChip’s IP portfolio. In addition, UniChip says it has joined Kilopass Technology’s Design Services partner program.

Jack Peng, Founder, President and CEO of Kilopass Technology, is quoted: “We are delighted to establish this partnership with UniChip. UniChip has a strong team of industry veterans with the necessary experience and capabilities customer seek in SOC design service providers. They will help accelerate the adoption of our XPM technology into designs created for high volume products.”

MatrixOne completed the acquisition on Synchronicity Software, Inc., a move first announced in June at DAC 2004. Per the Press Release: “The combination of MatrixOne and Synchronicity provides a breakthrough solution for any company that has high-value electronic content in their products.”

Mentor Graphics Corp. announced it has acquired Palmchip Corp.’s Parallel and Serial ATA IP business, which the company says “extends Mentor’s position as the leading provider of communication standards-based IP by adding Palmchip’s industry-leading ATA IP to its broad portfolio of standards-certified cores, and increases its IP offerings for the growing storage market.”

Mike Kaskowitz, General Manager of the IP Division at Mentor Graphics, is quoted in the Press Release: “When we look to augment our IP portfolio, we look to those vendors that uphold the same high standards we do. This acquisition enables us to offer our customers and Palmchip’s IP customer base a broader selection of certified cores for the storage market that provide them with a smooth transition as their design needs evolve.”

MVC Capital announced that 0-In Design Automation, Inc., one of MVC Capital’s portfolio companies, has been acquired for stock plus a multi-year earn-out by Mentor Graphics Corp.

Details per the Press Release: “As a result of the acquisition, the Fund is receiving 685,679 shares of Mentor Graphics stock, with a current market value of approximately $7.5 million. Of these shares, 603,386 shares are freely-tradable and will be valued daily by the Fund. The Fund is currently valuing these shares at $6.6 million. The balance of the shares are required to be held in escrow for a one-year period and, under the terms of the transaction, the Fund’s rights to receive all or a portion of these shares are subject to certain contingencies. While the current market value of the escrowed shares is approximately $900,000, the Fund has initially placed no value on them due to these contingencies. The terms of the acquisition also include a multi-year earn-out, based upon future revenues, under which the Fund may be entitled to receive additional cash consideration.”

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Politics & Government

Accellera announced that its Board of Directors has approved Accellera’s Property Specification Language (PSL) standard version 1.1 as an Accellera design verification standard, and that the organization has begun the IEEE standardization process for PSL with the IEEE Corporate Advisory Group.

Per the Press Release: “The PSL 1.1 effort focused on refinement of PSL 1.01 and on alignment of syntax and semantics between PSL and SystemVerilog Assertions (SVA) where possible. In addition to correcting errata discovered in PSL 1.01, PSL 1.1 incorporates new features and user-driven enhancements that benefit EDA vendors and users alike. The PSL extensions subcommittee focused on common requests from users, including the addition of a SystemVerilog flavor, adoption of SVA built-in functions, addition of labels on directives, as well as report clauses on certain directives, relaxation of some flavor macros, and refinement of operator precedence.”

Accelerated Technology announced that it has joined the Eclipse Foundation, a software tool vendors consortium, which was “formed to foster the expansion of a unified development environment and wide product integration. Eclipse is an open platform for tool integration built by an open community of tool providers.”

Novas Software, Inc. has announced that the company “continues to drive support for the Accellera SystemVerilog standard with hardware description language analysis (also known as linting) that builds on existing support for the language across the Company’s debug solutions. The Novas nLint tool now provides basic rule-checking capabilities for all SystemVerilog 3.0 design constructs to enable the early detection of design problems in IC development methodologies. The availability of SystemVerilog linting aids the adoption of unfamiliar, advanced coding constructs, which is critical as SoC designers get up to speed with the new language.”

Synopsys, Inc. announced that its DesignWare Endpoint Controller IP core for PCI Express is the first such IP to pass compliance tests from the PCI-SIG. Tony Pierce, PCI-SIG Chairman, is quoted in the Press Release: “PCI-SIG appreciates Synopsys’ development of IP enabling designers to accelerate the development of innovative products based on the PCI Express standard which greatly helps member companies to shorten their development cycle. We are pleased to see that Synopsys is included in the first group of member companies whose PCI Express-based product has passed the compliance tests and is on the Integrators List.”

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Early Bird Registration Open
2nd International System-on-Chip (SoC) Conference
WHEN and WHERE: November 3 & 4, 2004, Crowne Plaza Hotel, Silicon Valley -- Milpitas


AccelChip Inc. announced it has appointed Vin Ratford as President and CEO. Ratford has served on AccelChip’s Board of Directors since 2002, and comes to AccelChip from Giga Scale Integration Corp., where he was President. Ratford will continue to serve as a director for Giga Scale. Prior to Giga Scale, Ratford was President of deepTECH Consulting Group, Vice President at Virage Logic, and COO of the Microtec Division of Mentor Graphics. He also held numerous positions in the System Test Division of Teradyne.

Applied Wave Research, Inc. (AWR) announced that its Analog Office design suite has been selected for the 2004 LSI of the Year Award in the Design Environment/Development Tools category. The award is sponsored by Semiconductor Industry News and Reed Exhibitions Japan.

ARM announced the opening of its Beijing office, which according to the Press release will: “focus on supporting partners and leveraging strong growth opportunities in this fast-developing market.” ARM opened its first Chinese office in Shanghai in 2002. ARM also announced four new license agreements with CoreTek, HOPEN, Semiconductor Manufacturing International Corp., and ZRRT.

Chartered Semiconductor Manufacturing announced an award from the Singapore Ministry of Manpower presented at the Annual Safety Performance Awards ceremony in July. The company says that all of its fabrication facilities were cited for “outstanding safety performance, demonstrating effectiveness in safety management systems and company-wide support toward implementing long-term environmental sustainability programs.”

Esterel Technologies has named Chip Downing as CEO for Esterel Technologies, Inc., the U.S. arm of Esterel Technologies, and Vice President of Embedded Market Operations. Most recently, Downing served as Vice President of Business Development at Validated Software.

Magma Design Automation Inc. announced that Pete Teshima has been named Vice President of Finance, reporting to Greg Walker, Magma CFO and Senior Vice President for Finance and Administration. Teshima has 24+ years of experience in EDA and other technology industries, has served in financial management and operational roles, and has been involved in numerous M&A transactions. Most recently, he was as COO for Hier Design Automation, and served as CFO at InTime Software, Cyclone Commerce, Avanti, InterHDL, and High Level Design Systems. Teshima has a BS in Commerce from Santa Clara University.

Nassda Corp. announced Dermott Lynch has been promoted to Vice President, U.S. Sales, and Susanne Hampe has been hired as the European General Manager. In these new positions, both Lynch and Hampe report to Nassda CEO, Sang Wang. John Yelinek, who joined the company in January 2000, has been appointed Vice President of major accounts from his previous role as Vice President for Worldwide Sales. Yelinek will continue to focus on expanding business with Nassda’s largest and most important customers who require its advanced nanometer verification and analysis technology.

Dermott Lynch was formerly the director of Northwest sales at Nassda, and has 18 years in EDA. Previously, he was an executive at Sente until its merger with Sequence Design, worked at Quad Design, Ashling Microsystems, Elcor Associates and Contec Microelectronics. Susanne Hampe was formerly European Sales Director for Barcelona Design. Previously she worked as General manager for Central Europe for Simplex Solutions. After Cadence Design System’s acquisition of Simplex, she became business development manager for Europe at Cadence.

Sagantec announced that Hillel Ofek has been named President and COO, reporting to H.R. Johnson, Executive Chairman of the Board of Directors and CEO of the company. Before joining Sagantec, Ofek managed his own consulting company. He currently holds several advisory and board of director posts. Previously, he was General Director of Software Products at Actel, a Vice President at Dynachip, a Director at Amdahl, and an Executive at Silvar Lisco.

Ofek is a past member of the IEEE/Computer Society Governing Board and a member of the ACM and IFIP’s Working Group 10.5. Ofek was General Chairman of DAC and Chairman of several of its Executive Committees, including Finance and Program. He participated in the pioneering stages of VHDL development, served as President of the VHDL International Consortium, and as a member of the VIUF Advisory Board. Ofek began his career with 20 years at IBM. He has a BSEE from Technion, Israel Institute of Technology, and an MSEE from New York University.

Sequence Design announced that Jerry Frenkil has been named CTO. Most recently, Frenkil served as Sequence’s Vice President of Advanced Development. Frenkil joined Sequence when the company merged with Sente in 2000. He was one of the founders of Sente, has published papers on IC and low power design, and holds several patents on circuit design and design automation. Prior to co-founding Sente, Frenkil was an independent consultant focused on IC design. He also held management positions at VLSI Technology and Mostek. Frenkil has a BSEE from the University of Texas.

Silicon Dimensions Inc. announced that the company has opened a new office in San Jose to house the company’s expanded sales and AE staff.

Stelar Tools, Inc. announced Robert Grossman has been named Executive Vice President of Sales and Marketing. Grossman comes to Stelar from Novas Software. He has 25+ years of sales and marketing experience with various EDA companies including Tharas Systems, Vast Systems, and Mentor Graphics. Over the course of his career, he has been involved in a number of start-ups, from early stages through to acquisition or IPO. Grossman has a BE from Cooper Union University and an MSEE from the University of Massachusetts.

Synplicity Inc. has named Gary Meyers to be President and COO, reporting to CEO Bernie Aronson. Meyers will manage worldwide sales and be responsible for the company’s marketing and engineering functions, where previously he was Vice President for Worldwide Sales. Prior to Synplicity, Meyers was at LSI Logic, serving in various managerial roles, and an ASIC designer at TRW (now Northrop Grumman). Meyers has a BSEE from the University of Maryland and an MBA from UCLA.

Xilinx, Inc. recently announced a $330,000 donation to the Fudan University School of Microelectronics. The company says, “A full complement of the Xilinx programmable logic solutions - including design software, silicon and reference boards - will be incorporated into course curriculum and workshops focused on advanced digital electronic design. The Xilinx University Program (XUP) donation will be used to equip a new Fudan-Xilinx lab with more than 50 workstations, and various multi-media and demonstration boards equipped with Xilinx devices.”

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The IEEE Custom Integrated Circuits Conference takes place October 3 -- 6, 2004 at the Caribe Royale Resort Suites, Orlando, Florida. CICC has an exciting lineup of educational short courses, 146 technical presentations in 30 technical sessions, three exciting panel discussions, and vendor exhibits. CICC offers something for everyone involved with chip design, EDA tools, IC-enabled system development, and semiconductor process technology. Register by Sept. 17 for the early registration fee. Visit for the complete program and registration information.

Festivals & Fairs

Chartered Semiconductor Manufacturing will host several technology forums, on September 16 in San Jose, CA, and November 10 in Yokohama, Japan. This year’s forum is titled: “New Perspective. New Performance. New Choice,” and the focus will be on “smart” platforms, which present customers with technology, design and economic choices required at 90 nanometers and below. (

EDA Consortium Panel - EDAC’s Emerging Companies Committee will host a panel on September 22 in Santa Clara, CA, on the topic of “EDA Trends that You Can’t Ignore - How Short Product Cycles Are Stirring the EDA Industry.” The moderator will be Charles DiLisio, President at D-Side. The panelists will include MontaVista’s Kevin Morgan, Philips Semiconductor’s Robert Payne, SVB Alliant’s John Savage, and Intel’s Greg Spirakes. (

Gartner Dataquest Semiconductor Industry Summit - A revival of the Dataquest Semiconductor Conferences held in the 1970’s and 1980’s, the year’s event will take place on September 13 and 14 at the Fairmont Hotel in San Francisco, CA. (

ISSP Structured ASICs Seminar - Hosted by NEC Electronics America and Synplicity, the event will take place on September 16 in Minneapolis, MN, and will provide a forum for discussion of alternatives to cell-based ASIC and FPGAs. The two companies will address how to “Hit a Home run with ISSP Structured ASICs: Your Turnaround Time Advantage from 150 to 90 nanometers.” Attendees are invited to attend a ballpark-style dinner reception followed by a Minnesota Twins/Chicago White Sox game sponsored by NEC, Synplicity, North Pole Engineering and Matrix Marketing Group. (

IEEE ITC - the International Test Conference 2004 will be held in Charlotte, NC, from October 26 to 28. ITC is dedicated to the electronic test of devices, boards and systems, covering the complete cycle from design verification, test, diagnosis, failure analysis, and process and design improvement. (

MUSIC Panel - The Magma Users Summit on Integrated Circuits will take place on September 17 at the Santa Clara Convention Center. The day’s panel will be moderated by EETimes’ Richard Goering and will include ESNUG’s John Cooley, Magma’s Premal Buch, Virtual Silicon’s Barry Hoberman, PDF Solutions’ John Kibarian, Mentor’s Joe Sawicki, and OpenSilicon’s Naveed Sherwani. (

NanoCool Seminar - Hosted by Sequence Design, Artisan Components, and Sun Microsystems, and including presentations from Novas Software, Golden Gate Technology, and Tensilica - organizers say this series of seminars will explore logical and physical low-power design methodologies, RTL power estimation, power debug, voltage-drop analysis, power modeling, power grid design and leakage reduction. The NanoCool initiative is a collaboration between semiconductor designers, EDA tool vendors, IP companies, and library suppliers, to provide a complete power integrity flow at 130-nanometer and below. For times and locations, please see the website. (

SAME 2004 - The 7th annual Sophia Antipolis Forum on MicroElectronics will take place on October 6 and 7 in Sophia Antipolis, France. Organizers say the event will be helping the industry “Face the Future of Microelectronics.” The meeting will include tutorials and technical papers. (

Cadence Users Group & SOC Conference 2004 - The conference is sponsored by the IEEE Circuits & Systems Society and will take place from September 12 to 15, at the Hilton Hotel in Santa Clara, CA. Organizers say the conference provides a forum for sharing advances in SOC technologies and applications, and includes three days of technical papers and a full day of technical workshops. (

ESL Methodologies Seminar - Aldec, Inc. announced that it will host a 5-city seminar series on system-level methodologies. Topics will include SystemC methodology and implementation strategies for incorporating the language into current design flows. There will also be hands-on training using SystemC and an opportunity to practice writing high-level testbenches. The conferences are slated for Boston on September 16, San Jose on September 30, Dallas on October 12, and Austin on October 13. (

Wescon/2004 will be taking place at the Anaheim Convention Center from September 21 to 23. Organizers say this year’s show will address the total design and supply chain for the electronics design, manufacturing, and distribution process. The conference will include keynote speakers, panel discussions, and workshops related to the products and services featured in the exhibition hall pavilions. (

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Peggy Aycinena authors EDA Nation, serves as Copy Editor on Chip Design Magazine, and owns and operates EDA Confidential at She can be reached at

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