Contents

Editor’s Note
History & Geography — "Bookends at Cadence—Fister & Costello"
Commerce & Industry
Economics & Finance
Politics & Government
Citizenry
Festivals & Fairs

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Editor’s Note

October is a time of change. Spring and summer have come and gone, and autumn heralds the coming of winter. More than any other time of year, people tend to be looking back wistfully to the seasons just past, while also looking forward with determination - preparing themselves for the challenges and vigorous sport of the winter months.

This month's lead article is about Cadence Design Systems, its future and its past - topics seemingly analogous to the season. The first interview here is with the newly appointed Cadence President & CEO Mike Fister, who is looking forward to the challenges and vigorous sport of building Cadence to be an even bigger player in the EDA industry and the larger semiconductor supply chain.

The second interview, the other part of the autumnal experience, is a conversation with the original CEO of Cadence, Joe Costello, who has just been named by the EDA Consortium as this year's winner of the prestigious Phil Kaufmann Award. When people speak about Costello's era, it's often in wistful terms as his tenure at Cadence from 1987 to 1997 coincided with the glory days in EDA, those years when the industry was expanding rapidly and optimism abounded with regards to the business and technology potential in electronic design automation software.

Voices of the past and future not withstanding, my own impression in talking to these two men is of their remarkable similarity. They are both agile in their thinking, seemingly unfettered by conventional (read "formulaic") wisdom, and both bring a great deal of intense energy and confidence to the table - confidence in technology, confidence in a future based on that technology, and most importantly, confidence in their own abilities to shape and influence that future by shaping and influencing the technology.

They both seem equally able to say to the pending season of winter - 'Bring it on!

Meanwhile, no matter that the economic news out of EDA, and some companies in particular, is hardly something to write home about - the number of technical announcements coming out of the industry rages on! So grab that cup of java and come along for the ride.

Peggy Aycinena
Contributing Editor

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History & Geography

"Bookends at Cadence—Fister & Costello"

* Prologue - The official word from Cadence

You can skip this bit if you already know that...

Mike Fister is President and Chief Executive Officer of Cadence Design Systems, Inc. Prior to joining Cadence, he spent 17 years at Intel Corporation, where he was most recently Senior Vice President and General Manager of the company's Enterprise Platforms Group.

Previously, Fister served as Vice President and General Manager of the Performance Microprocessor Group, where he managed Intel's IA-32 processor development organization and was responsible for the design, development and marketing of IA-32 processors, including the last versions of the Intel486 and the entire line including the Pentium Pro, Pentium II, Pentium III, Celeron, Pentium II Xeon, and Pentium III Xeon processors. Prior to this role, Mike held many other product development positions at Intel and has a long legacy of successful technology development and product delivery.

Fister is a graduate of the University of Cincinnati where he received a BS and MS in electrical engineering in 1977 and 1978 respectively. He spent his early years in a variety of executive and engineering management positions at Wyse, Machine Vision International, and Cincinnati Milacron. He currently sits on the Board of Directors of Autodesk Corporation.

Chapter 1 - Mike Fister

Mike Fister was named President & CEO at Cadence this past spring, just in time for DAC 2004. Fister's appointment caused quite a stir at Cadence, and in the industry, because change always does. We spoke by phone on September 15, 2004 - the same week as the Cadence Users Group Conference in San Jose.

Q: How is the Cadence Users Group Conference going?

Fister: [Very well], although I've only been able to be there for a little bit this week.

Q: Presuming you've moved in from out of the area to take over at Cadence, how has the relocation to San Jose gone for you?

Fister: Our home is in Portland, Oregon and [we still have children in the area], so I'll be commuting down to San Jose. [But it doesn't matter where I am because] I'm very much a work-all-the-time person, which means I work about 100 hours a week. But, I've always loved what I do and I'm very committed to our Cadence team, [so it's not going to be a problem].

I'm also a big bicycle rider. I ride a lot in Oregon, and it's great that there's lots of biking in this area as well.

Q: Where were you born and where did you grow up?

Fister: I was born in Savannah, Georgia, but I grew up in Cincinnati. My father was a EE - he was infamous in the [design of the] instrumentation in jet engines at GE. So, I grew up wanting to be like Dad. I attended the University of Cincinnati, where I got my BSEE and my MSEE.

[While I was in college], I did an engineering co-op at Intel, where I worked on the 4040 and 4004 and got a lot of notoriety for some special stuff I did on those products when they were first coming out. So, after I got my MSEE, I went to work for Intel full time.

[At one point], I left Intel to join a small company working in the area of robotics. We were working on machine vision and the problems were pretty intriguing. We developed non-traditional computer architecture approaches [to the problem] based on an abstract algebraic approach - not a statistical approach. It's the computer architecture guys who [usually succeed in applying] these techniques to problems like traditional data processing, vision, and control.

After I left the start-up, I went back to Intel to develop microprocessors and micro-controllers, where several thousand of my buddies and I built product lines that you're probably typing on right now. We pursued the thoughtful evolution of products through to today's Pentium III and IV, which allowed us to change the world. I'll never be able to fully show the total strategy behind all of that - you've just got to meet guys like me and some of my colleagues to understand. It was a very considered evolution of those products - different products [to address the needs] of many different types of users.

We always planned the microprocessors at Intel with architectural innovations that would also show a product continuum. The why and the sense of the product flows were always implicit in the success of those product lines, because in the design process, it's the approach you're taking and knowing what kind of product you want to build. And, of course, always at the root [of everything] is a design method that's dependent on the human dynamic in the tools.

All of that left me interested in going out and trying to help our industry supercharge the inevitable, which is to be increasingly more dependent on the computer. You can see how I'm a logical guy to a fault.

Although I was trained as an engineer, I've always been more interested in how people think as opposed to how to get things done. My old man derives a formula [to solve a problem] when he needs it, whereas I develop a theory. Electrical engineering training is at the root of everything I've done, even in this adventure into EDA. Because in the design process, it's the approach you're taking which is just as much a part of the thing as what kind of product you want to build.

As the world continues to evolve, the complexity and dynamics increase - we'll have larger and larger devices, devices with crazy performance [metrics], and products that combine mixed signal with analog/digital stuff.

All of us are going to increasingly benefit from the companies in our industry. I have an organizational approach for integrating that experience and [helping to push that process forward].

Q: At the Gartner/Dataquest Semiconductor Conference this week, Intel CTO Patrick Gelsinger said that everything in design revolves around Platform, Package, and Power. Would you agree?

Fister: For me, it's more about the social issues.

Q: At that same conference, Gartner Analyst Jim Tully closed by summarizing the three major themes he saw at work in the industry - Consumer, China, and Consolidation. What do you think?

Fister: Yes, there is going to be further consolidation in the industry. At Cadence, we're very thoughtful about that and the roles we are going to play in doing that. We're busy trying to integrate disparate technology and [looking to achieve] a better, holistic tool set rather a tool for each domain.

And while we're bragging about our demonstrable [technology], we're also walking the talk about Open Access. [The ability to develop tools in an open environment promises] incredible rewards to the industry. We want to be the driving force behind Open Access - to drive our tools for interoperability, which may [actually] help drive our competitors' tools. So, it's a bold move for us, because we're daring ourselves to be good. But it's promising a new era in open industry participation - and a breath of fresh air.

Also, there are issues about licensing that we're addressing. There are a number of different business models that can go in a number [of different directions]. I'm very open to the view of trying the different things that will link us to the manufacturing ability of our customers, so we're also very concerned about] tools for manufacturability. [Many customers] have an idea that yield is more than the raw counting of dies, but [also in considering] the goodness of the product. However, you don't know how good it is, until you get to the end of the [manufacturing] loop. That's the reason why design is inexplicably linked to manufacturing.

A company must never stand still in its technology or its business model. Our leadership in the industry means we're going to lead the industry and [at the same time] compete with ourselves. We will be innovating not only in the technical areas, but also in business areas with relationships that we've formed with key customers - relationships, which are very methodical, while also allowing us to sustain our [leadership in the industry]. [All in all], we are all about trying to help our customers.

By the way, this may sound like a Cadence commercial, but it really isn't. [Laughing]

Q: How do you feel things are going in the EDA industry?

I'm a business pragmatist. I believe product lines should be the drivers - I'm not a technology zealot like some. At Intel, we were always careful about the evolution of the technology and timing of the technology, so that the product flow and the timing were very thoughtful. From Intel's standpoint, it's the product guys who are the most powerful manifestation of what the industry is doing.

In the EDA industry, we [frequently and unfortunately] get people to delve into unbelievably deep detail about stuff that doesn't have a lot of relevance to what the customer is trying to do. My fiber is [all about] looking at the problems that people are trying to solve - it's about a timing process synchronization. I want to look at the domains that will be the most relevant to users of our tools, [particularly] on a two-to-three year cycle.

As an example - somebody's attacking a mixed-mode design with analog, digital, high performance specs - there may be a technology that's preserved or reserved to do all of that, but laboring through and debating whether our technology is better than somebody else's ability to solve the problem is largely an academic exercise. I want to train our technology into a useable tool kit that attacks the application domain. I want to see [our customers getting] more value out of the holism of the approach - an entirely differently mentality.

In the quest for leadership in EDA, however, some people have decided to base their [position] totally on a technical foundation that sounds like techno-babble to customers. In fact, however, EDA is all about time to market, managing complexity, and garnering value for the integration of what our customers are doing.

When the Apple guys built the best MP3 player in the world, they weren't trying to say that they wanted to integrate this magnetic storage with that interface and [so on]. They were saying they wanted to create a package [with these specific features] that would fit into a pocket. They worked with the rest of the industry to integrate [specific technologies] to create a product that was smaller, sleeker, and cooler. And that's where our efforts should be directed.

I want us [to work with the customers, who are working] with hierarchical flows at 90 nanometers. It's a Fister passion that we're going to be in that thin strata of people, who actually talk to our customers' customers, because those are the penultimate "What?" guys. They'll give us the insight as to whether or not our tools and technology are relevant. We'll benefit [by adding] more value to our tools, our technology, and our services.

Q: When will Cadence buy Wind River?

Fister: [Big laugh] I haven't thought that much about it.

Q: A VC recently told me that the Cadence organization of late has been nothing short of a train wreck - a place of internal squabbles and contentious fiefdoms. How would you respond to that criticism?

Fister: Cadence has grown by acquisition and that's the [source] of some of that criticism. People wonder if we're going to be able to fully integrate those acquisitions - so it's fair to ask those questions. But, our post-acquisition retention characteristics are very strong and very high. Ping Chao is one of those guys and is a key member of the acquisition team.

I would tell you that, coming into this thing, we could be a better-integrated team, but we've got some very positive things going on at Cadence. My reputation is one of being a special person who's able to [communicate] inclusivity, camaraderie, and teamwork.

So, watch the situation at Cadence play itself out. We're going to bulk up the team in a few spots, and I know you're going to be impressed with the [additions to the team]. The people we're bringing in will be a great complement to the [existing structure], just like I was a complement to a great team.

Oh yeah - and we're going to have fun!

* Chapter 2 - Joe Costello

Joe Costello and I last chatted back in October 2001, as I was writing up an article profiling his career. This time around, when we spoke by phone in late September 2004, the conversation was prompted by Costello having been selected to receive this year's Phil Kaufmann Award. Here are the highlights of our visit.

Q: So, Joe - why the Kaufmann Award and why now?

Costello: [Laughing] Well, I got this message from my assistant that [Synopsys CEO] Aart de Geus had called. So I called him back, not having any idea of why he wanted to talk to me. Of course, all kinds of things go through your mind, so when I reached him and he said, 'I've been chartered to tell you that you've been chosen to receive the Phil Kaufmann Award,' I was definitely surprised!

I haven't been involved in EDA, except tangentially, since 1997. Although obviously, I still think about the industry a lot because I've been on several Boards of Directors since then, and am still sitting on Barcelona's Board. Also, I continue to be on the Engineering Advisory Board at U.C. Berkeley assisting [Engineering Chair] Richard Newton.

Anyway, my receiving the Kaufmann Award is one of those really great things for me. I was just beaming when Aart told me and thinking what a tremendous honor it is. It's fantastic! I think that in the group of people who have received the honor before me, it's kind of like Where's Waldo. And I'm Waldo!

Q: Are you as disaffected today with the EDA industry as you appear to have been in the past?

Costello: I'm really not thinking about EDA much these days, but I think it's true today even more than before. I don't think electronic design automation gets the value it deserves, because it still creates more value than it gets. Between the tools, the technology, and the services in EDA - people are still trying to work out the value equation.

It's not horrible, though - it's not ridiculously undervalued. I mean, we don't pay our schoolteachers anywhere near enough. Those services are horribly undervalued! EDA is not as undervalued as that, but still…

Q: Can the EDA industry evolve and improve?

Costello: Yes, it can evolve, although right now the market's a bit stagnant. It feels like it's sliding laterally, but things can happen during times of big change - which happens when markets emerge with a new view of things.

How do we grow? I still believe the way to change growth and value in an industry, is to deliver solutions, not just tools and technology. The difference is really understanding the customer's problems inside and out. What are the core objectives of your customer's business? What are their hopes and dreams on the one side, and their anxieties on the other side?

EDA is still coming at things with, 'We've got pliers, and here's a saw, and here's a plumber's helper.' But none of the customers are saying, 'I've got a hammer question.'

The customers are saying, 'We have a problem that requires a comprehensive solution.'

Q: When will the EDA industry link their financial success to that of their customers?

Costello: I agree. If you wanted to crack these things, tie your revenues and your profits to your customers' successes. That would change the equation and create opportunity for growth. Essentially what the EDA industry does today is, they limit their upside by protecting their downside. How many EDA vendors have their payments tied to the actual success of their customers?

When I pushed into services at Cadence, it was when we were trying to make that happen, although there's a limit there. In electronics and other industries, you may actually get push back in the other direction, because sometimes customers act the same way. You see them saying, 'I'll have my smart guys take your technology, and we'll do it on the cheap.' So, you see it in both directions.

The 90's were definitely the go-go years for software. Boards of Directors loved their companies to sell software. It was like selling drugs, because there were such high margins. You could sell very expensive packages with big labels like ERP, CRM, EDA, and you could make a lot of money that way through expensive sales channels and high prices.

Selling services is something different, however, and people are looking for something different today. Customers are saying, 'I already have a lot of software, and it didn't really work for me. I paid a lot, but didn't get real solutions.'

These days, people have changed the phrase 'Total Solution' into a political sound bite, but if you tie your revenue to your actual customer's success, people won't keep buying your software unless you really provide a solution. I'm talking about the kind of pro-active success that creates a real bond between a vendor and a customer. Something that people feel proud of, and that you can measure.

Q: Does it strike you as interesting that people often say that things in EDA were so much better when 'Joe' was around?

Costello: I did my piece in EDA and I'm not there anymore. So I don't really think about it.

Q: Okay - so, what are you going to talk about in your acceptance address at the Kaufmann Award dinner in October?

Costello: I'll probably talk about all of this stuff we've been talking about here. Of course, they'll say it's just the same old Joe, but I've seen this stuff succeed in other business segments. And, of course, now that I've worked in the MCAD industry, I've seen how much easier folks have it in EDA than in MCAD, where things change so much more slowly.

In EDA, Moore's Law forces the customer to continuously upgrade the technology, so it's a nice business-forcing function for the EDA industry. In MCAD, there isn't a Moore's Law, which forces the [MCAD vendors] to look at what the true value of their software is. In MCAD, you have to prove that you're solving a really big pain for your customers. If you're not, you're not going to get diddly from them.

It's completely different in EDA. What EDA needs today are leaders who have a higher motivation to move things forward. It's not just money that motivates people - it's the pride of making a change and making the industry better.

Q: Why do you think there aren't more women in EDA?

Costello: Well, generally people come into EDA from EE, and it's scary, but there just aren't many women there. I heard this story from Richard Newton that people claimed there was no gender bias in a college application for an electrical engineering program. But it turned out that there was this one question on the application that asked high school seniors if they had ever done any serious work on a computer science or technology project in high school.

It turns out, that by eliminating that one question on the application, the school was able to change their screening and increase their acceptance rate for women students to 30 to 40 percent. Because, although the women applicants did well in science and math, the gender bias showed up in that one question.

The hopeful things, however, is that there are more and more women going into business, even though EDA is biased towards engineers who tend still not to be women.

But really, if you want to be successful in running one of these companies, it just doesn't make any sense for somebody to try it who's not completely immersed in the technology. After all, that's the only way you're going to understand your customers and your own guys. If you don't have that technical background, it's really difficult to lead the company.

The flip side is, you can surround yourself with those kinds of people, the technical people. But even if you surround yourself with fabulous people, you're the one who's got to make the final decisions, and you shouldn't find yourself having to flip a coin to make important decisions.

Q: What do you think about the concern these days over the outsourcing of high-tech jobs?

Costello: I understand the underlying issues - most people are hysterically highlighting the thing right now. But instead of attacking it, we should embrace it. People outsource all sorts of things, so the important thing is how does our country, our economy, and our industry deal with it?

On the flip side, we need to be cautious in the U.S. We've gotten fat, dumb, and happy here. We need to step up the pace in this knowledge-based industry. The only thing that sets us apart is our education, the educational level of our population. We need the government to encourage education, and for people to take advantage of the educational opportunity they have here.

An engineering and science education is an extremely powerful foundation for people. I was not a practicing engineer for a huge number of years, but the foundation I got through that experience helped me to know how to approach problems and analyze things.

I strongly encourage that everyone be exposed more to that kind of education than they are today. A science and engineering foundation is an incredible platform that's extremely useful later in life, whether it's in management, sales, or even the arts.

What people get paid highly for in our society is Sales and Marketing - and even Finance. All of those people tend to get paid in our society more than our engineers, although many times engineers have a higher IQ. But the first group brings the higher value add to the thing, and just as we treat entertainers and athletes as celebrities, there's a personality thing that's required to be a success in Sales and Marketing. The thing that engineers can get paid for is innovation, which is always highly valued.

Q: What do you predict going forward to the technology sector?

Costello: My forecast says move to China, for the reason that things are happening there at a really incredible rate. Maybe some of the environmental things there aren't as good as they are in the U.S., but there are really smart people there and the market is really growing there. I mean, where do you think the next great innovations in cell phones are going to come from?

China has had some successes and some failures, but it's an exciting and a formidable place. We've got to take advantage of that, and I mean all players - whether you're in manufacturing or in electronics.

I say, don't play sour grapes and put up walls because of fears of outsourcing to China. We used to have it easy here in the U.S., but look at this summer's Olympic games. America didn't win at basketball and China was Number 2 in the overall number of medals won. That's where the world is going.

Q: So, are you looking forward to the EDAC Awards dinner?

Costello: Absolutely! I'm going to bask in the award, although I hope it isn't too obvious. [Laughing]

My number one message at the dinner will be, 'Get closer to your customers. It's true that sometimes customers can be mean spirited, arrogant, or cheap - picking away about small costs. But in general, you've got to embrace those customers. There's a whole new generation of semiconductor companies, and a whole new generation of things happening. So, there's a new generation of EDA that needs to be managed. There's an opportunity here for both sides to make a change. Break out of your defensive arrogance, and make things happen!' [Laughing again]

They probably all know I'll say these things, so you've got to see that it took a lot of guts for EDAC to give me this award!

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Early Bird Registration Open
2nd International System-on-Chip (SoC) Conference
www.savantcompany.com/SoC-Nov2004/main.htm
WHEN and WHERE: November 3 & 4, 2004, Crowne Plaza Hotel, Silicon Valley -- Milpitas

Commerce & Industry

Technically Speaking announced the PracticalHDL desktop multimedia HDL training course for interactive, self-paced learning with design tools from various companies including Synplicity and Xilinx. PracticalHDL includes parallel Verilog and VHDL instruction, with varying levels of complexity, and comes with learning modules for the coding of memory, finite state machines and RTL verification. Verilog and VHDL practitioners can download a free trial of the course by visiting the website.

Demos on Demand announced a broadband "video resource" for the IC design industry that features product demos from 70+ EDA, PLD and IP vendors. The site allows engineers 24-hour access to product demos from a spectrum of vendors. The programming features recorded sessions with product managers and AEs and is comprised primarily of in-depth product demos for IC design, from ESL design entry through layout. Engineers can visit the site and search by vendor or by product category.

AccelChip Inc. announced increased functionality for the AccelChip DSP Synthesis product, plus new support for third-party partners' RTL synthesis and simulation tools. Version 2004.5 includes support for new FPGA devices, and enhanced flows for ASICs, an enhanced floating- to fixed-point conversion, an enhanced scheduler, and a new implicit loop unrolling (ILU) functionality to the common explicit loop unrolling to array operations, where the user can specify all or down to the specific type of array to be unrolled. AccelChip DSP Synthesis is designed to fit into current design flows, to bridge the gap between MATLAB and RTL, and integrates verification and implementation flow with products from Aldec, Altera, Mentor Graphics, Synopsys, Synplicity, The MathWorks, and Xilinx.

AccelChip announced, as well, that it has extended its AccelWare IP libraries to include building blocks for signal processing and communication applications. The company says the new AccelWare blocks extend the range of the existing AccelChip DSP Synthesis toolset into various real-time, continuous communications and array signal-processing systems.

Finally, AccelChip says it has joined the OpenDoor program from Mentor Graphics. Juergen Jaeger, Marketing Director for the Design Creation and Synthesis Division at Mentor Graphics, is quoted in the Press Release: "When EDA vendors work together, the users reap the benefits. Strong partner solutions maximize productivity, expand choices and shorten time to market, all of which become increasingly critical factors for success in complex FPGA design."

Accelerated Technology (AT), the Embedded Systems Division of Mentor Graphics, announced the Nucleus EDGE software development environment based on the Eclipse open platform standard for the embedded systems industry. The new environment includes a project manager with an editor and builder, various debugging environments, run-mode debug capability, kernel awareness when using an RTOS, and basic execution and memory control. The Nucleus EDGE software will initially support the ARM GNU, RedHat GNU and ARM RealView C and C++ compilers.

Altium Ltd. released Version 8.5 of the TASKING C166/ST10 toolset, which includes enhancements to the compiler and debugger and introduces several key improvements. "Programming large applications is now easier - with support for 'the huge memory model' and additional memory allocation functions offering an optimal match of the application's program setup to the hardware organization. [Also], increased configurability of MISRA C compliance checking enables developers more flexibility to decide whether the code is required or just advised to comply with particular rules in keeping with the standards of their company and the requirements of the project. The C166/ST10 CrossView Pro debugger has also been enhanced in the new version of the toolset."

Altium also announced the release of its LiveDesign evaluation kits that include an evaluation board with the choice of either an Altera Cyclone or Xilinx Spartan-3 FPGA device. The kits are designed so engineers and designers can evaluate Altium's DXP 2004 product range and use the LiveDesign design methodology in Altium's Nexar and Protel design systems. LiveDesign uses FPGAs as reconfigurable implementation platforms for digital circuitry during system development, permitting "live and interactive development and testing of electronics systems inside a programmable hardware design space."

AMI Semiconductor (AMIS) and ARM announced that AMIS has selected the ARM architecture for some new programmable automotive electronics. AMIS has licensed two ARM7 family processors, the ARM7TDMI and ARM7TDMI-S microprocessors, to use in developing products that the company says will help improve driver information, in-car entertainment, body electronics and passenger safety. The first ARM technology-based automotive solutions from AMIS are expected to be available in 2006.

Apache Design Solutions announced that Toshiba has adopted Apache's full-chip dynamic power integrity tools into the Toshiba SoC power closure flow.

Applied Wave Research, Inc. announced their Microwave Office 2004 design suite for RF and microwave circuit designs. The new software integrates 3D planar electromagnetic (EM) simulation with circuit simulation and layout tools, so that arbitrary physical structures can be embedded within linear and nonlinear circuit simulations. The simulator uses a full-wave spectral-domain approach based on the method-of-moments, and is multi-threaded to take advantage of multiprocessor computers. AWR says various third-party EM solvers are integrated with the company's unified data model, including: Sonnet Software's EM product, Zealand Software's IE3D, MEM Research's EM3DS, Simulation Technology and Applied Research's Analyst, and Optimal Corp.'s O-Wave.

In addition, Applied Wave Research and Euan Information Technology announced that BOE HYDIS Technology Co., Ltd.'s Advance Technology Development Group Development division plans to utilize AWR's Analog Office software for the design and simulation of thin film transistor (TFT) liquid crystal display (LCD) panels.

ARM and Sun Microsystems has announced a long-term collaboration to integrate and distribute "optimized" Java solutions for mobile devices. The companies say they'll streamline access to the integrated products by establishing one single distribution source through Sun. The integrated product will be distributed by Sun; commercial deployment of the integrated product will be subject to the separate licensing terms of Sun and ARM respectively.

ARM also launched its new NEON media and signal processing technology targeted for mobile and consumer products that implement multiple combinations of video encode/decode, 3-D graphics, speech processing, audio decoding, image processing, and baseband functionality. The NEON technology will be implemented in future ARM processors, and will be supported by ARM and third-party tool chains. NEON technology is a 64/128-bit SIMD (single instruction multiple data) instruction set that "can execute an MP3 audio decoder in less than 10 CPU MHz, and can run the GSM AMR (Adaptive Multi-Rate) speech codec using only 13 CPU MHz."

Artisan Components and Cadence Design Systems announced a collaboration to provide library views for designers to optimize low-power chip designs. Per the Press Release: "Artisan and Cadence performed qualifications using Artisan's SAGE-X standard cell library and measured delays against SPICE while varying voltage, slew and load. The average difference in measured delays between SPICE and ECSM was 0.5%."

BAE Systems, Celoxica Ltd., and Medius Inc. announced what the companies are calling a "novel software approach to sensor integration that allows for optimized performance and dramatic cost reduction for cruise control, collision avoidance and other automotive safety systems." The new technology comes in release 2.0 of the companies' sensor-fusion technology demonstrator series, and has a self-aligning intelligent sensor that can automatically line up with the frame of reference of the vehicle it is attached to, therefore minimizing factory alignment issues.

Cadence Design Systems and the Shanghai Research Center for Integrated Circuit Design (ICC) announced the ICC-Cadence CPU/DSP SoC reference methodology, which includes the Cadence Encounter platform and Incisive platform, and CoWare's ESL design and verification tools. ICC was established in March 2000 by the Science and Technology Commission of Shanghai Municipality, and is said to focus on "promoting Shanghai and all China IC Design industry to realize rapid development."

Cadence Design Systems also announced the availability of an RTL-to-GDSII reference flow for SoC designs at 130 nanometers and below. The flow uses IP libraries and memories from Faraday Technology Corp. and technology from UMC to allow both high-speed and low-leakage transistors to be combined onto a single chip.

Cadence then announced that Fujitsu Ltd. has standardized worldwide on the Cadence Incisive Conforma equivalence checking tool for verifying ASIC requirements of Fujitsu's SoC designs.

As well, Cadence announced that Stretch Inc. met "an aggressive time-to-market goal for a high-performance software-configurable processor design - and benefited from the strength of a comprehensive Cadence Digital IC design flow and libraries from TSMC to mitigate its design risks and ensure high quality of silicon (QoS) through improved area and performance." Wow.

Cadence Design Systems also announced that Renesas Technology Corp. has standardized on MaskCompose for automated reticle design synthesis in its 90-nanometer design flow.

Finally, Cadence Design Systems announced two new product suites, OrCAD PCB Designer and OrCAD PCB Designer with Pspice, both of which are included in the OrCAD 10.3 release. The suites include the OrCAD PCB Editor constraint-driven PCB layout editing tool. OrCAD PCB Designer includes the SPECCTRA autorouter and the OrCAD Capture design entry tool, while PCB Designer with PSpice includes PSpice A/D for analog/mixed-signal simulation. OrCAD 10.3 also has features for OrCAD Capture, OrCAD Layout, and PSpice. The OrCAD 10.3 release with OrCAD PCB Designer will be available in November 2004.

Carbon Design Systems announced the addition of VHDL and mixed language (VHDL and Verilog) support to its product line. Carbon's SPEEDCompiler software reads synthesizable Verilog and/or VHDL and generates a DesignPlayer engine, which can represent one or more chips. The company says multiple engines can represent a system that encompasses hundreds of millions of gates.

Catalytic Inc. announced the first of what the company says will be a series of DSP design automation software products. Per the Press Release: "Catalytic's Fixed-Point DSP Studio software speeds floating-point to fixed-point conversion for users implementing systems using C or RTL. It shortens implementation time for fixed-point DSP algorithms by providing fixed-point variables in MATLAB from The MathWorks, accelerating MATLAB verification simulations up to 20X."

Celoxica announced it will support the Xilinx's new Virtex-4 FPGAs through the latest release of Celoxica's suite of system design and synthesis tools. Note that Celoxica's tools synthesize complex algorithms described in C or SystemC direct to the FPGA fabric. Alternatively the designer can use the same algorithmic description and output RT-level VHDL and Verilog.

Chartered Semiconductor Manufacturing announced functional 0.13-micron 300-millimeter wafers from its Fab 7. The company says the results exceed internal targets within five months of the first equipment installation. Chartered also announced it has launched the engineering for 300-mm wafers at Fab 7 for its 0.11-micron process, and for the 90-nanometer platform being jointly developing with IBM. The 90-nanometer cross-foundry platform that will be available at both Chartered's Singapore-based Fab 7 and IBM's East Fishkill fab in New York.

CoWare Inc. announced a new version of the company's SPW DSP application product, SPW 5-XP for Windows. CoWare says the new release includes new features and functionality to make DSP application design faster and easier. These features include integration with MATLAB from The MathWorks that the companies say accelerates implementation starting from MATLAB algorithms. New features also include Windows "look & feel,' an open, extendible, standard XML database, and SPW's simulation engine and library of 4,000+ DSP application models."

Meanwhile, CoWare and AccelChip Inc. announced a joint effort to provide an advanced design and verification flow for DSP designs that originate in MATLAB. The companies have integrated CoWare's DSP application design tool, SPW, with AccelChip's algorithmic synthesis tools to offer DSP design teams the ability to verify generated RTL levels in Verilog or VHDL within the SPW environment.

Denali Software Inc. and Mentor Graphics Corp. announced a collaborative effort whereby Mentor Graphics will use Denali's PureSpec verification IP product to confirm that Mentor's PCI Express IP core is compliant with the PCI Express and Advanced Switching Interconnect (ASI) interface standards, and interoperable with other system designs.

eInfochips Inc. announced the availability of DSP-Karma, a suite of DSP software, hardware and systems integration services. The company says DSP-Karma offers is a suite of services with emphasis in the areas of video conferencing, wireless multi-media devices and remote server management solutions. Services includes algorithm design and development, DSP processor selection, board support packages for RTOS on DSP, porting and migration across diverse platforms, board-level systems and firmware solutions on DSP.

Emulation and Verification Engineering (EVE) announced that Amos Technologies will be its exclusive distributor to electronics companies in Israel. Under terms of the distribution agreement, Amos Technologies will market and support ZeBu, EVE's verification platform used by IP, FPGA, ASIC, SoCs, and embedded software. EVE also announced that D'Gipro Design Automation and Marketing, Ltd. to be EVE's distributor in India.

FishTail Design Automation, Inc., announced exclusive distribution agreements with both Saros Technology Ltd. in Europe and Advinno Technologies in Southeast Asia. The company already works with SC HighTech in Japan. The company says the distributors will provide customers with front-line sales and support in their regions.

Fujitsu Ltd., Fujitsu Microelectronics America, Inc., and Synplicity, Inc. have announced an agreement to develop a custom physical synthesis product for Fujitsu AccelArray structured/platform ASIC devices. Fujitsu and Synplicity say they will work closely to produce an optimized version of Synplicity's Amplify physical synthesis software, specifically targeting the AccelArray architecture and enabling performance and faster overall timing closure for Fujitsu's devices. Under the terms of this agreement Fujitsu and Synplicity will jointly define and Synplicity will develop the customized Amplify software for the AccelArray physical synthesis product.

HDL Works announced Version 5.2 of the EASE design entry environment for VHDL, Verilog, and mixed-language designs for FPGA and ASIC projects. EASE 5.2 includes Tcl-driven version management with support for ClearCase, RCS, and Synchronicity Design Sync, as well as Verilog 2001 support and a new project browser.

HDL Works also announced Version 1.1 of HDL Companion, an environment for insight into IP, integrating IP with new code and keeping an overview of HDL designs. New features include Signal Tracing through the design hierarchy, support for Verilog 2001, and version management with support for CVS and RCS.

IMEC announced the IMEC Industrial Affiliation Program (IIAP), which will "seek alternatives to the current use of scaling to reduce device dimensions using nanotechnologies. The program will also investigate disruptive technologies or new paradigms for semiconductor manufacturing processes. Although single devices have been demonstrated, there has been little effort in using nanotechnology building blocks to create an innovative technology with higher density and new functionality. IMEC program participants will investigate the use of semiconducting wires, carbon nanotubes and spintronics and, at the same time, develop the metrology and theoretical approach required as a backbone for implementation of the new methodologies."

"In the first phase of research, the potential of semiconducting wires will be studied. IMEC's fabrication process for making these vertical-pillar structures is now sufficiently mature to start evaluating their use in back-end-of-line (BEOL) processing, more precisely in the vias between the BEOL metal layers. The typical dimensions of the pillars (20nm to 100nm) match perfectly with state-of-the-art optical lithography, demonstrating an ideal link between evolutionary and revolutionary technologies. Applications may be possible in both optical and switching components."

Swept up in the excitement, Freescale Semiconductor, Inc. and IMEC say they are currently in the process of "helping you realize the vision of seamless mobility. IMEC and Freescale are working together on reconfigurable multiprocessor systems." Freescale says it has joined IMEC's Industrial Affiliation Program (IIAP), and thereby plans "to deliver leading edge mobile multimedia solutions by utilizing IMEC's existing and future reconfigurable technology, capitalizing on IMEC's total system approach and its focus on low power, as well as leveraging IMEC's system design tools and methodologies."

iRoC Technologies Corp. introduced the Soft Error Analysis Web Tool, a web-based tool that assesses the Soft Error Risk (SER) of IC designs-transient faults caused by external radiation that affect the logic states of ICs and memories in SoCs, ASICs, FPGAs, or memories. The tool also gives recommendations on steps that can be taken to quantify and also reduce the soft error failure-in-time (FIT) rate if the target application or industry requires it.

iRoC Technologies also introduced its SERPRO services for transistor-level SER prediction and optimization. The company says the services will "help semiconductor companies perform faster and more accurate soft error modeling before design tape out-making their ICs more reliable in the field."

Eric Dupont, iRoC's President and CEO, is quoted: "Up to 90 nanometers, both standalone and embedded memories have been the primary design element impacted by cosmic rays, so memory providers and designers of SoCs with large memory elements will benefit greatly from our new services. As more devices are designed for 90- and 65-nanometer nodes, potential damage from cosmic rays will not only affect memory elements, but also logic gates. Designers of memory and logic devices need to be able to analyze, simulate, predict and optimize their SER numbers during the design cycle to achieve their target SER rate and ensure product reliability."

Lattice Semiconductor Corp. and Mentor Graphics announced a multi-year extension and expansion of their OEM agreement for Mentor Graphics synthesis and simulation tools. The new agreement adds the Mentor's Precision RTL synthesis tool to the Lattice OEM portfolio,

LSI Logic Corp. announced three new RapidChip IntegratorQSslices. Per the Press Release: "The new slices leverage LSI Logic's proven-in-silicon and standards-compliant GigaBlaze serializer/deserializer (SerDes) technology by including four independent lanes of 4.25 gigabits per second (Gbps) SerDes. Another key architectural advantage of the RapidChip IntegratorQS slices is that they support PCI Express datapaths of 250 MHz. These datapaths are implemented in the metal configurable R-cell logic transistor fabric. The combination of SerDes and logic performance ensures that developers can implement ASIC-class low latency, high system performance solutions, with the benefits of risk mitigation and affordable NRE costs associated with Platform ASIC technology."

Magma Design Automation Inc. and ChipX announced availability of an RTL-to-GDSII design flow based on Magma's Blast Create and Blast Fusion. The companies say they have worked together to test and customize the Magma flow to support the ChipX CX5000 family and future structured ASIC product families.

Also, Magma Design and MIPS Technologies, Inc. announced the availability of a validated reference methodology for the high-performance MIPS32(R) 24K microprocessor core family. The methodology includes flow documentation, floorplanning information, tool scripts and make files. In addition to validating the reference flow, MIPS says it has completed the Magma IP verification process for the 24K family and the company has been added to the growing list of "Magma-Ready" IP providers.

MatrixOne, Inc., and Technia AB signed a software and service agreement with Ericsson to use MatrixOne's PLM software as Ericsson's global platform for managing development projects. MatrixOne and Technia will work together on the global deployment and implementation of the system within Ericsson's R&D units.

Mentor Graphics announced the availability of the Altera Stratix GX design kit for ICX. The companies say the new design kit allows engineers using the Mentor Graphics ICX signal integrity (SI) analysis tool to perform full-board analysis on designs featuring the high-speed serial I/O technology of the Altera Stratix GX devices "hundred of times faster than previously possible with SPICE-based simulation techniques."

Mentor Graphics also announced that its suite of advanced synthesis products will support the newly introduced Virtex-4 FPGAs from Xilinx. Customers who use the Precision RTL or LeonardoSpectrum tools can now request software that supports the full range of Virtex-4 devices, while the Precision Physical tool is offering beta-level support

Then, Mentor Graphics announced that it has "enabled the industry's most accurate simulation of nanometer technology with the introduction of new resistance and capacitance engines for its full-chip, transistor-level parasitic extraction solution, Calibre xRC. Based on the new resistance engine, Mentor Graphics has also developed hierarchical netlisting and optimized back annotation capabilities between Calibre xRC and Nassda's high-performance simulation platform HSIMplus."

Mentor Graphics also announced that the Calibre product line is now accepting OASIS files and supporting OASIS output in the upcoming 2004.3 production. It includes the GDS-to-OASIS translator, which was previously made publicly available for validation and verification of the new format. The OASIS translator will be an included feature in the Calibre releases, and available to all Calibre customers.

Mentor Graphics also announced new enhancements to its MBISTArchitect BIST tool for on-chip testing of embedded memories generated by Artisan Components. Additionally, Artisan says it has recognized the MBISTArchitect tool as a "qualified BIST solution" for testing its embedded memories and facilitating its Flex-Repair(TM) Redundancy solution for yield improvement. Per the Press Release: "As the use of embedded memory continues to increase, thorough testing and defect diagnosis has become paramount to product quality and yield enhancement. Memory BIST has emerged as the most efficient method to test and diagnose problems with embedded memories."

Mentor Graphics also announced a technical collaboration with StarCore to offer Seamless hardware/software co-verification processor models for StarCore's licensable processor cores, SC1200 and SC1400. The support packages will implement SC1200 and SC1400 cores and subsystems, as well as providing performance profiling for cache activities, memory accesses and software codes.

Mentor Graphics also announced new automated functionality in its ATPG, FastScan, and TestKompress embedded deterministic test tool. The ATPG Expert feature works as an internal "expert" within the FastScan or TestKompress tools to automatically analyze the design, manages test generation complexities, and determines the sequential depth or abort limits to set, the types of compression to exploit, and how to handle clock interactions and bus contention.

Mentor Graphics also announced a new version of its popular ModelSim simulator and new verification technology from the recently completed acquisition of 0-In Design Automation. With the ModelSim 6.0 simulator and the 0-In product line, Mentor Graphics says it now offers "standards-based support for the most advanced verification methodologies. Offering support for assertion-based verification and coverage-driven verification flows, as well as verification IP, Mentor's scalable verification platform offers engineers a faster way to reach verification closure than current methods."

Finally, Mentor Graphics announced it has established business agreements with Optimum Design Associates (Optimum) and PCB Libraries to make their libraries available for use with the Mentor Graphics PADS PCB design flow. These agreements will allow PADS customers to choose from various suppliers of component libraries in selecting components for their electronic products." Clearly, it's been a busy month for Mentor!

PolarFab has published its 2005 PolarShuttle schedule. The company says that designers can "test prototypes and minimize a new product's time to market by incorporating PolarShuttle into their development schedule. New for 2005 are two additional manufacturing runs of PolarFab's PBC4 0.5-micron BiCMOS-DMOS (BCD) process."

Pulsic Ltd. has announced that Hynix Semiconductors has adopted Pulsic's shape based place-and-route flow "to reduce the turnaround time for leading-edge designs."

QuickLogic Corp. announced a Reference Design Kit (RDK) for low-power designs that uses the company's Eclipse II FPGAs. The Low Power RDK includes hardware and software tools, and allows designers directly measure the power consumption of Eclipse II designs, and calculate, analyze, and simulate power dissipation for Eclipse II designs under development. The Low Power RDK comes with two PCBs - a prototyping board housing the Eclipse II FPGA and a daughter board for power measurement.

QuickLogic also announced the QL92xxx family of programmable SoC devices, products based on the QL902M member of the QuickMIPS product family. The new products incorporate additional pre-programmed modules that will target the device for embedded digital-media applications. The first member of the family, the QL92010, incorporates an IDE controller. Subsequent devices, to be announced later this year, will embed functionality "consistent with the company's focus on providing silicon solutions for equipment that distributes and processes digital media across wired and wireless IP networks."

Silicon Canvas, Inc. announced the release of Laker-AMS version 6.1. The new release includes a new licensing scheme transition from Rainbow to FlexLM, enhanced hierarchy navigator usage, added Tcl/Tk scripting language support, a streamlined Spice-out procedure, and a new interface to the Laker full-custom layout tool. The company says the new release assists in the shift from a traditional polygon pushing methodology to the schematic driven layout flow methodology.

Silicon Dimensions, Inc. announced an agreement with eSilicon Corp. to distribute Chip2Nite to the eSilicon customer base. In addition, eSilicon says it will adopt Chip2Nite into its silicon implementation flow and collaborate with Silicon Dimensions to develop new tools to meet future IC design challenges.

SMSC announced what the company describes as "one of the industry's most comprehensive lines of USB2.0, mobile super I/O and embedded Ethernet controllers for a wide range of consumer and commercial connectivity solutions. With this announcement, SMSC delivers the USB2503 and USB2507, the industry's first USB2.0 3-port and 7-port hub controllers with SMSC's innovative MultiTRAKTM multiple Transaction Translator (Multi-TT) technology, as well as the USB2504, a second generation 4-port hub controller; the USB2228, a controller for 12-in-1 flash card readers; the USB3250, a second generation USB2.0 physical layer transceiver (PHY) device; the SIO1000, a second generation consumer InfraRed (IR) I/O controller; plus the Company's LAN9118,a second generation 10/100 Non-PCI Ethernet controller." Again, wow.

Stone Pillar Technologies Inc. announced TestPlanManager, which the company describes as the newest addition to its Silicon Insight family of products for developing semiconductor process technologies. TestPlanManager automates the creation of test routines for device characterization and provides capabilities for test library management, which the company says improves test plan readability, reduces errors, guarantees consistency between test plan documentation and executable, and reduces engineering effort by as much as 75 percent.

Synopsys, Inc. announced that Samsung Electronics Co. Ltd. has signed a multi-year license agreement for Synopsys' DesignWare IP, under the terms of which Samsung is licensing Synopsys' PCI Express and USB families of digital cores and analog PHYs. The first core Samsung will use under the license agreement is the USB 2.0 PHY core.

Synopsys also announced that Synopsys' Design Compiler FPGA (DC FPGA) now supports the Xilinx Virtex-4 family of domain optimized FPGAs and ISE 6.3i place and route software. Synopsys says that DC FPGA is targeted for designers who prototype ASICs using high-end FPGAs. [Bets are on that there will be more and more of this type of news in the coming era coming from a range of different EDA vendors.]

Synopsys also announced that IPCore Technologies Corp. (described as "China's pioneer pure design foundry") has signed a multi-million dollar agreement to adopt Synopsys' Galaxy Design and Discovery Verification Platforms, and Synopsys' DesignWare IP portfolio as IPCore's primary internal design flow. The company says that under the terms of the agreement, Synopsys Professional Services will expand its delivery capability in China by selectively utilizing IPCore on a subcontracting basis.

Synopsys also announced that Microchip Technology Inc. has standardized on Synopsys' Circuit Explorer optimization and analysis solution for its complex analog designs. The Microchip team says they selected Circuit Explorer because "it enabled them to take weeks off of their design cycle and eliminate the tedious manual tasks usually associated with complex analog designs." Something to celebrate.

Synopsys announced, as well, the availability of the DesignWare USB 2.0 On-The-Go (OTG) PHY (Physical Layer) Core targeted to TSMC's 90-nanometer, 130-nanometer, and 180-nanometer processes, as well as an extension of the Hi-Speed USB 2.0 PHY Core product line to the 90-nm process node. The new OTG PHY will handle HNP (host negotiation protocol) and SRP (session request protocol), which are the OTG-specific differences between the Hi-Speed 2.0 and the new OTG standard. The OTG solution is based on the Synopsys USB 2.0 PHY that is already certified and shipping in volume.

Then, Synopsys announced that Atheros Communications, Inc. has adopted Synopsys' NanoSim for the RF front-end circuit verification of Atheros' AR5005G single-chip wireless product. The company says the chip is a multi-million-gate IC that supports the IEEE 802.11b and 802.11g protocols, and that using NanoSim 2004.06, Atheros engineers can now perform RF front-end circuits verification of their complex mixed-signal devices.

Also, Synopsys announced that its Proteus optical proximity correction (OPC) software has been adopted by NEC Electronics Corp. for use in NEC's 90-nanometer production.

Synopsys also announced that BAE Systems used Synopsys' Galaxy Design Platform to achieve success on 24 radiation-hardened space-qualified ASICs. Per the Press Release: "Galaxy's predictive timing closure, as well as its tightly integrated flow, was instrumental in the design success of the complex chips."

Finally, Synopsys and Photronics, Inc. have announced a joint program for improving the manufacturability and quality of photomasks and reducing the cycle times for design-to-photomask flows. The companies says that they'll explore and develop solutions in the area of DFM and mask synthesis targeting faster time to yield for semiconductor manufacturers.

Synplicity Inc. announced that the company's newest version of the Synplify Pro synthesis software provides full support for Xilinx's Virtex-4 FPGAs. The company also announced the latest version of its FPGA synthesis and physical synthesis software solutions. The Synplify Pro 7.7 synthesis tool includes enhancements, as well as support for new FPGA devices from Xilinx and Lattice Semiconductor. Synplify Pro software now include timing-driven synthesis support for Xilinx's Virtex-4 FPGAs and support for Lattice Semiconductor's LatticeECP and LatticeEC FPGA device families. Synplicity says enhancements have also been added to the Amplify FPGA 3.7 physical synthesis software.

TransEDA announced the availability of its PCI All-in-One verification IP and its latest VN-Control bus-based system-level test generator release 3.0. The new verification IP provides a single, compatible programming interface which allows verification teams to reuse their tests on systems containing any combination of PCI Express, PCI-X and PCI buses. This IP accommodates testing of various system-level configurations such as systems containing PCI Express buses only, a combination of PCI-SIG standard buses, or a single PCI-SIG standard bus selectively enabled.

Wolfson Microelectronics plc announced that the company has purchased software from Verific Design Automation and is using it as part of its internal design environment. Wolfson said they had to because the increasing digital complexity of Wolfson's advanced mixed-signal products has motivated a transition of its digital design flow from a partly schematic, partly Verilog hardware description language (HDL), flow to a fully Verilog HDL based flow. Verific's HDL Component Software provides a Verilog parser and analyzer.

X-FAB Semiconductor Foundries AG announced an extension to its modular 0.35-micron process family to include a high-voltage option, as well as 0.35 µm-BiCMOS technology. With this product extension, X-FAB says the XH035 0.35 µm CMOS technology can be "flexibly expanded with virtually a free range of combinable add-on modules."

Xilinx announced shipments of the 6.3i release of its Integrated Software Environment (ISE), which the company says is optimized for the Xilinx Virtex-4 family of Platform FPGAs. The company says the new ISE 6.3i uses the Virtex-4 architecture to support up to 200,000 logic cells and 500 MHz performance for twice the density and up to 10 times better performance-price ratio than previous generation FPGAs.

Xilinx also announced the version 6.3i of the Platform Studio for system-level embedded processing design on Xilinx Platform FPGAs. The company says that the tool suite automates various architecture-level design steps and offers a new software environment based on the Eclipse IDE. The Platform Studio 6.3i release supports the Xilinx processor products, including the MicroBlaze and the immersed PowerPC cores, and allows for system-level design for the Virtex-4 LX, SX, and FX device families, while also supporting the Xilinx Virtex and Spartan-3 Series Platform FPGAs.

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Economics & Finance

EDAC's Market Statistics Service (MSS) announced a 2-percent growth in Q2 2004 over Q2 2003 for license and maintenance, the largest EDA revenue category. Total Q2 2004 revenue, which included semiconductor IP, was $993 million, a 4-percent increase over Q2 2003. Services revenue at $70 million showed an 11-percent increase over the same quarter last year.

Computer-aided engineering generated revenue of $474 million in Q2 2004, 4 percent more than the same period in 2003. IC physical design and verification revenue was $282 million, down from $285 million in the same period last year. Revenue for PCB and multi-chip module layout was $84 million in Q2 2004, 1 percent less than in Q2 2003. Semiconductor IP revenue was up 28 percent to $84 million over Q2 2003, due in part to growing SIP participation in MSS reporting with CAST and Tensilica initiating participation in the second quarter.

North America revenues increased by four percent to $523 million, Europe revenues of $180 million were up 4 percent, and Japan at $176 million was down five percent. The rest of the world had total revenues of $115 million, up 19 percent from Q2 2003. Reporting companies employed 20,000 professionals in Q2 2004, 6 percent more than Q2 2003, a new high in employment reported by the MSS since it began tracking employment data in Q1 2000.

Nonetheless, Walden Rhines, EDAC Chairman and Chairman and CEO of Mentor Graphics, struck a solemn note in the Press Release: "Despite very modest growth in the EDA industry, there are no indications of overall strength. Growth in services versus last year is positive, but the sequential decline is not. Good growth in some areas, like analysis tools, RTL simulation, system-level design/verification, floorplanning and resolution enhancement, was offset by weakness in physical design/verification and logic synthesis. Similarly, growth in Pac Rim was offset by weakness or slow growth in other regions."

Apache Design Solutions announced that "Q3 2004 marks the company's seventh consecutive record quarter." Andrew Yang, CEO of Apache said that the Q3 results were "well balanced, with existing customers adding quantities of licenses for world-wide deployment, new first-time customers, and a number of renewals."

Magma Design Automation revised its outlook for the second fiscal quarter ended Sept. 30, 2004. Magma now expects total revenue for the quarter to be in the range of $35 million to $39 million, matching the target revenue range the company announced during its July 28 earnings call.

However, Magma alarmed some in the industry when it said it expects total orders (bookings) to be in the range of $37 million to $45 million for the second quarter, below the target range of $70 million to $90 million that the company gave as guidance during its July 28 earnings call. Magma President & COO Roy Jewell is quoted in the Press Release: "A small number of mid-size orders that were expected to close in the quarter were delayed by the customers. These customers indicated they still intend to complete their purchases with Magma, and although they could not close the transactions within the quarter-ending time frame we still expect them to be completed - none were lost to competitive pressures. We see many of our customers having a lack of visibility in their businesses and continuing to spend their R&D budgets judiciously. As a result, we see no change in our previously stated perspective that overall EDA spending will remain flat to down for the next year."

Ambric, Inc. announced completion of its Series A financing. The $10.4 million round was led by both ComVentures and OVP Venture Partners, and included all of Ambric's seed-stage investors, including Northwest Technology Ventures and private investors. The company was founded by Jay Eisenlohr, President and CEO, and Anthony Mark Jones, Vice President of Engineering and CTO.

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Politics & Government

Accellera announced that its Board has re-elected all its officers at a Board meeting earlier this month. In addition, the organization announced plans for the next year. Dennis Brophy, Director of Strategic Business Development at Mentor Graphics, was elected Accellera's Chair for a 5th term. Shrenik Mehta, Director, Frontend Technologies - ASICs & Processors at Sun Microsystems, was elected Vice Chair for a 3rd term. Dave Kelf, Vice President of Marketing at Novas Software, was elected Treasurer for a 2nd term. Karen Bartleson, Director of Interoperability at Synopsys, was elected secretary for a 5th term. Congratulations to all of these hard-working folks.

In the next year, Accellera says it plans to continue to work with and strengthen its relationship with the IEEE Standards Association and focus on standardization activities that include Accellera's Open Kit & Harmonization standards and Accellera's Verilog Analog/Mixed Signal (Verilog-AMS) design language standard.

The VSI Alliance (VSIA) also announced the results of the 2004 election for Board of Directors. Seven seats were up for election, and these seats have been filled by six incumbents and one new board member. The Board members elected include: John Goodenough, ARM; Bill Billowitch, Agere Systems; Victor Berman, Cadence Design Systems; Homer Hegedus, Freescale Semiconductor; Raminderpal Singh, IBM; first-time member Ronnie Vasishta, LSI Logic Corp.; and Ian Mackintosh, Sonics. The current Board consists of eleven Board members, including those already listed and the following: Infineon Technologies AG, Mentor Graphics, ST Microelectronics, and TSMC.

Also per the Press Release: "For the past 18 months, the VSIA has undergone significant changes, including a refocusing on key issues and a reorganization of the working groups into Pillars that address the key issues. The four Pillars are: IP Quality, IP Protection, IP Infrastructure (IP packaging and transfer) and R&D. During the past year, the IP Quality Pillar in conjunction with the FSA have released the Quality IP Metric to VSIA members. During the past month, the IP Protection Pillar released the hard and soft IP tagging Standards to members. The IP Infrastructure Group is working on an IP packaging spec that should be released by the end of Q1 2005. The R&D Group is currently looking at analog FIRM, IP valuation, and design for manufacturability."

In less collegial news, Synopsys announced it received a patent assertion letter from Magma Design Automation citing three patents, two of which (U.S. Patent No. 6,453,446 and No. 6,725,438) name Dr. Lukas van Ginneken, a Magma founder and former Synopsys employee, as the sole inventor. Per the Press Release: "After a thorough review, Synopsys has determined it is not infringing the cited patents, and further determined Synopsys rightfully owns the two van Ginneken patents. Accordingly, Synopsys today filed suit in Federal court against Magma under the van Ginneken patents to enforce its rights as the owner of the inventions and to bar Magma from practicing Synopsys' technologies."

Meanwhile, Magma Design Automation announced that a lawsuit and accompanying public statements by Synopsys alleging that Magma has violated Synopsys' patent rights are without merit. Per the Press Release: "Magma also affirmed that its intellectual property rights are protected in several patents issued to Magma by the United States Patent & Trademark Office. Magma further affirmed that it will not only vigorously defend itself in this matter but will also take the offensive and fully enforce its patent and other rights against Synopsys."

Tharas Systems announced that the U.S. Patent and Trademark Office has awarded Tharas Systems four patents for technology that address "hardware-assisted debug and functional verification." The company says that U.S. Patent number 6,629,297 entitled, "Tracing the change of state of a signal in a functional verification system," and U.S. Patent number 6,625,786 entitled, "Run-time controller in a functional verification system," enables Tharas to embed debug infrastructure inside the hardware-assisted engine - while U.S. Patent number 6,691,287 entitled, "Functional verification system suited for verifying the function of non-cycle integrated circuits (IC) design," and U.S. Patent number 6,629,296 entitled, "Functional verification of cycle-based integrated circuit design," enables delivery of a unique, cost-effective and scalable solution for high-performance, hardware-assisted verification of complex integrated systems.

Denali Software announced the company has joined the newly formed Serial ATA International Organization (SATA-IO), and introduced two new products for use in the design and verification of chips incorporating the Serial ATA (SATA) interface standards. The new products include IP core designs and verification IP tools for the SATA II standards.

DAFCA Inc. announced that the company has been awarded an Advanced Technology Program (ATP) grant totaling $1.9 million from the National Institute of Standards and Technology (NIST), a division of the U.S. Department of Commerce. The grant will fund a three-year research program that aims to extend applicability of DAFCA's reconfigurable infrastructure platform for SoC devices, and research into in-situ error correction and yield enhancement tools. The Advanced Technology Program provides cost-shared funding to industry for high-risk R&D projects that are deemed important, with potentially broad-based economic benefits for the U.S. The awards are made on the basis of a peer-reviewed selection process. (www.atp.nist.gov)

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Citizenry

The EDA Consortium announced that Joe Costello, Chairman and CEO of think3 and former Chairman and CEO of Cadence Design Systems, is this year's recipient of the EDA industry's Phil Kaufman Award. The Consortium will present the Award on Thursday, October 28, at its 11th annual Award dinner and ceremony in San Jose.

The Phil Kaufman Award honors an individual whose contributions have had measurable impact on the creativity and productivity of design engineers. Per the Press Release: "Joe Costello was selected to receive the Phil Kaufman Award because of his business contributions that helped grow the EDA industry. Under his leadership (1987-1997), Cadence became the world's leading supplier of EDA software and services and one of the top ten largest software suppliers in the world."

EDAC Chairman and Chairman & CEO at Mentor Graphics, Walden Rhines, is also quoted: "[Joe] displayed a savvy ability to recognize important design trends and did a great job of moving the industry forward to capitalize on those trends."

Cadence Design Systems the completion of a major renovation of the EDA laboratory at Czech Technical University in Prague, Czech Republic, as part of the company's University Partner Program. Per the Press Release: "With the support of the Ministry of Education, the laboratory has been renovated to develop engineering talent in advanced electronic design for the Czech electronics industry. In addition to financial support for construction, the Cadence contribution provides an enriched design environment in the lab with a broad array of industry-standard software."

Emulation and Verification Engineering (EVE) announced the formation of Nihon EVE K.K., a wholly owned subsidiary based in Yokohama. EVE CEO and President Luc Burgun also announced the appointment of Tsugumi Fujitani as managing director for EVE's new Japan operations. Previously, she managed Tera Systems' operations in Japan, and was CEO and Co-founder of Spinnaker Systems. Fujitani began her career as an application engineer at Hitachi. She moved to Okura, Ltd., where she served as a FAE manager. Fujitani is quoted in the Press Release: "I was elated when presented with the opportunity to join EVE as head of Japanese operations. Its hardware-assisted verification technology offers outstanding specifications. The EVE team is cordial, rigorous and impressively smart." Lovely.

iRoC Technologies Corp. has named Mark Derbey as General Manager of operations for its European headquarters in Grenoble, France, where he will oversee daily operations of iRoC's European headquarters, and manage engineering and R&D. efforts. Derbey comes to iRoC from Sun Microsystems, where he led the software development team for its Telco high-availability product. Before joining Sun, Derbey was a senior manager at Bull SA. He has a BS in Computer Science from Joseph Fourier University in Grenoble, France and an MS in Artificial Intelligence from the Paul Sabatier University of Toulouse, France. He is also certified by the Program Management Institute.

Stelar Tools, Inc. announced Robert Grossman has been named Executive Vice President of Sales and Marketing. Previously, he was with Novas Software. Grossman has 25+ years of sales and marketing experience with various EDA companies including Tharas Systems, Vast Systems, and Mentor Graphics. He has been involved in various start-ups from early stages through to acquisition or IPO. Grossman has a BE from Cooper Union University and an MSEE from the University of Massachusetts.

Silicon Design Systems, Inc. announced it has established a Technical Advisory Board that will consult and advise the company's executives and engineering management on technology directions for its physical design closure products. Initial Board Members includes: Dr. Eby G. Friedman, University of Rochester, Dr. Sachin Sapatnekar, University of Minnesota, Dr. Naveed Sherwani, President, CEO and Co-Founder of Open-Silicon, and Udi Kra, CTO of Silicon Design Systems.

Synplicity Inc. announced that Gary Meyers has been named CEO of Synplicity, and will hold the title of President and CEO. Meyers, who was recently appointed President and COO is succeeding CEO Bernie Aronson, who will remain a member of Synplicity's board of directors. Aronson is leaving Synplicity to join Kilopass Technology Inc. Synplicity says that Meyers' transition to president and CEO completes the succession plan for Aronson.

Of course then, Kilopass Technology needed to announce that Bernie Aronson, former CEO of Synplicity, has joined Kilopass as President and COO. Jack Peng, Founder and CEO of Kilopass Technology, is quoted in the Press Release: "Mr. Aronson is a proven business leader and a successful serial entrepreneur who has grown great companies from start-up to IPO. We are delighted to add such leadership and experience to our team. Bernie will help us grow our business and accelerate the adoption of our memory technology into designs created for high volume products." Lucky Kilopass!

Meanwhile, Synplicity also announced Andrew Haines has rejoined Synplicity as Vice President of Marketing. Haines originally joined Synplicity in 1996 as the company's Vice President of Marketing and remained in that capacity until 2002, when he departed to work in the IP industry. Most recently, he was Vice President of Business Operations at Catalytic, Inc. Haines was also an executive at ARC International, and before joining Synplicity in 1996, and was President and Founder of Page Mill Marketing. Earlier in his career, he held management positions at Actel, VLSI Technology, and Intel. Haines has a BS in physics from the University of Wisconsin.

Synplicity announced as well that Jim Lovas is now Vice President for North American sales, reporting to company President and CEO Gary Meyers. Lovas has 20+ years of experience in the EDA and semiconductor industries. Prior to Synplicity, Lovas was at Summit Design, and also held senior sales and AE manager positions at Zycad Corp. Lovas started out as an ASIC designer at ITT Avionics. He has a BSEE from the New Jersey Institute of Technology and an MSCS from the Steven's Institute of Technology.

Mentor Graphics announced that test industry expert, Bernd Koenemann, has joined its DFT product division as a chief scientist. Koenemann joins Mentor Graphics from Cadence Design Systems. Previously, he served at LogicVision, IBM and Honeywell. He holds several patents in the field of test technology. Meanwhile, Koenemann is preparing to deliver the keynote address at the International Test Conference (ITC) on October 26. In his speech, Test in the Era of "What You See Is NOT What You Get," Koenemann will discuss how increasing design complexities threaten design closure predictability as well as its effect on yield. You should be there!

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Festivals & Fairs

ESL Methodologies Seminar - Aldec, Inc. is hosting a seminar series on system-level methodologies, divided into two parts. The morning session will covers SystemC methodology, and the afternoon session provides hands-on training. The seminars will be in Dallas, TX, on October 12 and Austin, TX, on October 13. (www.aldec.com)

ARM Developers Conference - This first time event is taking place October 19 to 21 in

Santa Clara, CA. Organizers describe the conference as "the only industry event for developers of ARM Powered solutions." ARM and its technology and tools partners will all contributing to the discussions. (www.arm.com/developersconference/)

IEEE ISQED'05 - Conference organizers have extended the paper submission deadline for next year's meeting to October 20. ISQED 2005 will be held March 28 - 30 in San Jose, CA. (www.isqed.org)

IEEE ITC 2004 - The International Test Conference 2004 will be held in Charlotte, NC, from October 26 to 28. ITC is the premier conference in North America dedicated to the electronic test of devices, and boards and systems. Papers and panels cover the complete cycle from design verification, test, diagnosis, failure analysis and back to process and design improvement. (www.itctestweek.org )

SOPC World - System on a Programmable Chip World will be taking place in San Jose, CA, on October 27, and in Boston, MA, on November 4. Altera is hosting the event, with help from Aldec, Mentor Graphics, Infineon, The MathWorks, Micron, and Tektronix. The organizers say the conference will "acquaint you with today's most advanced programmable solutions, including: How to maximize performance for digital signal processing (DSP) & embedded systems, and how to use FPGAs to solve high-speed design, signal integrity & memory interface challenges." (www.altera.com)

Cadence Design Systems is seeking a Silicon Valley non-profit organization to be the beneficiary of its 2005 Stars & Strikes Fund-raiser. Deadline for proposals is Oct. 29.

Mentor User2User Conference - Mentor Graphics announced that October 29 is the abstract deadline for submitting papers to the 2005 User2User meeting, taking place April 27 to 29 in Santa Clara, CA. (www.mentor.com/user2user/cfp/)

International SoC Conference - The 2nd annual conference will be held in Milpitas, CA, on November 3 and 4. The Open Core Protocol International Partnership (OCP-IP) is co-sponsoring the event, which will address the entire SoC-related chain, including semiconductor vendors, chip foundries, EDA-tool and IP vendors, and vendors of CPU and DSP cores. (www.savantcompany.com)

ICCAD - The International Conference on Computer Aided Design takes place in San Jose, CA, from November 7 to 11. The conference is an all-encompassing event that addresses the myriad design and manufacturing issues cropping up at all levels of semiconductor device design and implementation. (www.iccad.com)

Denali Software, Inc. announced Denali MemCon will be on November 9 and 10 in Silicon Valley. Denali MemCon is held annually in Taiwan, Tokyo, Boston, and San Jose. This year's event in San Jose provides a forum for exchanging information about the technology and markets for semiconductor memory, serial interface standards and related system-on-chip design issues. The event is expected to draw more than 1,000 system architects and chip developers, will offer two executive keynotes, three panel sessions, and 40+ presentations from industry experts. (www.memcom.com)

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Peggy Aycinena authors EDA Nation, serves as Copy Editor on Chip Design Magazine, and owns and operates EDA Confidential at www.aycinena.com. She can be reached at peggy.aycinena@extensionmedia.com.

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