History & Geography
— "ESL & All That Jazz"
Commerce & Industry
Economics & Finance
Politics & Government
Festivals & Fairs
Welcome to the January issue of EDA Nation. This past year was a complex one in many places around the world, with news and headlines reflecting the stunning developments in politics, war, economics, weather, earth science, and oceanography, just to name a few. Dramatic, frequently tragic, and occasionally beyond comprehension - for many, those headlines defined 2004 and caused them to welcome 2005 with a sense of relief. “That’s enough of 2004! Let’s get on with 2005!”
Meanwhile, there were significant developments within the EDA Nation in 2004. Although the headlines in EDA were rarely on the scale of the larger events sweeping the globe, many of the stories within the industry were interesting, intriguing, and compelling in their own way on both the business and the technical sides of things.
In my estimation, 2005 promises to be even more interesting for those who track EDA. Acquisitions and new management teams at various companies will continue to fuel the business headlines, while news and developments in the areas of verification, DFM, ESL, and embedded software will further amuse and amaze those who track those technologies.
Appropriately then, this month’s article spans both the business and the technology paradigms within EDA. The main article is a discussion with Jeff Jussel, Vice President of Marketing at Celoxica (Abingdon, Oxfordshire, U.K.). These days Jeff is carrying around a nifty set of PowerPoint slides that help to articulate Celoxica’s position in the market. The slideshow details Jeff’s and Celoxica’s take on electronic system level design (ESL), how ESL interfaces with EDA, and how Jeff’s subsequent definition of behavioral synthesis differs from that of Celoxica’s competition.
Of course, you might be inclined to ask why any set of slides from a VP of Marketing warrants being the basis for an article in a technology newsletter that purports to be both objective and impartial. Well, either you’ll have to take my word for it, or you’re going to have to track Jeff Jussel down and have him walk you through those slides in person - or, you could read the article. No matter which way, however, I’m telling you the slides are plain long nifty and they provide a great starting point for a point/counterpoint discussion of ESL and All That Jazz.
Happy New Year to everyone here in the EDA Nation. I sense a strong undercurrent of optimism in the industry at the outset of the year, and I believe the next 12 months offer a lot of promise for the folks who work here. Now, if we could just get the rest of the world to follow suit…
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History & Geography
"ESL & All That Jazz"
What follows here is my take on Jeff Jussel’s narration of the Celoxica slides on ESL. He walked through the presentation for me in early January, and I thoroughly enjoyed the presentation. Jussel’s a pretty serious guy, and I give him high marks for avoiding the let-me-insert-some-market-speak-into-this-explanation explanation. And, although you may not agree with everything Jeff has to say here, it’s clear that Jussel’s is one voice that will be part of the conversation on ESL that’s inevitably unfolding in the industry even as we speak.
Celoxica’s Jeff Jussel on ESL …
“The focus in these slides is to give an overview of ESL - where does ESL fit into EDA? Presently, the EDA companies are in two camps. Either they’re moving into the physical side - the big guys w/ design suites for 90 nanometer and below - driven by Gary Smith or customer demands, or both. Or they’re companies like Celoxica - trying to attack the system-level space by developing tools for algorithm implementation.”
“Algorithms are the key to ESL design. It used to be, when I started designing, that a company was competitive because they were made up of polygon pushers who had developed their own, better, faster technique for doing a design.”
“These days, however, it’s more about - can I get my algorithm into place faster than my competition. An algorithm is the key to a product these days; it’s what’s driving the value. It’s no longer so much, can I make a design that’s faster and smaller - after all, at 90 and 65 nanometers, the pressure is off there - now it’s about - getting my algorithm implemented faster. And the algorithm is what determines if my HDTV, for instance, has a sharper picture and is out on the market faster than my competition. Or, can I get my robot up fast enough to save the Hubbell Telescope before it runs out of power. It’s these types of algorithm-focused problems that we’re trying to solve today.”
“So, what ESL really involves is something that’s very verification centric. Is the algorithm correct? The next question then, is the architecture correct, the implementation of the hardware? All of that revolves around the transaction-level model. That is what’s driving ESL; it’s taking the algorithm to implementation based on the functionality of that algorithm.”
“Standardization is helping out there, working in standard languages like SystemC. Also, taking a transaction-level model (TLM) and synthesizing it - doing it in a hardware implementation so you don’t have to break the verification flow with RTL translations - is helping out there.”
“Until recently, those sorts of things weren’t available. If you weren’t able to take your model and create hardware from that model, what you had to do was to take your best guess and implement by hand. That was a slow and painful process, but you gave the best guess of the architecture you needed to implement the thing. Of course, it took 6 to 8 months for the engineering to implement it in hardware and, of course, by the end of that time if something wasn’t right, you were just out of luck. No product and no market. You’d end up with an algorithm that wasn’t exactly correct and a design that wasn’t necessarily the best architecture.”
“All of this leads to the fact that the benefits for system-level design are that it allows you to get the best architecture in place, and to make sure that the implementation is optimal, without having to break the verification flow in doing it. With system-level design, you get accurate implementation of your algorithm and you can do it quickly.”
“So the crucial process in ESL is to develop the model, refine the model, decide what to implement in software and what to implement in hardware. You make architectural decisions that you’d like to be able to do on the fly, doing trade-offs through virtual prototypes using performance models. Then, from there, you determine what’s going to be in hardware and what’s going to be in software.”
“Of course, the ideal says you could take your algorithm implementation directly from the C model untouched, without having to write the thing in RTL - perhaps using FPGA prototypes and synthesizing directly from the C-based models. This kind of quick implementation of the algorithm leads to rapid prototypes that can verify the algorithms in the hardware even faster than simulations can run the C code. This algorithmic or “behavioral” synthesis is the enabler for ESL. This is the problem statement, the overall philosophy and the general direction that ESL is headed in. Understanding this problem provides a way to define ESL.”
“So, at this point we need to be able to define behavioral synthesis. A lot of the reason that ESL didn’t work the first time around in the industry is that people promised too much from behavioral synthesis. It was nothing more, at that point, than EDA alchemy. People were saying, ‘Our tool will translate C code into perfect hardware.’”
“But, that wasn’t realistic then, and it’s still not realistic. It’s just too difficult even today, and people are still smarter than machines. In the end, you can give the machines that do design a lot of help, and they certainly save a lot of time, but human intervention makes the difference between output that is trash and output that’s good.”
“C-based code can model algorithms at higher levels of abstraction, and there are now tools for implementing directly from that, but that’s not the same as taking C code and never touching it before getting a design out. Behavioral synthesis has to do with defining the process for getting from algorithm to implementation. To get to hardware, we have to add things like concurrency, timing, and data types. Both the tools and the users have to deal with these things.”
“Looking first at concurrency, behavioral synthesis allows you to take advantage of the parallel nature of hardware. In hardware, some algorithms can be made to run faster than on a processor by spreading out things to save time. But, how to tell what should be parallel and what should be sequential?”
“One explicit technique is for the user to specify in the code that we want this part of the design to be sequential, and we want this part to be parallel. Or, in some cases the tools can figure out the partitioning automatically. In general, the user will have to define the broad strokes in the code, and then give the compiler a chance to concentrate on the smaller things. In that strategy, user interaction defines the parallel portions of the design to achieve better results.”
“In SystemC, we’re using constructs like SC_METHOD - or SC_THREAD - to allow the user to explicitly define those parallel portions of the design. In SpecC or Handel-C - and, remember that our tools at Celoxica originated with Handel-C - there are “par” statements. The C code is by default sequential unless you insert a “par” statement to define what to implement in parallel.”
“Another challenge in system-level design is timing, because C code has no concept of timing in a hardware sense. So, behavioral synthesis has to be able to implement clocked processes. You can explicitly define the clock cycles, or you can do this through rules in the language, different constructs in the language. Or you can have the compiler try to achieve timing based on user-defined constraints.”
“Some tools try to achieve timing by adding proprietary statements or labels within the code, which tell the tool, for instance, “I need 5 clock cycles between labels A and B.” The compiler then tries to go out and meet those constraints automatically and responds with the results.”
“Our concept here at Celoxica is to give the user direct control using standard language constructs to get real designs out with deterministic results. For example, you can insert explicit timing within SystemC. Every time you want a clock edge, you put in a ‘wait’ statement. In that way, everything that happens between ‘wait’ statements happens on a particular clock cycle. In Handel-C, it’s a little different, however. It’s a rule-based language where an equal sign denotes a clock cycle. Every assignment with an equal sign advances the clock one cycle in sequential sections of the code. Assignments within “par” statements happen in one clock cycle. All of this thinking clears up the confusion, or in any case takes the focus off of the smoke and mirrors of empty ESL marketing promises - that promise that you can run your design from untouched C code and you’ll get a perfect hardware implementation out.”
“That promise is smoke and mirrors because you’re always going to have to deal with:
- Timing/Clock domains
- Data Types
- Resource Sharing
and those are problems that every tool has to attack. It’s how to do that, which is being debated today so hotly within the ESL community.”
“At this point in my presentation, I describe how our SystemC and Handel-C tools compare with those from our competition at Forte Design and Mentor Graphics.”
“What we do at Celoxica is to provide direct user control from C-based code for really good results and productivity. Just as you can write good VHDL or good Verilog code - just as you can write bad VHDL or bad Verilog code - you can write good or bad SystemC code for synthesis.”
“In our tools, versus those from our competition, we have the philosophy that the user knows best here. The user will have complete control over everything. For concurrency and timing, we have the user explicitly define those things in their code. That makes the process standard, not proprietary, and means they can take their code and use it in the competition’s tools or use it in standard simulation tools. But, we have the user explicitly define the concurrency. We adhere to all the standard reference manuals here, but again - the user must explicitly define things so that we can get explicit control.”
“Based on this strategy, our tools can handle multiple clock domains, and can handle the interface between clock domains. Synthesis re-timing can help to optimize things, as well, so the user’s explicit definitions can stay at a high level.”
“In the tools from Mentor Graphics, they say you can use any old C code and their tool will synthesize. But the reality is, the user must add data for concurrency and timing, etc. in a GUI, and the GUI stores constraints provided by the users. Then the edited GUI output is synthesized. The downside to that approach is that you can only do a block-based design because the tool can only take in so much complexity before it’s too difficult to use. And, it won’t support multiple clock domains.”
“Forte Design’s tool, Cynthesizer, is a little different. It doesn’t use a GUI, but it uses command-based functions. Forte is trying to solve things heuristically, using trial and error to get the results out. The problem there is that approach also limits you to a fairly simple problem set, which again is block-based only. The other problem is that trial and error is random, so that one little change in the code produces a completely different result. That generates inconsistencies plus limits the user to a single clock domain.”
“So, we believe that what we’re offering is not EDA alchemy. It’s not smoke and mirrors, it’s a functional development and implementation scheme, and tools that allow you to split out the design into the hardware and the software. To do this in ESL, there are two tracks from algorithm to implementation. The first track is language based - system-level designers come up with the algorithm in C-based code and move through functional design, to architecture definition and analysis, to implementation. Celoxica provides some good solutions for going from specification to implementation, but of course by no means provides all of the possible ESL tool sets for this track.”
“The other track used by a different type of designer is the block-based approach. You’ve got IP that already fits into your design, so the system-level tools try to make use of that existing IP. The slides in this portion of my presentation indicate where we have tools in each part of the possible ESL tool set for each track, and where we don’t.”
“Celoxica at this point has also introduced some block-based design tools, but we know we have some holes there. There are holes today in the flows from every company that describes itself as an ESL design tools company. Customers today must partner with a number of different companies to get the full flow - to get all the way from specification to implementation for all possible types of design. That fact is another part of the reality and the debate on ESL that’s very important to point out.”
“In ESL today, no one company has everything. Of course, there’s marketing motivation to say, ‘Use us. We’ve got everything.’”
“But, people get confused when they hear a company say that and then find the reality is something different - which only adds to the problems and the misunderstanding. At this point, everybody has got to see themselves as only providing a piece of the overall ESL solution. I understand that Gary Smith is going to be conducting an industry wide conversation this year to try and establish a complete ESL flow. I would very much like to be part of that conversation.”
“At this point, as Gary Smith and Daya Nadamuni both acknowledge, Dataquest has missed some stuff in their ESL forecast. It’s as if they’re looking at the traditional CAD groups doing traditional RTL-to-GDSII design and seeing a slow-down there. From our perspective, however, that’s not where things are happening in ESL. From our perspective, progress in ESL is happening in other sectors where system designers have algorithms to quickly implement into embedded systems using processors, fixed and programmable hardware and board peripherals. And, from our perspective, ESL is definitely accelerating. That’s what our business and technology motivation is based on.”
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Commerce & Industry
AccelChip Inc. announced what the company describes as significant new MATLAB language support that improves the ability to create forward-error correction algorithms written in MATLAB for synthesis and verification in its AccelChip DSP Synthesis product. Enhancements include: a new AccelWare Advanced Math Toolkit with matrix inversion and factorization to generate hardware implementations of complex algorithms used in wireless communications applications; new IP cores including Reed-Solomon decoding; new native Galois field support in the AccelChip DSP Synthesis tool; Improved support for two-dimensional array operations; wider variety of designs using matrix- and array-based operations can be synthesized and verified using AccelChip products; support for Virtex-4 devices; and support for Cadence’s Incisive Simulator
Agilent Technologies Inc. and Synopsys Inc. announced a new diagnostics reference methodology, which has been designed to speed fault localization and failure analysis. The methodology relies on the Agilent 93000 SmarTest Program Generator (PG) 2.2 and the Synopsys TetraMAX ATPG tool, in conjunction with the Agilent 93000 SOC Series test platform. The companies say the combination of tools automates the bi-directional information sharing between EDA and ATE required for scan diagnostics.
Aldec, Inc. announced the release of Active-HDL 6.3, described as the Actel edition. The company says that when Active-HDL is connected with Actel Designer (aside from synthesis), the system becomes a closed environment to the engineer. It has unrestricted VHDL, Verilog, EDIF or mixed simulation, which can execute all Actel implementation tools from the Active-HDL GUI. Active-HDL is compatible with most third-party synthesis tools from various companies including, Synplicity, Magma, Synopsys, and several FPGA-vendor provided tools.
Altium Ltd. announced that its Nexar system design software has been updated to support v4.2 of Altera’s Quartus II development software. James Smith, Director of EDA Vendor Relations at Altera, is quoted: “As the only development tool that supports FPGA, CPLD and structured ASIC designs, the Quartus II software allows Altium customers to easily target their prototyping and production solutions using our programmable logic devices.”
Aprio Technologies Inc. announced the release of its first products, the Halo suite of tools, which include Halo OPC, Halo Sim and Halo-Cal. The company says the products deliver a “fresh and effective answer to the thorny problems that come with chip design re-spins, designs that need OPC (optical proximity correction) modification to solve yield issues, or modified designs that require a quick change to mask data (also called ECOs). Because qualification of an OPC tool can take considerable time and require several test wafers, Aprio has chosen to architect its Halo suite to leverage incumbent OPC tools when applicable. In those instances, the Halo-Cal tool is used to generate models for Halo-OPC and Halo-Sim that mimic the behavior of the already-qualified tool. This calibration tool makes it possible to use Halo-Sim for finding errors in existing OPC results while Halo-OPC is then used to fix those errors in a style consistent with the tool initially used.” Aprio says the Halo suite of tools complements existing OPC generation tools that have already been qualified by the manufacturer.
ARM announced that LG Electronics, Inc. has licensed ARM OptimoDE embedded signal processing technology for use in LG’s video encoding and decoding product lines. LG says the first product that will use from OptimoDE technology is an H.264 based HDTV. The technology will be expected to provide the processing performance required by HDTV frame rates and frame sizes, while still retaining reprogrammablity to accommodate multiple video decoding standards.
BYO Solutions, Inc. announced the Partition-Pro partition tool designed for partitioning "big ASIC design in RTL description across multiple FPGAs automatically."
Cadence Design Systems, Inc. announced that NEC Corp. used Cadence’s Encounter design platform to develop “the complete 90-nanometer chipset for one of the world’s fastest vector supercomputers. With Encounter technology, NEC achieved a 2x improvement in chip performance on its most advanced, highest performance 90-nanometer vector supercomputer chipset to date. The NEC SX-8 chipset is comprised of four 90-nanometer designs, including a hierarchical 9-million instance chip that was routed flat for final engineering change order implementation and rapid design closure.”
Cadence also announced that Toshiba America Electronic Components, Inc. (TAEC) has introduced a design kit for Custom SoC and ASIC customers using Cadence’s Encounter RTL Compiler synthesis. The new kit supports designs for implementing in TC280 (130-nanometer), TC300 (90-nanometer), and newer process technologies.
Cadence also announced that Oki Electric Industry Co., Ltd. has taped out a chip for Oki’s uPLAT SoC design platform with Cadence’s Encounter RTL Compiler synthesis. The companies say that with Encounter RTL Compiler, Oki reduced power by 45 percent and area by 12 percent.
Cadence announced the release of Encounter Conformal Constraint Designer, which the company says automates the generation and validation of design constraints at all stages of the design process from RTL to final netlist. The company says the product performs comprehensive design constraint quality checks that help reduce the number of iterations due to invalid constraints. Design constraints are used to direct synthesis, timing analysis and place and route to meet a chip's timing, area and power requirements. Encounter Conformal Constraint Designer is designed to help pinpoint the root cause of constraint problems.
Cadence announced new capabilities that the company says will enable wireless chip designers and manufacturers to have better insight into the mixed-signal and RF challenges that surround wireless design. The new Cadence product offering combines "new Cadence RF extraction technology, two new design flows tailored for wireless chip design, Engineering Services, silicon-proven IP, and integration with technology from industry-leading Cadence partners Agilent, CoWare, Helic, and Mathworks. The RF IC flow [features] Assura RF, the new Cadence technology that delivers complete extraction for RF design. The two new design flows that are included [are] based on 802.11b wireless LAN design IP. These flows enable simultaneous verification of the RF, analog and digital domains together and verification of the wireless IC design in the context of the system. The flows integrate technology from Cadence partners to help streamline wireless design."
Celoxica announced that important algorithm IP, and a block-based graphical design entry platform, have been added to the company’s portfolio of ESL design tools. Jeff Jussel, Vice President of Marketing at Celoxica, is quoted in the Press Release: “There are two popular methods of design entry in ESL design tools; block-based schematic-style entry and software-style algorithmic coding using text-based descriptions. With PixelStreams, we’ve fused these approaches in a block-based graphical editor manipulating a library of C-based video processing models as well as custom C-language models. When combined with C-language synthesis, PixelStreams provides the absolute fastest way to get from algorithm concepts to hardware implementation for applications using these imaging functions.”
Celoxica also announced version 3.1 of its DK Design Suite, DK3.1, which is designed to provide high-level system co-design, verification and C-based synthesis for complex algorithm implementation to high-density FPGA and Programmable SoC devices. DK3.1 also includes performance upgrades to the Nexus-PDK co-verification environment and new device support in the integrated Platform Developers Kit (PDK) board and processor support packages. DK3.1 enhances the implementation path from prototype to SoC through high-level synthesis characterized by IEEE compliant VHDL and Verilog output, automatically generated from complex C algorithms.
CoWare Inc. announced an expansion to its ConvergenSC Model Library with the addition of ARM PrimeCell peripherals. The library now contains IP platform models for peripheral. The companies say that their cooperative effort has allowed CoWare to use the golden RTL and test benches to create these SystemC PrimeCell models.
CriticalBlue announced it has completed a benchmark project validating its Cascade tool with respect to Synopsys’ RTL implementation flow. The company says it worked with a "leading" semiconductor company who defined the embedded software benchmark example and its target gate count and performance constraints, and Cascade determined the available solution space and to generate synthesizable RTL for suitable co-processor architecture. No modifications were made to the original embedded software. Synopsys DC and VCS were provided to CriticalBlue through a Synopsys marketing program.
Denali Software announced that Ubicom, Inc. has selected Denali’s verification IP products for its chip design and verification projects. The companies say that Ubicom engineers use Denali’s PureSpec verification software to model and simulate interactions between its chips and other devices in the target system.
Forte Design Systems announced that Toshiba Corp. has chosen Forte’s Cynthesizer SystemC behavioral synthesis product for use in their SystemC design flow. The companies say they have entered into a multi-year agreement to use Cynthesizer in Toshiba’s next-generation system-level ICs for the consumer, networking and computer markets. Seiichi Nishio, Senior Manager of Methodology at Toshiba, is quoted: “ After extensive evaluations, we determined that by using Cynthesizer, we can substantially reduce the time to design and implement next generation products so that we meet customer needs while taking advantage of the increasing performance and complexity that our advanced technologies provide.”
HARDI Electronics AB announced availability of a new motherboard in the company’s HAPS family, designed for access to multi-gigabit serial links, embedded PowerPC processors, and 1600+ pairs of LVDS signals. The board is named HAPS-20 and is for designers who need high-speed prototypes of large ASICs. The board can be used as a stand-alone device to prototype ASIC designs up to 4 million gates. Capacity can also be increased by stacking two or more HAPS-20 boards together. The HAPS-20 conforms to the HAPSTrak standard, and therefore is backward and forward compatible with various generations of HAPS motherboards and daughter boards.
IMEC announced that it has achieved what is described as the smallest triple-gate device SRAM cell reported to date. The device is a 6-transistor SRAM cell with an area of 0.314mm2. The SRAM cell has a static-noise margin of 240mV at 1.0V operation and shows good functionality down to 0.4V with a symmetric butterfly curve. The cell also shows great potential for scaling down to the 32nm node.
Knowledge*on Semiconductor announced the availability of new design kit for the Agilent Technologies’ Advanced Design System (ADS). The design kit contains various passive components, as well as the three types of HBT. The companies says that RF engineers will benefit from the design kit because it includes accurate models for 214 inductors, 30 capacitors, resistors, via hole, pad and transmission line, which the foundry provides with. The design kit has a temperature scalable HBT model; the accuracy of the model is confirmed through temperature dependent DC and frequency measurements.
Magma Design Automation Inc. announced QuickCap NX, which the company describes as an enhanced” version of its QuickCap parasitic capacitance extraction tool. Added capabilities include: new process modeling, technology model encryption, a parallel execution mode, reference-level SPICE netlist generation, and a new 3D graphics viewer. Per the Press Release: “QuickCap NX is a highly accurate 3D solver that precisely models advanced process effects such as OPC, CMP and trapezoidal wires … With better process models, QuickCap NX users can do more accurate noise and timing analysis and achieve design closure faster. QuickCap NX also includes technology file encryption capabilities that provide foundries with a secure method of sharing additional process information with their customers, allowing them to further enhance the accuracy of their parasitic extraction. Magma has added a 3D graphics viewer to simplify and accelerate the debug of new complex circuit structures and technology files. QuickCap NX also provides parallel operation to reduce runtime.”
MagnaChip Semiconductor announced a new Process Design Kit (PDK) that supports Agilent’s RF Design Environment (RFDE) EDA software. MagnaChip says the PDK contains the full frequency range for its 0.18-micron mixed-signal/RF CMOS processes, from DC through baseband and into the RF range, thus allowing designers to simulate the entire SoC design and therefore ensuring correct operation at all frequencies. At the 0.18-micron node, these frequencies typically range from the audio and video frequencies in the baseband to 5 GHz in the RF band. In the future, designers are expected to be able to produce frequencies of higher than 10 GHz in the 0.13-micron node.
MatrixOne, Inc. announced that Comau Pico selected MatrixOne as its standard PLM environment. Comau Pico says that its adoption of MatrixOne PLM comes after several successful implementations of MatrixOne in other business units of the Comau Group.
Mentor Graphics Corp. announced that its Platform Express XML-based rapid SoC design creation tool now supports the SPIRIT 1.0 specification for IP design reuse. Ralph von Vignau, Chairman of SPIRIT and Director Technology & Standards of Philips Semiconductors, and CTO for the Reuse Technology Group, is quoted in the Press Release: “The success of SPIRIT depends on EDA vendors supporting the standard with their tools. Mentor is a technology contributor and active participant in creating the SPIRIT standard, so it’s great to see this work being successfully deployed in Platform Express.”
Mentor Graphics announced that TSMC used a comparison of Calibre xRC results, field solver data and silicon measurements as part of the validation for its 90-nanometer process technology. The companies say that TSMC and Mentor Graphics worked collaboratively on the test structures and the measurement technique to accurately quantify and measure 90-nanometer parasitic effects.
MIPS Technologies, Inc. and Virage Logic Corp. announced that using a MIPS32 24Kc core plus Virage Logic's Area, Speed and Power (ASAP) Logic High-Density (HD) libraries and ASAP Memory HD memories in a TSMC 0.13G process, the companies have produced a tape-out ready design for a 333 MHz processor in 3.7 mm2, consuming 166.5 mW and delivering 480 Dhrystone MIPS (DMIPS) performance.
Open Core Protocol International Partnership (OCP-IP) announced the availability of CoreCreator 4.0. OCP-IP says that CoreCreator provides a single graphical or command-line-based environment for validating Open Core Protocol (OCP) implementations. Version 4.0 is fully compliant with, and supports OCP 2.0. CoreCreator 4.0 streamlines generation and packaging of core models, interfaces, timing parameters, synthesis scripts, test vectors, and verification suites necessary for efficient IP core reuse and SoC integration.
The Optical Internetworking Forum (OIF) announced that six of its member companies will demonstrate interoperability functionality using the OIF’s recently approved Common Electrical I/O (CEI) Implementation Agreement (IA). The demonstration will take place at DesignCon 2005, and will include Altera, Interconnect Technologies (A Northrop Grumman company), Molex, Tyco Electronics, Vitesse and Xilinx. Test equipment from member companies Agilent Technologies Inc. and Tektronix, Inc. will provide test equipment for the demonstration.
Prosilog SA announced the release 2.2 of its Magillem platform-based design tool. The company says this release includes the “SPIRIT Editor” module, which allows the packaging of IP blocks according to the SPIRIT 1.0 specification released in December 2004. Ralph von Vignau, SPIRIT Chairman, is also quoted in the Prosilog Press Release: “We are pleased with the traction that SPIRIT has gained in the market with the delivery of the version 1.0 specification. Companies such as Prosilog, are delivering SPIRIT-compliant EDA tools, demonstrating that an ecosystem focused on an open standard for IP reuse is building rapidly.”
Pulsic Ltd. announced that it has licensed its Lyric Physical Design Framework to ON Semiconductor. ON Semiconductor says it has licensed Lyric components for floorplanning, standard cell placement, interactive editing and automatic routing of its next generation of mixed-signal designs.
QualCore Logic announced availability of 15 “silicon-validated” analog IP cores and special inputs/outputs (I/Os) for graphics and memory interface applications. Each of these was successfully validated in 0.13-micron process technology from two leading foundries to reduce risk and accelerate product development of system-on-chip (SoC) designs. The 15 analog IP cores and special I/Os are available in the 0.13-micron 1.0v/3.3v process technology and are delivered as GDS II files. Mahendra Jain, QualCore Logic’s President and CEO is quoted: “QualCore Logic’s strategy is to build the largest and most diverse portfolio of silicon-validated analog and mixed-signal IP and special I/Os. These 15 new IP cores bring that number to more than 400.”
ReShape, Inc. announced it has shipped its enhanced PD Builder, which the company says supports SoC Encounter Global Physical Synthesis (GPS) from Cadence Design Systems. ReShape says it worked in collaboration with multiple customers that use Cadence software and, utilized the PD Builder Open Flow feature to insert "expert tool user practices" into its programmable reference design flow.
SMSC and TransDimension announced completion of USB-IF On-The-Go (OTG) compliance testing of a Hi-Speed USB solution utilizing a stand-alone transceiver. Per the Press Release: “TransDimension’s Hi-Speed USB controller IP with a UTMI+ Low Pin Interface (ULPI) interface block and SMSC’s USB3300 ULPI stand-alone physical layer transceiver (PHY), are the first Hi-Speed USB products to pass OTG compliance testing, which is governed by the USB Implementers Forum (USB-IF). ULPI modifies the well-known UTMI+ link/PHY interface to significantly reduce the pin count necessary for discrete USB transceiver implementations to support host, device or OTG functionality.”
Synopsys, Inc. announced that Winbond Corp. has used Synopsys’ Galaxy Design Platform for Winbond’s latest 130-nanometer MPEG-4 multimedia chips - and had first-pass success. Per the Press Release: “Winbond’s MPEG-4 chip is representative of leading-edge 130-nm designs, where utilization of greater than 80 percent of the silicon area is fast becoming the norm. Congestion and increased risk of SI issues are more prevalent in chips of this density, and can contribute to significant increases in chip failure, declines in yield at target frequencies, and reduced performance.” Edward Wan, Senior Director of Design Services Product Marketing at TSMC, is quoted in the Press Release: “Synopsys and TSMC have partnered to ensure that our mutual customers targeting TSMC’s advanced technologies can take advantage of TSMC Reference Flow 5.0 and TSMC in-house library to achieve the best quality of results, accuracy, and time to volume. Winbond’s silicon success demonstrates that our combined flow and TSMC in-house libraries are proving to be seamlessly integrated and highly effective for the most complex designs.”
Synopsys, Inc. and Grace Semiconductor Manufacturing Corp. announced that Synopsys' Professional Services group and Grace have jointly developed a reference design flow for Grace's 180-nanometer processes. The companies say the RTL-to-GDSII flow is based on Synopsys' Galaxy Design and Discovery Verification platform, and that end-users can download the pre-verified reference flow, which is available immediately from Grace.
Synopsys also announced that UMC is using Synopsys’ alternating aperture phase-shift mask (AA-PSM) technology to improve manufacturability for its 90-nanometer process. The companies say the manufacturability improvements are achieved through increased lithography resolution, a larger process window, and better performance. They also say that UMC and Synopsys engineers worked together to retarget an FPGA chip to the AA-PSM process using Synopsys’ DFM flow.
Synopsys also announced that Artisan Components, Inc. has standardized on Synopsys’ ESP full-custom memory equivalency checker for its new low-power, high-density Metro Platform memories. Dhrumil Gandhi, Senior Vice President of Product Technology at Artisan, is quoted in the Press Release: “ In order to support leading-edge low-power design techniques, Artisan’s Metro memories are significantly more complex. Synopsys’ ESP verification solution plays a major role in helping us meet our customers’ first-pass silicon requirements.”
Synopsys also announced that CEVA, Inc. has taped out its next-generation high-speed serial interface chips and the CEVA-Teak DSP using Synopsys’ Galaxy and Discovery platforms: Physical Compiler and Astro products for increased capacity, PrimeTime SI tool for signal integrity, Power Compiler products for power management, and VCS and NanoSim software for mixed-signal chip sign-off.
Tensilica, Inc. announced that it has based its FPGA prototyping design flow on the Design Compiler FPGA (DC FPGA) tool from Synopsys. The companies say that DC FPGA supports key design elements of the Tensilica processor.
Tensilica also announced that NVIDIA Corp. has licensed the Xtensa LX configurable processor. The companies say this license will allow NVIDIA to add specialized functions to its outstanding graphics capabilities in new SOC designs. Chris Malachowsky, NVIDIA Co-Founder and Vice President of Hardware Engineering, is quoted in the Press Release: "For the application areas we are targeting, the extensibility and performance of Tensilica’s Xtensa LX microprocessor were key factors in our license decision."
Tensilica also announced that LG Electronics has used the Xtensa configurable processor core to deliver what the companies describe as "the world’s first mobile phone capable of receiving digital broadcast signals. Compatible with the Terrestrial digital-multimedia-broadcast (T-DMB) system, a broadcast system currently being rolled out in Korea, the new mobile phone is powered by a sophisticated digital media processor which was designed using the Tensilica Xtensa processor core and design environment."
Tower Semiconductor announced the availability of Virage Logic’s Nonvolatile Electrically Alterable (NOVeA) embedded memories for production on Tower’s 180-nanometer CMOS logic process. Per the Press Release: “NOVeA is the industry’s first embedded reprogrammable nonvolatile memory (NVM) to be manufactured on a standard CMOS logic process without any additional masks or process steps.”
TransEDA announced SystemVerilog support in new versions of its VN-Cover and VN-Check tools. The company says that by delivering these new versions, TransEDA says it is providing support for the emerging SystemVerilog standard, and that VN-Cover can take advantage of new SystemVerilog constructs such as enumerated types, records, user-defined types, etc., and still accurately measure code coverage on their design in the same way they do with VHDL and Verilog.
Virage Logic Corp. announced its third-generation Self-Test and Repair (STAR) Memory System. The company says the STAR Memory Systems provides “cost-effective on-chip testing and repairing of designs embedding megabits of memories, but adds significant enhancements that result in faster time-to-market, lower test costs, smaller area and better yield for complex SoC designs. The enhancements provide increased intelligence and automation. In nanometer SoC design, soft errors, memory leakage and the need for high-speed testing are just a few of the challenges plaguing designers. These challenges are compounded by the ever-increasing numbers of memory blocks. Virage Logic has added intelligence in both the test and repair architecture and algorithms to meet these challenges. The STAR Memory System’s embedded error-correcting-code (ECC) circuitry employs the widely used Single Error Correction, Double Error Detection (SEC-DED) approach to automatically detect and correct soft errors for improved reliability.”
I spoke by phone with Krishna Balachandran, Senior Director of Product Marketing at Virage, about the announcement. Krishna told me, “We’re announcing a new test and repair solution for embedded memories that advance nanometer processes. The processes have gotten so much more complex, and taking that much longer to mature - while the memory content on the chip is going up dramatically at the same time. People, in the past, were using tens of memories. Now they’re using hundreds, or even over a thousand on a chip, such that memory is now the driver for overall yield on a design. Therefore, it’s appropriate that memory repair and test solutions must provide the avenue towards decent yields and product profitability. In this announcement, we’re addressing the challenges by adding intelligence and automation to the STAR Memory System. It’s a brand new architecture for an evolving product.”
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Economics & Finance
EDAC’s Market Statistics Service (MSS) announced that Q3 2004 EDA License and Maintenance revenue, the largest EDA revenue category, declined 3% over Q3 2003. Total Q3 revenue, which included semiconductor IP, was $953 million, a 2% decrease from Q3 2003. Wally Rhines, EDAC Chairman and Chairman and CEO at Mentor Graphics, is quoted in the Press Release: “Despite a weak third quarter, the EDA market has shown a positive three percent growth rate on a year-to-date basis. The weakness in Q3 was focused in North America, where all major categories were down versus Q3 2003. On a product-line basis the recent Q3 weakness was driven primarily by the IC/ASIC Physical Design categories, while a number of other key categories that have usually shown growth remained relatively flat versus a year ago.”
MSS reported that EDA’s largest tool category, Computer-Aided Engineering (CAE), generated revenue of $453 million in Q3 2004 - no change from the same period in 2003. IC Physical Design & Verification revenue at $272 million was down nine percent from $298 million in the same period last year. Revenue for Printed Circuit Board (PCB) and Multi-Chip Module (MCM) Layout totaled $81 million in Q3 2004, one percent less than in Q3 2003. Services revenue at $66 million showed a 5 percent increase over the same quarter last year. Semiconductor IP revenue rose eight percent to $81 million over third quarter of last year. This rise was in part due to growing SIP participation in MSS reporting with CAST and Tensilica initiating participation in the second quarter. North America revenues declined by nine percent to $472 million while Europe revenues of $192 million showed a four percent rise, and Japan at $183 million was also up four percent. Double-digit growth continued in the rest of the world, which showed total revenues of $107 million, up 11 percent from Q3 2003. Reporting companies employed almost 20,500 professionals in Q3 2004, four percent more than Q3 2003. This was the third consecutive quarter of new highs in employment reported by the MSS since it began tracking employment data in Q1 2000.”
Mentor Graphics announced that its fourth quarter 2004 bookings and revenues had achieved record levels, with revenues expected to exceed Thomson First Call consensus estimates of $204 million. Bookings for the fourth quarter were up about 40%, year over year. The company also grew backlog significantly, up approximately 35% from the fourth quarter of 2003. Fourth quarter special charges are expected to result in GAAP basis earnings below guidance. Earnings per share on a pro forma basis are expected to modestly exceed consensus estimates. Fourth quarter bookings performance was broad-based across all regions and product lines, and not driven by any particular large transactions. All regions performed well with bookings in North America up 15%, Europe up 50%, and Japan and the Pacific Rim both up over 100% over the fourth quarter of 2003.
Nassda Corp. announced financial results for the quarter ended December 31, 2004, the first quarter of Nassda's fiscal 2005. Revenue for the quarter ended December 31, 2004 was $11.3 million, an increase of 16% from $9.7 million for the quarter ended December 31, 2003 and an increase of 2% from $11.0 million for the quarter ended September 30, 2004. Net income for the quarter ended December 31, 2004 was $1.3 million, or $0.05 per diluted share, an increase of 135% from $572,000, or $0.02 per diluted share, for the quarter ended December 31, 2003 and an increase of $68.6 million from a net loss of $(67.3) million, or $(2.50) per diluted share, for the quarter ended September 30, 2004. Operating expenses for the first quarter of fiscal 2005 were lower than expected, primarily due to lower litigation costs. As a result, Nassda says it was able to achieve an operating margin of 14% for the quarter ended December 31, 2004.
Xilinx, Inc. announced the launch of a $100M corporate venture fund, that the company says will fuel industry innovation within the company’s growing “ecosystem for programmable system design.” Initially, the venture fund activity will be focused in Europe and the U.S., with an emphasis on high-speed DSP, embedded processing and high-speed connectivity. Ecosystem Venture Fund proposals are reviewed by Xilinx business development for potential investments ranging from $250K to $5M. Applicants must meet the following criteria: Demonstrated commitment to the Xilinx ecosystem from a Xilinx executive sponsor to validate and advocate for the candidate company; Early customer validation of the proposed technology; Well-managed companies with sound business fundamentals and good potential for growth and profitability; Interest and/or engagement by other investors.
Synopsys, Inc. announced the Federal Trade Commission (FTC) has requested additional information and documentary material in connection with its review of Synopsys’ proposed acquisition of Nassda Corp. Synopsys says it will promptly respond to the FTC request. The FTC request extends the waiting period under the Hart-Scott-Rodino Antitrust Improvements Act of 1976. Synopsys announced on December 1, 2004, that Synopsys and Nassda had entered into a merger agreement providing for the acquisition of Nassda by Synopsys in an all cash transaction at $7.00 per share and, subject to the closing of the acquisition, to settle all outstanding litigation by Synopsys against Nassda and certain Nassda officers, directors and employees.
Nassda Corp. also announced that the FTC has requested additional information and documentary material in connection with its review of the proposed merger between Nassda and a subsidiary of Synopsys.
Cadence Design Systems, Inc. announced that it has signed a definitive agreement to acquire Verisity Ltd. Under the terms of the agreement, Cadence will acquire Verisity in an all-cash transaction. Upon closing of the acquisition, which is subject to customary shareholder and government approvals, Verisity stockholders will receive $12 in cash in exchange for each outstanding share of Verisity stock. Upon completion of the acquisition, Moshe Gavrielov, CEO of Verisity, will join the Cadence executive management team, and Yoav Hollander, founder and CTO, will, according to the Press Release, “play an integral role in setting Cadence’s verification technology direction.”
Mike Fister, President and CEO, Cadence Design Systems, is quoted: “The global electronics industry is under unprecedented pressure to develop and bring to market innovative products as quickly as possible. Our acquisition of this highly innovative team and successful business is consistent with Cadence’s focus on enabling the world’s leading electronics companies to address the demand for increasingly complex systems.”
Moshe Gavrielov is also quoted: “Customers are demanding solutions that automate the entire verification process and make it more predictable from planning to closure. This requires the integration of our VPA solution with a unified verification infrastructure. The combination of the two companies will greatly accelerate the delivery of these integrated solutions.”
Jasper Design Automation announced that it has acquired Safelogic. The terms of the transaction were not disclosed. The companies say the acquisition “brings together technology leaders in complementary areas within the formal verification market, creating a combined company with the EDA industry’s strongest solution for verification and debugging of block-level designs using assertions and high-level requirements. Safelogic brings to Jasper one of the world’s fastest formal proof engines … [and] the merged company has one of the formal industry’s strongest engineering teams, with development sites in Mountain View, Calif., Berkeley, Calif., and Göteborg, Sweden.”
Pär-Jörgen Pärson has joined the Jasper board of directors, and Jonas Risberg, a Safelogic board member, will participate on Jasper’s board as a board observer. All Safelogic employees became employees of Jasper Design Automation in December 2004, when the transaction closed. Safelogic was originally founded in 1999.
Harry Foster, chairman of the IEEE-1850 PSL Committee and chief methodologist at Jasper Design Automation, is quoted in the Press Release: “Safelogic is widely recognized as having made a major contribution to the development of the PSL standard, particularly as it relates to formal proof. In contrast to the many rudimentary and incomplete implementations out there, Safelogic has the most comprehensive support of PSL in the formal industry. This, combined with Jasper’s support of Verilog-based requirements and commitment to SystemVerilog Assertions, puts the combined company at the forefront of assertion language support.”
Kathryn President and CEO made these comments by phone: “I’m very excited about this merger, although it took a while to close. Jasper first got wind of the technology and technologists at Safelogic back in middle of last year when some formal tools developed by Safelogic outperformed the competition at a specific event. That was the tip of the iceberg. This is the team that has developed what is unquestionably the best of class in the world, best for ease of use and ease of adoption for formal verification. Now we’re finding incredible, complementary chemistry, and good camaraderie between the teams.”
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Politics & Government
The SPIRIT Consortium (Structure for Packaging, Integrating and Re-using IP within Tool-flows) announced the first public release of the approved SPIRIT specification. SPIRIT Version 1.0 is said to indicate that “for the first time SoC designers worldwide have access to an industry standard for IP reuse that will enable them to select, configure and integrate SPIRIT-compatible IP from multiple vendors using a range of different SPIRIT-compatible EDA tools and design environments.”
“SPIRIT Version 1.0 addresses SoC design at RTL level, but work is already underway to draft Version 2.0 of the standard that will extend the specification to cover comprehensive interoperability between tools and explicit support of Electronic System Level (ESL) Design and Verification. This will include, for example, the ability to launch application-specific tasks operating on SPIRIT formats from within different EDA tools. It will also enable provision of configurable IP for automated ESL design, assembly, verification and simulation. At this time, the SPIRIT 1.0 standard is available under a simple non-restrictive click-through license at: www.spiritconsortium.com.
Ralph von Vignau is quoted in the Press Release: “The release of an approved specification that has already been validated by leading IP and EDA providers within the SPIRIT consortium is a real win-win situation for the industry and users alike. It represents a major step forward in short time-to-market integration of the complex system-on-chip solutions needed for today’s and tomorrow’s embedded systems.”
Open Core Protocol International Partnership (OCP-IP) announced the availability of CoreCreator 4.0. CoreCreator provides a single graphical or command-line-based environment for validating Open Core Protocol (OCP) implementations. Version 4.0 is fully compliant with, and supports, OCP 2.0. It is said to “streamline generation and packaging of core models, interfaces, timing parameters, synthesis scripts, test vectors, and verification suites necessary for efficient IP core reuse and SoC integration. It also provides an environment for stimulating a core (or multiple cores) and analyzing performance and functionality in a system environment. The tool features a comprehensive design environment for importing existing IP cores or creating new IP cores OCP protocol and physical constraint compliance verification; and maximum frequency and gate area estimation. Its automated environment provides configuration, simulation, logic synthesis and timing analysis, as well as TCL scripting for auto-generation of configuration files and timing constraints.”
“CoreCreator also contains a physical constraint extractor and packager as well as a packager for all necessary verification files, including scan test and functional vectors. CoreCreator decouples core and system development, allows multiple-core development in parallel, provides a structured core debug and system-level design verification to reduce design time and risk, ensuring rapid time to market. The CoreCreator design environment gives users the freedom to choose their own EDA providers, tools, and design methodologies. Version 4.0 was approved for release after an extensive review and now supports all the latest enhancements to the OCP 2.0 specification CoreCreator 4.0 is available to OCP-IP members through the website: www.OCPIP.org.
Mentor Graphics Corp. announced it has joined the Serial ATA International Organization (SATA-IO). The SATA-IO is a non-profit organization that works to sustain the quality, integrity and dissemination of the SATA technology (a storage connectivity technology responsible for transmitting data to and from storage peripherals) by maintaining the specifications, promoting and marketing the benefits of the technology and creating future interface features and specifications that carry storage into the next decade. As an active SATA-IO member, Mentor Graphics says it will help influence the future direction of SATA specifications as well as drive industry adoption of the SATA technology.
eASIC Corp. announced that the company was granted an additional patent for the company’s technology. The patent is titled “Customizable and programmable cell array” (6,819,136), and was issued on November 16, 2004 by the U.S. Patent and Trademark Office. The company says this patent “is a continuation of a previous patent (6,756,811) granted to eASIC in the area of chip customization. This patent protects the company’s unique configurable logic technology, which utilizes electrical programmable cells connected with lithography-defined custom interconnections. The patent also protects the use of a coarse-grain array fabric, where each cell comprises of flip-flops with some fine grain functions such as inverters or multiplexers used as logic gates.”
Nassda Corp. announced it has been issued a patent by the U.S. Patent and Trademark Office for its method of describing a hybrid system of static analysis and dynamic simulation for IC design verification. The patent, #6,820,243, covers technology, which is used for circuit-level timing and crosstalk analysis of leading-edge custom digital designs at 130nm processes and below. Graham Bell, Senior Director of Marketing at Nassda is quoted: “This patent forms the basis for a new innovative approach to circuit-level timing analysis. For leading-edge custom digital designers, verification can no longer be limited to either dynamic or static analysis at the circuit-level. We believe our innovative hybrid technology in HANEX delivers a new level of accuracy and performance by optimizing the advantages of both dynamic and static analysis methods.”
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U.C. Berkeley’s Donald Pederson passed away on December 25, 2004. He was 79 and had been suffering from Parkinson’s Disease. Dr. Pederson was a long-time faculty member at Cal, and is credited with spearheading the research effort in the 1960’s that resulted in the SPICE simulator, a technology still widely used today. In addition, Professor Pederson was graduate advisor to several generations of leading EDA technologists. Among his many honors, Dr. Pederson received the Phil Kaufman Award, EDA’s highest accolade, in 1995.
Ambric, Inc. has named Mike Butts as Vice President of Architecture, and Kevin Ross as Director of IP for the company. Prior to Ambric, Mike Butts was co-founder of a programmable IC platform company. In the 1980s, he co-invented hardware logic emulation using reconfigurable hardware-technology. He has also developed a number of reconfigurable chips and system products. He has worked, in addition, at Mentor Graphics, Quickturn Design Systems, Synopsys, and Cadence, where he was a Cadence Fellow. Butts has a BSEE and an MS in EE and CS from MIT. Kevin Ross is a patent attorney and, prior to Ambric, was a partner at Marger Johnson & McCollom, P.C., an IP law firm providing IP counsel to Ambric. Ross formerly practiced law in Seattle, WA, and in Milan, Italy, where he worked as a U.S. patent law specialist. Before practicing law, he was an application computer programmer. Ross has a BS in CS from Westminster College in Fulton, MO. In addition, he did graduate studies in EE and received his law degree, both from the University of Missouri, Columbia.
Applied Wave Research, Inc. (AWR) announced that it is teaming with Rohde & Schwarz. The companies say that the partnership will produce test solutions that include Rohde & Schwarz test and measurements instruments along with AWR software.
Arithmatica announced that Tony Curzon Price has been promoted to CEO, and Dave Burow to Executive Chairman. The company says, “Both executives have worked closely together during the past two years, and will continue to do so in the future, resulting in a seamless, transparent transition. A co-founder of Arithmatica, Curzon Price has run all UK R&D operations for the past two years, and now is expanding that role to lead all company operations worldwide. The company says that Burow has established the processes and infrastructure necessary to ensure a solid basis for growth, and that he will remain active in the company’s operations. Company headquarters will remain in Menlo Park, CA.
Calypto Design Systems, Inc. announced its arrival and said the company will have a strategy for bridging the gap between electronic system level design and IC implementation. The company says it intends to deploy EDA products based on proprietary technology that will connect system-level models and RTL design flows in order to support faster verification times and design at a higher level of sequential abstraction. The company announced its first broad-scale product release in Q2 2005. Calypto Design has also named the senior management team. Devadas Varma is CEO. Michael Sanie is Vice President of Marketing and Business Development. Larry Lapides is Vice President of Sales. Gagan Hasteer is Vice President of Engineering. Anmol Mathur is Chief Architect. Devadas Varma is a former Cadence fellow, and previously held CTO and senior engineering positions at Ambit, Viewlogic, and Mentor Graphics. Michael Sanie was Group Director of Industry Initiatives at Cadence and Director of Marketing and Business Development for IC Design at Numerical Technologies. He has also held marketing and technical positions at Actel, Compass Design Automation and VLSI Technologies. Larry Lapides was Vice President of Sales at Verisity. Prior to Verisity, he was busy building sales teams for Surefire Verification and Exemplar Logic. Gagan Hasteer was Director of Engineering for Innologic System prior to their acquisition by Synopsys. Anmol Mathur is described as the architect of the Cadence datapath synthesis engine and served on a tools development team at the MIPS division of SGI.
Catalytic Inc. says it has been selected from a field of hundreds as a finalist for this year’s EDN Innovation of the Year Awards. Instituted in 1990, the awards honor people, products and technologies that have shaped the semiconductor industry over the past year.
Mobilize, a product from Virtual Silicon Technology Inc., was named as a finalist for an EDN Innovation Award in Intellectual Property category. The winners of the EDN Innovation Awards will be chosen by EDN readers, editors, and an editorial advisory board and announced at an awards banquet on March 7th
Eagleware Corp. announced today that the company name has changed to Eagleware-Elanix Corp. to reflect Eagleware's recent acquisition of Elanix, Inc., an ESL design tool provider. In addition, the company announced a new version of SystemView, SystemView by Elanix 2005, with library support for the emerging Ultra-Wideband (UWB) IEEE standards.
eASIC Corp. announced that its Structured eASIC product was selected as a DesignVision Award finalist by The International Engineering Consortium (IEC) in the category of “Structured/Platform ASIC, FPGA, and PLD Design Tools”. The inaugural DesignVision Award recognizes companies for recent products and services that have added a new dimension to the electronic design industry and to the society as a whole.
eASIC Corp. announced that two new executives have joined the company’s management team. Ronnie Vasishta was appointed to Executive Vice President of Marketing and Salah Werfelli was appointed to Executive Vice President of Strategic Business Worldwide. Both Werfelli and Vasishta will report to company President & CEO Zvi Or-Bach. Prior to joining eASIC, Ronnie Vasishta was Vice President of Technology Marketing at LSI Logic. Prior to LSI Logic, Vasishta held process and test engineering positions at Motorola and STC Semiconductor. Salah Werfelli has 25+ years of experience in system and IC designs. Prior to joining eASIC, he was an Executive Consultant to various start-up companies where he helped to establish strategic directions and business partnerships. Previously, he served as Senior Vice President of Sales and Marketing for AmmoCore Technology, and held various executive positions at Cadence Design Systems. Prior to Cadence, Werfelli was an executive at Magma Design Automation. Werfelli started his professional career at Unisys.
Giga Scale Integration Corp. (Giga Scale IC) announced that its chip estimation tool, InCyte, has been named a finalist by the IEC for a DesignVision Award in the ASIC and IC Design Tools category of the first annual IEC DesignVision Award program. Winners of the award, which organizers say honors achievement in electronic design innovation, will be announced at DesignCon on February 1st.
Jasper Design Automation announced the formation of a Technical Advisory Board (TAB) made up of technologists from the academia working in the field of formal verification. Jasper says the TAB will advise the company’s management team on academic research trends in formal verification, provide guidance on Jasper’s technical product development, and educate students on the commercial trends in formal verification. Initial members of the TAB include Alan Hu, Associate Head of the Department of Computer Science at the University of British Columbia; Sharad Malik, Professor in the Department of Electrical Engineering at Princeton University, and Chair of DAC 2004; Satoshi Goto, Professor at the Graduate School of Information, Production and Systems, Waseda University, Kitakyushu, Japan; and Claudionor Coelho, Associate Professor at the Federal University of Minas Gerais, Belo Horizonte, Brazil. Jasper should be proud of this pretty heavy-duty crew!
Atrenta Inc. announced that Charles Schadewitz has been named as Vice President of Worldwide Sales. He will report to Chairman, President and CEO Ajoy Bose. Prior to Atrents, Schadewitz served as Vice President of Sales and manager of the company’s major accounts program at Cadence Design Systems. He came to Cadence after serving in a similar role at Simplex Solutions. Schadewitz has a BSME from U.C. Berkeley.
Additionaly, Atrenta announced that John Rizzo has joined to the company and will report to the Vice President of Marketing. Previously, Rizzo was at Intel, Oracle, Informative, and Apple Computer. He has a BSEE from Stanford. Simon Young has also been hired, reporting to John Rizzo. Previously, Young was at Nassda, Synopsys, Silicon Metrics, Mentor Graphics, Intel and TI. Simon Young has a MSEE from Imperial College in London. Finally, Alan Feinberg is also joining Atrenta as senior business unit director, having served most recently as vice president of marketing and North American sales at Monterey Design Systems. Before starting his own consulting business, Tekstart, Feinberg held several director-level sales and sales operations roles at Synopsys, including director of North American sales operations and director of western area sales. Alan has a BSEE from the University of Rochester and in MBA from Northeastern University.
Nascentric, Inc. announced the appointment of Vess Johnson as President and CEO, and Frank Childers as Vice President of field operations. Nascentric is a new company working in the area of IC design tools for timing power and signal integrity for nanometer-scale designs. Prior to Nascentric, Johnson was President and CEO of Silicon Metrics Corp. at the time when the company was acquired by Magma Design Automation. He was then General Manager of Magma’s Silicon Correlation Division. Prior to Silicon Metrics, he held management positions at Omniview Design Automation and Xynetix. Johnson has a BS in Mathematics, a BA in Philosophy, and an MS in Computer Science from the Bagley School of Engineering at MSU. Prior to Nascentric, Childers was Vice President of Worldwide Sales for Silicon Metrics. Prior to Silicon Metrics, Childers was an executive at Alliance Systems and Micrografx, Inc. He also has served in management roles at Mentor Graphics. Childers has a BS from the United States Air Force Academy and an MA from the University of Northern Colorado.
Nascentric also announced the appointment of Scott Yore as CFO, reporting to President & CEO Vess Johnson. Previously, Yore was CFO at Silicon Metrics up through its acquisition by Magma Design Automation. Earlier, Yore was at CCI/Triad (now Activant Solutions, Inc.), and Ernst & Young.
VaST Systems Technology Corp. announced that Alain Labat has been named President and CEO Labat has 20+ years of EDA industry experience. Prior to joining VaST Systems, Labat was CEO of TeraSystems and Founder, President and CEO of Sequence Design. He was previously with Synopsys as Senior Vice President of Worldwide Sales and Marketing. Labat has an undergraduate degree from INSEEC, France, and an MBA from Thunderbird, The Garvin School of International Management in Glendale, Arizona.
ZMD AG announced the appointment of David Sanchez as its Distribution Sales and Marketing Manager for the North American standard products (ASSP) business unit. Prior to joining ZMD, he was an account manager at Insight Electronics. Sanchez will be based in Melville, NY.
Applied Wave Research, Inc. (AWR) announced that TeraSoft, Inc. will be a value-added reseller of AWR software in Taiwan. James Spoto, AWR President and CEO, is quoted in the Press Release: “The growing microwave and RF design community and strong demand for AWR products in Taiwan is driving our continued expansion. We are pleased to partner with TeraSoft, which has an excellent presence in Taiwan and also has a reputation for customized and dedicated customer service.”
CoWare Inc. announced relationships with two universities - The Indian Institute of Technology (IIT) Delhi and IIT Kharagpur. The company says these relationships will “drive research and development efforts for ESL design tools and methodologies in India. As part of this relationship, both institutions will have access to the entire range of ESL tools from CoWare, support from the strong team at CoWare India Private Ltd. and inclusion in co-development projects to facilitate ESL research and adoption. CoWare will also offer ESL tool licenses to several other academic and research institutes in India through the government funded Special Manpower Development Program (SMDP) Phase II.”
Alok Kumar, Managing Director of CoWare India Private Ltd. says, “India’s traditional strength in the software domain makes it a pivotal player in the emerging ESL market. And as the leader in ESL design, it is important that CoWare partner with leading Indian universities like IIT Delhi and IIT Kharagpur to encourage ESL research and development, ultimately making it easier for our customers to make the move to ESL and gain competitive advantage.”
Tensilica, Inc. and eInfochips announced plans to set up a software development center in India, which the companies says will focus on extending the IP solutions around the Xtensa platform. eInfochips will also develop new embedded tools and testing suites for the Tensilica processor. Chris Rowen, President and CEO of Tensilica, is quoted: “We chose to partner with eInfochips because they’re based in India and understand how to run strong engineering teams that work closely with US companies.” Pratul Shroff, President and CEO of eInfochips, is also quoted: “ Our endeavor is to continuously seek new ways to add value and benefits to our partners. When you combine access to India’s strong engineering resources, with a proven outsourcing model, that we call Applied Outsourcing Model (AOM), companies like Tensilica can maintain their technical edge and, at the same time, save time in their development cycles.”
Zenasis Technologies announced it is now a member in the ARM Connected Community. The ARM Connected Community is a global network of companies aligned to provide a complete solution, from design to manufacture and end use, for products based on the ARM architecture. Jay Roy, Zenasis’ CEO, President and Co-founder, is quoted is the Press Release: “Zenasis helps ASIC and SoC design teams to quickly reach their target performance by injecting large timing gains into their designs that are significantly larger than gains achievable with conventional physical timing closure tools. We are excited to be part of the ARM Connected Community Program. We will continue to provide solutions to ARM customers enabling success over their competitors.”
Novas Software, Inc. announced that the company’s Verdi Automated Debug System has been selected as a finalist in the first annual IEC DesignVision Award program. Winners of the award, which organizers say honors achievement in electronic design innovation, will be announced at DesignCon on February 1, 2005.
Synopsys announced that Agere Systems has named Synopsys as the recipient of a Best-in-Class Supplier Award for 2004. Per the Press Release: “Synopsys was one of four companies singled out to receive a special award in its respective service area out of all Agere suppliers. The award cited Synopsys as best in class in General Procurement because the company … ‘led its competitors by providing great service for Agere’s design teams, a broad portfolio of competitive solutions, and flexibility.’”
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Festivals & Fairs
** DesignCon 2005 - DesignCon is sponsored by the International Engineering Consortium (IEC), and is for semiconductor and electronic design engineers. The conference will be January 31 to February 4, 2005 at the Santa Clara Convention Center. Synopsys’ Aart de Geus, Mentor Graphic’s Wally Rhines, and Cadence’s Mike Fister will deliver the conference keynotes this year. (www.designcon.com/conference/)
** IEEE ISSCC 2005 - The International Solid State Circuits Conference is taking place from February 6-10, 2005 in San Francisco, CA. This is the companion conference to IEEE’s International Electronic Devices Meeting, which takes place every December.
** DATE 2005 - Europe’s principle conference and exhibition for Electronic Design, Automation and Test happens each year in either Paris, France, or Munich, Germany. This time around it will be in Munich from March 7-11, 2005.
** ISQED 2005 - This will be the 6th International Symposium on Quality Electronic Design, and will be happening March 21-23, 2005 in San Jose, CA. The Topic of this year’s meeting will be “Design for Quality in the Era of Uncertainty.”
** DAC 2005 - The Design Automation Conference will be taking place at the Anaheim Convention Center June 13-17, 2005. All indications are that the EDA industry is picking and, and this year’s DAC promises to be a very well-attended event.
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Peggy Aycinena authors EDA Nation, and owns and operates EDA Confidential at www.aycinena.com. She can be reached at firstname.lastname@example.org.
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