Contents

Editor’s Note
History & Geography — "DVCon - Wally, Gary & Gabe"
Commerce & Industry
Politics & Government
Economics & Finance
Citizenry
Festivals & Fairs

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Editor’s Note

February and March are busy months for those who like to attend technical conferences - especially if you like conferences in Silicon Valley. Of course, the semiconductor industry spans all geographies on the globe, so only looking at things from a vantage point in Silicon Valley can be highly misleading. Nonetheless, people continue to look to this place for guidance and/or signposts of change and growth in the design automation industry. Hence, this month’s article on DVCon 2005.

DVCon is an intimate gathering of friends and enemies - people who work and compete for design starts, tools customers, and language dominance. It’s held each year around this time, and usually takes place at the DoubleTree Hotel in San Jose, CA. This year’s 3-day meeting was a good, solid gathering of the tribes - and although there were moments of rancor, in general, things went smoothly. Companies may be arch competitors, but on an individual basis - engineers and technologists have an easy way amongst each other, which lends a certain ambiance to meetings like DVCon.

I attended a number of different events at DVCon, but missed many other events of equal importance. This article details one keynote and two panels that pretty much define today what’s happening - for better or worse - within EDA. Mentor Graphics CEO Wally Rhines gave a well-received keynote address on Tuesday morning, February 8th. EDA Editor Gabe Moretti moderated a panel on Quality in Design on February 9th, in the early afternoon. And Dataquest’s Gary Smith moderated a panel on Catching up in ESL to close out the conference late that same afternoon.

Of course, DVCon showcased a lot more content that just these three items, but if you need to see the whole conference, it’ll be on-line starting February 23rd, on the DVCon website. All told, DVCon manages to portray a pretty detailed picture of where things are in hardware design. These days, that picture includes compelling evidence that a) things are inexorably moving up to higher levels of abstraction, b) verification technology is undergoing a marked consolidation, and c) achieving quality designs is not getting any easier.

I enjoyed my several days at DVCon. I learned a lot and believe that knowledge will be an asset as I head off to DATE in Munich next month. Across the paradigms of hardware/software, RTL/ESL, North America/ Europe, and global/local design & implementation - the interface between DVCon and DATE offers up a point/counterpoint that mirrors the situation in chip design today, here half way through the first decade of the new Millenium.

Peggy Aycinena
Editor

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History & Geography

"DVCon - Wally, Gary & Gabe"

Industry stalwarts orchestrate roadmaps to an unclear future

Chapter 1 - Mentor Graphics CEO Walden C. Rhines on Verification

Wally Rhines' keynote at DVCon - “Verification Discontinuities in the Nanometer Age” - was well received according to a lot of people in attendance. Rhines started by telling us that half of the design effort is in the verification, and not surprisingly there were 76 companies last year at DAC selling verification tools. There was also $47 million invested in 7 new verification companies in 2004. There are 12 sub-categories of verification tools within the EDA tool paradigm, and $1.18 billion is spent annually on verification, which is more than synthesis and place & route combined.

Despite all this effort, however, there's more bugs at each process node. At the current rate, Rhines estimated the hypothetical Pentium 10 will show up with 6,000,000,000 bugs in need of resolution. Ron Collete, per Rhines, says that 66 percent of every ASIC/IC design requires 2 or more respins. Bugs, Rhines said, want to track Moore's Law, but fortunately they don't. And why is that? Rhines said it's because the tools for verification get better enough fast enough that the trajectory of Moore's Law is not quite the trajectory of bug count. Nonetheless, the problems are enormous and growing.

Rhines posed the question asked by many, and then answered his own query: “How did the bugs get there? Engineers put them there.” Then he pleaded the case of the engineer. The methodology for design is wholly changing every 15 years and at this point, we're on the verge of yet another one of those changes. Rhines reviewed the history: source and drain design in the 1960's and 70's led to schematic capture and logic simulation from the 70's to the early 90's, HDL synthesis and simulation from the late ‘80s though to the early 2000's, and static timing analysis and equivalence checking from the 1990's to today. Given this history, can we know what's next? Rhines said, “Yes.”

He believes the verification of complex embedded blocks will constitute the biggest methodology shift since the move to HDLs, and the methodology shift will require change. However, even though technology changes quickly, people don't. Add that to that, the fact that EDA companies invest in tools, but designers invest in methodology - and you've got some serious speed bumps out on the straightaway in front of you. And we're bearing down on them pretty darn fast.

Rhines said that as we get to the point where the methodology is completely broken - although people rarely change, change will happen nonetheless. Assertion-based verification and functional coverage will be augmented by language exploration and increased availability of standards - and the next phase of the story will get underway.

With that background, Rhines moved into a detailed discussion of present and future realities in verification. He said assertions need to be everywhere and they'll require a lot of work up front. Expect to have 1 assertion for every 10 lines of code, he said. Why aren't people using assertions today? Well, they are, Rhines said, but the process is not standardized.

He credited PSL 1.1 and SystemVerilog 3.1a with going in the right direction there, and said those efforts mean the tool evolution is being enhanced as a result. He said that formal checking has a future and that model checking's just a year away. Assertions will be constrained for model checking, which will help with redundant verification cycles. Rhines said we need metrics and when everything's in place, “Model checking will take over the world.”

He moved to IP and showed a traditional S-shaped graph. He said things move slowly at the outset of a design project, and then at a more satisfying, linear clip mid-project. But progress slows to a crawl again at the end of a development project. He said experienced managers know that the last 5 percent of the gates that are designed today gobble up 31 percent of the project time. He said the situation's not improving and so, with respect to the verification portion of the process, you've got to adhere to the mantra:

“If it isn't verified - it's broken.”

Rhines endorsed a verification flow that includes simulation, formal verification, emulation, and testbenches - and then repeated that we've got to have coverage metrics to know how we're doing. Having laid out the plan, he then asked, “How do we get there?”

Again he answered his own question: “It's easy. Use coverage constraints built into PSL and SystemVerilog, simulation integrated with functional coverage to improve performance, and then develop new test strategies that require functional coverage, as well as random and constrained random testing - and coverage to determine what they've tested.”

Rhines said abstraction happens, so C synthesis tools are coming. ESL initiatives will produce tools that will eliminate RTL coding. And, if you can get design to start at the system level, you'll be able to make decisions based on an optimized partitioning of the problem - partitioning between the hardware and the software. Rhines also touched on platform-based design. Snapping together blocks of IP is intuitively pleasing he said, and commended the SPIRIT Consortium as a type of effort that was helping to move the industry towards that reality.

Rhines ended by declaring the roadmap going forward. In the near term, he said that the EDA tools vendors will support SystemVerilog and PSL. Farther out, designers will automatically determine the sequence of algorithms to apply based on the design, and based on the requisite testbench and coverage required. Farther out, simulation will run until complete coverage is achieved.

Rhines fielded one telling question from the floor after wrapping up his talk. How many additional designers can the world support, given predictions of higher levels of abstraction and more sophisticated tools and methodologies? He said with 50,000 ASIC designers and 500,000 FPGA designers - one could envision 5,000,000 system designers working with a palette of reconfigurable platforms and tile-based structures. That level of involvement, worldwide, Rhines said will be great news.

“Anytime you grow your user base, you grow the opportunities for creativity as well.”

Overall, the keynote offered a tidy, positive, and logical kick-off to DVCon 2005.

Chapter 2 - EDA Editor Gabe Moretti on Quality

Gabe moderated a panel - “Designing Quality In: The Better Design Paradigm” - and entertained discussion from Dataquest's Gary Smith, Jasper Design Automation's Harry Foster, Azul Systems' Kevin Normoyle, Intel's LimorFix, and Verisity Design's Andrew Piziali. The conversation was substantive.

Gabe started by suggesting that it was cheaper to avoid bugs than to find them and fix them. He called it crisis avoidance economics and asked what's so inhumane about asking people to build quality into their products. His panelists were ready to respond.

Andy Piziali said quality is a soft metric and instead, we should look at whether chips are produced on time. He said the timeliness goal requires an efficient design team structure, and that the structure requires separate design and verification groups. He also said that moving to higher levels of abstraction would enhance the overall design process, and commended Brian Bailey's concept of the Abstraction Bridge.

Andy said that EDA and IP vendors must work together to demonstrate IP quality and to annotate that quality within the verification plan. He asked why so much time is spent on functional verification, and said it's because it's hard. An automated verification environment would help but all proposals to that end, hinge on changing the culture that surrounds the verification process. He concluded that design for verification rules should be codified to prevent unverifiable, or difficult to verify logic design from being put forth in the first place.

Next, Kevin Normoyle stood up and spoke to the reality of design. He said that he'd yet to see any article in any magazine that describes how the design process really goes - that everything in print is misleading and glib, suggesting that design is an easy and straightforward process. Kevin said that post mortums on design projects are never published. He also said that if hardware designers start to think like the software guys, we'd all be going down the slippery slop demonstrated by Microsoft - the road that leads to buggy designs and an acceptance of all that represents.

Kevin said we need to get the tool vendors in sync, and in agreement, that quality is indeed important in designs and that if we could do that - the future would be big, indeed. That we could honestly look at 500,000,000 gate designs and celebrate the process of getting there. Then he pulled the rug out from under the vendors: “The tools don't matter. Individual people don't matter. It's the team that matters. Period.”

Kevin said you've got to have one carefully choreographed, well managed, well integrated, honest and organized team that includes everybody from the designer through to the verification guys and beyond. And, he said if you build a verification scaffolding into the design flow, you'll maximize on the skills set that everybody on the team brings to the effort. He was quite adamant about all of it and didn't seem to want to compromise on his vision. He said the end result would be intentional complexity in the products, not unintentional complexity in the product design.

Harry Foster said that 15 years ago, we had separate design and verification teams. But over the years, the verification testbenches have become even more complex than the designs. Despite that, few managers ever realize that you've got to schedule in more time for the verification phase of the project. So, clearly we need to explore the complexity of the specification much earlier in the flow. Harry's conclusion:

“We should optimize the process of design, not the outcome of the problem.”

We've got several ways to approach that end, Harry said. We need to look at the subsystems in the design versus verifying the integrated whole, and we need to look at the system (as in the software) versus the components of the system (as in the hardware). Harry said, unequivocally, the verification team must be part of the design team. And contrary to the popular contemporary urban legend, Harry said we're not doing design, we're doing implementation. And moving to ESL is not going to solve that problem.

If you're keeping score - at this point it's 1 to 2, Separate Teams (Andy) to Integrated Teams (Kevin & Harry).

So, now for the comments from Limor Fix. Limor presented an appealing spreadsheet with Abstraction level, Reuse, Incremental design, and Coverage down the left side of the matrix and How it's done today, How it'll be done tomorrow, Who's doing it today, and Who'll be doing it tomorrow across the top of the matrix.

The 16 resultant squares included: Row 1 with Design 1st, assertion later, Unified assertions (first) + design (later as needed), RTLers + Validators, Designers; Row 2 with Reuse as a starting point, Reuse without altering (accept NIH), Designers, and Designers; Row 3 with Validation begins late - when large enough blocks have been coded, Blocks of any size, Validators, and Designers; Row 4 with Design verification coverage + limited functional verification, More functional verification + unified functional verification/design verification coverage, Validators (mainly manual), and Designers (mainly automated).

If you're serious about following the reasoning here, please get out pen and paper. Draw the 4x4 matrix. Label the columns and rows per Limor's instructions, and fill in the 16 squares again per the instructions. Look at it for a long time and then compare the conclusions to Wally Rhines' keynote. More than settling the argument over Separate Teams versus Integrated Teams, the sensibilities in Limor's spreadsheet dovetail with the sensibilities in the Wally's keynote. And, if Intel and Mentor can be in that much agreement - there might be hope for the world.

That is - if we can first decide how to structure the development/verification teams.

Chapter 3 - Dataquest's Gary Smith on ESL

Gary's panel - “ESL Leadership: Can the U.S. Catch-up to Europe and Japan? - included Summit Design's Emil Girczyc, Forte Design's Brett Cline, HDLabs' Tony Chin, and Philips's Maurizio Vitale. Emil and Brett were speaking on behalf of the smaller North American ESL vendors, and Tony and Maurizio were chartered with presenting the view on the ground in Japan and Europe, respectively.

All told, it was a pretty depressing hour and a half, if you paid close attention to what people were saying.

Maurizio Vitale said that 5 years ago, Europe thought it was behind in the race to ESL, so they did something about it. Now they're in a leadership role in the technology, and as far as he's concerned - in a respectable race with Japan. Maurizio said the U.S. might as well give up now. It's too late, they've missed the boat, and in the end - the U.S. should just accept the fact that they've got just one fate awaiting them as a result of their delay:

To be the eventual home for global manufacturing.

Tony Chin said that in Japan, everybody's learning SystemC. Everybody. Nobody's holding back. It's a hot, hot, consumer-product driven market there and nothing can be done at the development speed required to compete in that market unless it starts, robustly, at the system level. He said that almost all semiconductor companies in Japan have products and plans in place that revolve around SystemC.

It's too late for the U.S., so give up now.

Brett Cline then had a turn. He said that RTL's clearly too difficult, so let's speed up the design process by going to SystemC and behavioral synthesis. He said that big chips and big systems require new thinking, and hinted that it's not too late for the U.S. to expand their horizons and confront the competition for global markets being presented by Europe and Japan.

Brett added that with 600,000 engineers graduating each year in China with degrees in engineering, that those of us in North America need to do something to address that threat. He said that something has got to be the move to ESL -

Now.

Finally, Emil Girczyc said the U.S. is not behind in ESL. Countering the viewpoint of his fellow panelists, he said the U.S. is working in ESL, it's just not doing it by way of SystemC. He said we needed to move past the narrow perception that the only definition of working in ESL, is to be working in SystemC.

Emil said you can't get from SystemC to gates, and that it's no faster to work in SystemC than it is to model in Verilog for higher levels of abstraction. And, besides - consider the fact that there's very little IP written in SystemC. So how is obsessing about SystemC going to help?

Emil said the over-arching problem in the U.S. is that the EDA vendors have a vested interest in the status quo. They're not pushing SystemC or ESL - instead, they're just protecting their existing products and the known flows that support those products. It's not clear that Emil's picture was any rosier, but he did establish a beachhead for the concept that:

ESL is not just about designing in SystemC.

It was indeed a pretty depressing hour and a half, if you sensed the implication that innovation, at least in the area of chip design, is moving off-shore (from a North American point of view) - possibly for good.

Gary Smith closed out the discussion, which included a lot of give and take from the panelists, by answering a multiple-choice question from the floor.

“Is the problem here that a) there's a bunch of obstinate old men in leadership roles in EDA that are inhibiting the move to ESL, or b) the U.S. doesn't actually need to be playing catch-up with Europe and Japan because ESL and/or SystemC aren't the only game in town.”

Gary answered matter-of-factly, “The answer is A - a bunch of obstinate old men.”

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Commerce & Industry

Accelerated Technology announced the Nucleus RTOS for Texas Instruments' OMAP1710 processor. Other components for the OMAP1710 processor include the Nucleus POSIX API, the Nucleus SHELL command line interface and the Nucleus file management software.

Actel Corp. announced its ProASIC3 and ProASIC3E families, which the company describes as its “third-generation of flash-based programmable logic solutions and the world's lowest-cost FPGA. With the ProASIC3/E families, the company says it is addressing the strong market demand for full-featured, cost-effective FPGAs for consumer, automotive and other price-sensitive application areas. In addition, the company announced a device programmer and starter kit, which supports its ProASIC3 and ProASIC3E FPGAs.

Actel also announced the availability of 90 IP cores to support its new ProASIC3 and ProASIC3E device families, which the company says demonstrates its commitment to the deployment of its new FPGAs.

Actel also announced that its Libero 6.1 Integrated Design Environment (IDE) provides complete support for the company's ProASIC3 and ProASIC3E devices.

Aldec, Inc. announced the release of Active-HDL 6.3, Altera Edition with direct support and automation for Altera's Quartus II design software version 4.2, Stratix II FPGAs and HardCopy II structured ASICs. The company says it has produced a Tcl-based script that automates the design flow interface between Active-HDL and the Quartus II software, so the engineer has a closed design environment and the ability to compile and simulate FPGA and HardCopy structured ASIC devices from a single design environment.

Altium Ltd. announced the release of Service Pack 1 for P-CAD 2004, which is Altium's PCB design system. The company describes the current release, SP1, as a “minor update initiated in response to feedback from customers via Altium's P-CAD Forum.”

Anadigm announced AnadigmDesigner2 version 2.5, which has a new Visual C++ Prototyping tool for dynamically reconfigurable FPAAs using the AnadigmVortex development system. The new user interface includes improvements to the CAM browser and handler, and other features, which allows users to create custom filters by manually moving pole and zero positions.

Apache Design Solutions announced the RedHawk-EV dynamic power analysis and verification tool. The company says that RedHawk-EV provides increased coverage for design weakness identification and exploration, automatic supply noise repair for power closure sign-off, and higher capacity for transient simulation of SoC designs. RedHawk-EV is designed to allow designers to verify potential power-related functional and timing behavior, and avoid excessive over-design.

ARM announced that Siemens has licensed the ARM Jazelle Technology Enabling Kit (JTEK) software for use in its next-generation “ARM Powered” feature phones.

Applied Wave Research announced that the company will provide its Microwave Office design suite to Eagle Test Systems to simulate performance of RF boards that are part of the Eagle's ATE products.

Arithmatica, Inc. announced an integrated, front-end flow for mutual customers of Arithmatica and Cadence Design Systems, which the companies say will improve quality of silicon for “math-critical” chips. The new flow was developed as part of the Cadence OpenChoice Program and includes Arithmatica's CellMath silicon IP and Cadence's Encounter RTL Compiler synthesis and Conformal formal verification tools.

Blue Pearl Software, Inc. the Indigo RTL Analysis tool designed for “rapid functional closure.” The company says it will be releasing its timing closure product later in 2005. Indigo identifies functional issues in RTL designs prior to synthesis, and resolves things like synchronization of data crossing clock domains and logic races. Indigo runs at the full chip level, without synthesizing to gates, and analyzes multiple clock domain designs to see that data crossing domain boundaries is synchronized. It recognizes double register, memory and custom synchronization schemes and points to data that re-converges from independent synchronizers.

Cadence Design Systems, Inc. announced that ATI Technologies Inc. is now using Cadence's new Palladium II acceleration/emulation system to “significantly accelerate” the functional verification of ATI's high-performance digital television (DTV) chip designs.

Cadence Design Systems also announced that Sanyo Electric Co., Ltd. had achieved an “important” production tapeout using Cadence's Encounter digital IC design platform, which helped “decrease power consumption of an important block of Sanyo's chip by 10 percent, while maintaining critical performance requirements.”

Cadence Design Systems and Rising Microelectronics Co., Ltd. announced that Rising has started sampling a SCDMA/GSM dual mode (1.8GHz SCDMA and 900MHz GSM) RF IC transceiver. The companies say the transceiver was designed using the Cadence Virtuoso and Encounter design platforms, and was implemented on IBM's 0.18um BiCMOS 7WL process and process design kit (PDK) developed and qualified by IBM for Virtuoso technologies.

Cadence also announced that its tools helped Fujitsu to achieve “first-pass silicon” on 66 recent, consecutive designs.

Cadence also announced that its Encounter digital IC design platform helped Silicon & Software Systems design multiple 90-nanometer designs over the past 18 months. The companies say the designs ranged in complexity and size from 1 million to 10 million gates, and exhibited performance metrics of 600+MHz.

Celoxica announced its Agility Compiler for SystemC, which the company says includes system design capabilities for synthesis of SystemC models to hardware. “It produces IEEE-compliant RTL descriptions as input to various, currently available ASIC/SoC synthesis flows, and then generates gate-level EDIF netlists for what the company describes as “high density” PLDs … The direct path from SystemC to hardware closes a critical gap in the ESL design flow for successful SoC design from system-level models. Agility Compiler synthesizes a complete hardware system with no artificial limitations on design hierarchy, structure, timing or interfaces.”

Celoxica also announced that within the Synopsys in-Sync program, it formalized the interoperability between Celoxica's Agility Compiler and DK Design Suite and Synopsys' Design Compiler.

Celoxica announced, as well, an agreement with Toshiba Corp. to provide its DK Design for application design and development using Toshiba's Media Embedded Processor (MeP) digital media SoC. The multi-year agreement covers C-based design entry, simulation, co-simulation and synthesis, as well as development hardware, through the availability of a MeP RapidPlatform developers' kit.

CoWare Inc. announced a new option for its SPW 5-XP DSP application solution for Windows that the company says “enables early verification of complex embedded DSP designs. “Using the option, designers who are developing DSP applications can reuse their SPW 5-XP reference models for verification of embedded software for TI TMS320C6000 and C5000 DSP platforms developed using TI's Code Composer Studio (CCStudio) IDE.”

CoWare also announced its SPW DSP application design tool has been integrated with the new Cadence Virtuoso custom design platform for RF designers.

CriticalBlue says it has validated its Cascade tool with respect to Synopsys RTL implementation flow. The work was completed in conjunction with “a leading semiconductor company who defined the embedded software benchmark example and its target gate count and performance constraints. No modifications were made to the original embedded software.”

EMA Design Automation announced that RadiSys Corp. has adopted the Cadence Allegro system interconnect design platform 600 series at all of its design centers.

IBM and Chartered Semiconductor Manufacturing announced they are expanding their joint development efforts to 45-nanometer bulk CMOS process technology. The companies say that when development is complete, they'll have a common process platform which span three generations of process technology. This 45-nanometer joint effort is a continuation of an agreement signed in November 2002 to jointly develop and align on 90-nanometer and 65-nanometer on 300mm silicon wafers.

Chartered Semiconductor Manufacturing also says it has begun prototyping customer products at its 300mm facility at multiple advanced technology nodes. The company says pilot production activities are currently running on Chartered's 0.13-micron process, the 90-nanometer cross-foundry platform jointly developed by Chartered and IBM, and the 90-nanonmeter SOI process.

IBM, Sony Corp., Sony Computer Entertainment Inc. and Toshiba Corp. (Toshiba) announced a multi-core architectural design, which includes floating point performance with observed clock speeds at 4+ GHz. The new microprocessor is code-named Cell. The prototype chip is 221 mm2, integrates 234 million transistors, and is fabricated with 90-nanometer SOI technology.

IMEC announced it has produced a 5GHz and 15GHz low-power voltage controlled oscillator (VCO) by post-processing high-quality inductors on top of 90-nanometer RF CMOS devices using a thin-film wafer-level packaging (WLP) technology. IMEC's thin-film technology uses alternating layers of BCB (benzo-cyclobutene dielectric) and thick electroplated Cu layers deposited on top of the passivation. The post-processing is compatible with both Cu and Al back-end.

LogicVision, Inc. announced that Open-Silicon is using LogicVision's embedded memory-test and repair-analysis technology as part of its standard tool flow in ASIC designs. Additionally, the companies announced that LogicVision will collaborate with Open-Silicon to add automatic memory repair to Open-Silicon's tool flow.

M2000 announced 90-nanometer FlexEOS embedded FPGA macros, The company says the new macros have 1,000+ reprogrammable look-up tables (LUT's) per mm2 and performance capable of 2.7 GHz. The macros have 98,304 LUTs, are SRAM based, and can be dynamically reconfigured to change the functionality of ASIC and SoC circuits after silicon processing and packaging.

Magma Design Automation Inc. announced that Texas Instruments Inc., and Sun Microsystems will use design software from Magma as part of a collaboration on a next-generation computer system chip set.

Magma Design Automation also announced that Enuclia Semiconductor has selected Magma's front-end tools, Blast Create and Blast Plan Pro, to prototype designs in FPGAs and structured ASICs, and then move them into to Enuclia's ASIC/COT (customer-owned tooling) design flow.

Mentor Graphics Corp. announced that LSI Logic has licensed Mentor's 10/100/1000 Ethernet Media Access Controller (MAC) IP core. The companies say the core has been proven in silicon and has been pre-verified and tested for integration into SoC designs. Mentor Graphics acquired their line of Ethernet IP from Alcatel in July 2003.

Mentor Graphics also announced that its suite of synthesis products supports Altera Corp.'s new HardCopy II structured ASIC family. The companies say that Precision RTL Synthesis and LeonardoSpectrum tools are now available in relationship to HardCopy II devices.

Mentor Graphics similarly announced that its suite of synthesis products has added support for Actel Corp.'s new ProASIC3 and ProASIC3E FPGAs. Users of the Precision RTL Synthesis tool from Mentor Graphics can request software updates for designing with the new devices. Initial support for ProASIC3/E in the Precision Synthesis tool suite has been available to some customers since October 2004.

Nascentric, Inc. announced its Nascim fast-SPICE simulation technology, with current-based transistor models to reflect actual current flow and current density in CMOS circuitry. The company says it's the first in a series of simulation and analysis products being developed by Nascentric. The suite of products intends to focus on transient physical and electrical effects that negatively impact timing, power and signal integrity in nanometer designs, effects such as IR drop, leakage currents, electromigration, and cross-coupling.

ProDesign announced the availability of the CHIPit Gold Edition Pro high speed ASIC design verification platform for multimedia ASIC and SoC design. Uses range from the initial phases of design algorithm creation, through the basic IP development and debugging, to the validation of complex SoC designs and early “quasi prototyping” for firmware and software development.

Pulsic Ltd. announced that Elixent has licensed its Lyric Physical Design Framework. Elixent says it will use Lyric for automatic and interactive routing of its advanced cell designs for its D-Fabrix RAP cores. The D-Fabrix array is automatically compiled from a library of cells designed at the transistor level to optmize possible speed and power performance in the smallest possible area.

QuickLogic Corp. announced a partnership with Renesas Technology Corp. to develop an 802.11b/g IP phone reference platform, which the companies say will target the Wi-Fi market. The reference platform will be designed based on Renesas' SH7720 32-bit RISC processor and QuickLogic's low-power programmable PCI bridge.

QuickLogic also announced the company's Eclipse II family of low power FPGAs are now qualified for operation at the extended industrial temperature range, -40 degrees to +100 degrees Celsius device junction temperature.

ReShape, Inc. announced it has shipped its enhanced PD Builder, which the company says supports SoC Encounter Global Physical Synthesis (GPS) from Cadence Design Systems. ReShape says the company worked in collaboration with various Cadence software users so the PD Builder Open Flow will include best practices in its programmable reference design flow. Designers using PD Builder, can work in conjunction with physical design tools from Cadence, Mentor Graphics, and/or Synopsys.

Sandwork Design, Inc. announced that its analog and mixed-signal circuit debugging tools have been incorporated into the design flow of ON Semiconductor Inc.'s design centers.

Silicon Dimensions, Inc. announced support for AMD's 64-bit Linux platforms in its Chip2Nite suite, so now Chip2Nite users can have access to “64-bit computing with applications involving large data sets and computationally intensive tasks.” The company says that Chip2Nite currently supports Red Hat 7.2, 7.3, and 8.0 and Red Hat Enterprise Edition 2.1 and 3.0.

Sonics, Inc. announced that Toshiba Corp. will design the SonicsMX and Sonics3220 SMART Interconnects into a new family of wireless handheld products. The companies say that Toshiba currently uses Sonics' Silicon Backplane SMART Interconnect and Sonics' MemMax Memory Scheduler in its processor-based digital consumer product.

Synopsys, Inc. announced that Aarohi Communications, Inc. is now using Synopsys' VCS RTL verification tool for the functional verification of Aarohi's “next-generation” FabricStream intelligent storage product.

Synopsys also announced release of its DesignWare Hi-Speed Universal Serial Bus (USB) On-The-Go (OTG) controller core, which the company describes as “the lowest gate count IP available on the market.” The core is a modular version of earlier DesignWare Hi-Speed USB and OTG cores.

Synopsys also announced that NetSilicon, Inc. has had “first-silicon success” using Synopsys' Vera testbench automation tool and the VCS RTL verification tool as part of NetSilicon's NS9750 NET+ARM processor verification environment.

Synplicity announced enhancements to its FPGA synthesis software to improve productivity and integration with formal verification, place & route, and debugging products. Enhancements include: integrated formal verification flow support for Cadence's Conformal and Prover Technology's eCheck equivalence checker software; tighter integration with P&R tools from Actel, Altera and Xilinx, and Synplicity's Identify source code debugging product for FPGAs is now integrated into the Synplify Pro product. Also, this version of Synplify Pro software includes support for Actel's ProASIC3 FPGAs and Altera's HardCopy II structured ASICs.

Synplicity and Prover Technology Inc. announced an integrated verification flow for Synplicity's Synplify Pro FPGA synthesis tool. The companies say the flow combines the Prover eCheck equivalence checker and the Synplify Pro 8.0 software, and that users of the Synplify Pro can use Prover's formal verification product in their verification flow. The combined flow automates equivalence checking of Altera and Xilinx FPGA designs.

Synplicity also announced enhancements to its Synplify DSP software, which include new DSP synthesis optimizations for performance and area, additional blockset functionality, including support for saturation/rounding, and a customizable DSP block library so that designers can add custom DSP IP to their library. The company says Synplify DSP gives users of products from The MathWorks with a DSP synthesis path from Simulink to hardware.

TDA Systems Inc. announced a new S-parameter tool, which allows differential S-parameter measurements based on Time Domain Reflection and Transmission (TDR/T) data. The product is available on a stand-alone basis or bundled with TDA's IConnect software, and is designed for digital design, electrical-compliance testing and signal integrity engineers.

TDA also announced version 3.5 of its IConnect and MeasureXtractor TDR and VNA software, which the company says includes the new S-parameter functionality.

Taiwan Semiconductor Manufacturing Company (TSMC) announced a suite of internally developed libraries that support its Nexsys 90-nanometer technology. The libraries include links to TSMC technology and support for design methodologies represented by major EDA, package and IP vendors. The company says the libraries are already in volume production, and are TSMC Reference Flow 5.0 proven and DFM compliant.

Tensilica, Inc. announced the V6 suite of automation tools, which the company says speed ups block design in SoCs design, and makes it easier to design SoCs with configurable processors. The company says a designer with an existing algorithm coded in C or C++ can develop a customized Xtensa LX processor in a day, as opposed to a RTL design cycle that usually requires six to nine months.

Tharas Systems, Inc. announced support for Verilog 4-state logic simulation in Hammer 100. The company says that Hammer 100 can detect and propagate 4-valued logic similar to a Verilog software simulator.

TransEDA announced Expression Coverability Analysis for automatic analysis of conditional expressions for designs written in Verilog, VHDL and mixed languages. The tool uses an embedded formal engine to identify uncoverable expression terms and coverable terms that have not been exercised. Uncoverable expression terms are reported and eliminated from the overall coverage calculation.

TTP Communications plc. and ARM announced collaboration to design and develop 3G IP platforms, which use ARM processors and TTPCom Cellular Baseband Engine (CBEmacro) technology. TTPCom says it will distribute the combined technologies to semiconductor manufacturers. ARM says it will license the processor core to its silicon partners and TTPCom will license the CBEmacro technology.

Virtual Silicon Technology, Inc. announced an integrated digital frequency synthesizer (DFS), the Delta-Sigma Fractional-N Phase Locked Loop product for synthesizing output frequencies to suit an individual project. No special processing is required for mixed-signal circuits.

Zuken says its CADSTAR 3D desktop design tool has been upgraded and now has Windows XP functions, with drag and drop loading of designs, floating toolbars, and modeless and dockable dialogues for Design Browser.

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Economics & Finance

AMD, Analog Devices, Freescale, and IBM announced that they are the first companies to publish certified scores for processors tested against the new DENbench suite, EEMBC’s new Digital Entertainment benchmarks. The first processors to be evaluated under the new benchmarks are the AMD Geode NX1500, the Analog Devices ADSP-BF533, the Freescale MPC7447A, and the IBM 750GX.

EEMBC says the DENbench suite has 65+ benchmark tests that allow developers of set-top boxes, PDAs, mobile phones, and in-car entertainment systems to evaluate the performance

Applied Wave Research, Inc. (AWR) and Auriga Measurement Systems, LLC announced an OEM agreement aimed at providing new modeling and extraction solutions. Under the terms of the agreement, Auriga will embed AWR’s Microwave Office design software into the company’s upcoming measurement and model extraction test system.

Giga Scale Integration Corp. announced that it has launched a new website, ChipEstimate.com, that provides free access to the company's InCyte chip estimation tool. After registering, visitors can download a free copy for immediate use. In addition, upgrade subscriptions providing access to additional IP vendor and foundry data are available at the ChipEstimate.com website.

IMEC announced that Samsung Electronics Co. LTD. has become the first strategic partner within IMEC's M4 (Multi-Mode Multi-Media) research program, which IMEC says focuses on the mobile terminal for the future ubiquitous network era. Under this agreement, Samsung and IMEC will develop technologies for future portable communication products. IMEC also has relationships with Freescale, Infineon and Xilinx within the M4 technology programs.

MatrixOne announced the MatrixOne Materials Compliance Central business process application, which the company says is designed to help companies to comply with new environmental regulations in affect for the product development process.

SilTerra announced it will provide Virage Logic Corp.’s IPrima Foundation Platform to Its 130-nanometer process customers IPrima Foundation has memory, logic and I/Os optimized to SilTerra’s 130-nanometer process. Under the terms of the agreement, SilTerra customers can download design kits with the IPrima Foundation IP Platform from the "Members" section of Virage Logic’s website.

Synopsys, Inc. announced a service to allow users of Verisity's Specman Elite testbench product to migrate to Synopsys' VCS RTL verification tool. The company says the Native Testbench (NTB) migration service converts Specman Elite verification environments to VCS environments and includes tool, language and methodology training.

Virage Logic announced it is extending its distribution model from a customer-paid licensing and royalty-bearing model to include a new "Foundry Pays" option in which foundries can license Virage Logic IP directly and provide it to their customers.

Actel Corp. announced net revenues of $40.3 million for the fourth quarter of 2004, down 1 percent from the fourth quarter of 2003 and up 2 percent from the third quarter of 2004. For the full fiscal year, net revenues were $165.5 million, up 10 percent from fiscal 2003. Pro-forma net income, which excludes acquisition-related amortization and other non-recurring items, was $0.6 million for the fourth quarter of 2004 compared with $3.0 million for the fourth quarter of 2003 and $1.2 million for the third quarter of 2004.

Ansoft Corp. announced financial results for its third quarter of fiscal 2005 ended January 31, 2005. Net income for the third quarter was $3.0 million, or $0.23 per diluted share, representing a 115% increase when compared to net income of $1.4 million, or $0.11 per diluted share in the previous fiscal year's third quarter. On a GAAP basis, net income for the third quarter was $2.8 million, or $0.21 per diluted share, compared to GAAP net income of $941,000, or $0.07 per diluted share in the previous fiscal year's third quarter. Revenue for the third quarter totaled $17.4 million, an increase of 24% compared to $14 million reported in the previous fiscal year's third quarter.

Apache Design Solutions announced that the company’s sales in creased 3X in 2004 compared to the previous year, Q4 2004 is the company’s eighth consecutive record quarter. In addition, the company is relocating its headquarters to a new facility in Mountain View, CA.

Cadence Design Systems reported fourth quarter revenues were $343 million, compared to $311 million for the same period last year. Full year revenues totaled $1.20 billion, an increase of 7 percent over 2003 total revenues of $1.12 billion. On a GAAP basis, Cadence recognized net income of $60 million, or $0.20 per share, in the fourth quarter of 2004, compared to net income of $15 million, or $0.05 per share, in the same period last year. On a full year basis, Cadence net income for 2004 was $74 million, or $0.25 per share, compared to a net loss of $18 million and a diluted net loss per share of ($0.07) for the year 2003.

Mentor Graphics announced revenues of $214.9 million for the fourth quarter of 2004. Diluted earnings per share for the quarter on a pro forma basis were $.39, and on a GAAP basis were $.20. Book-to-bill reached its highest level since 1996 and backlog reached a level not seen since year 2000. Bookings rose over 35% for the quarter and 20% for the year.

Synopsys, Inc. reported results for the first quarter ended January 31, 2005. For the quarter, Synopsys reported revenue of $241.3 million, a 15% decrease compared to revenue of $285.3 million for the first quarter of fiscal 2004, but in line with the Company's targets. The decrease was expected, and is due primarily to a lower percentage of up-front license revenue, driven by the shift in the fourth quarter of fiscal 2004 in Synopsys' license mix away from software licenses on which revenue is recognized when the product is shipped toward licenses on which revenue is recognized over the term of the license.

Synplicity announced financial results for the fiscal quarter and year ended December 31, 2004. Revenue for the quarter ended December 31, 2004 was $15.1 million, a 14 percent increase from revenue of $13.2 million for the quarter ended December 31, 2003 and a 7 percent sequential increase from revenue of $14.1 million for the quarter ended September 30, 2004.

Taiwan Semiconductor Manufacturing Company (TSMC) announced revenue and net income for the quarter ended December 31, 2004. Fourth quarter revenue reached NT$63.87 billion, while net income and fully diluted earnings per share came to NT$22.18 billion and NT$0.96 per share (US$0.15 per ADS unit), respectively. For the full year of 2004, TSMC's revenue set a new record, NT$255.99 billion, 26.8% higher than in year 2003. Net income for the entire year grew 95.3% to NT$92.32 billion, also a new record. In US dollar terms, revenue for 2004 was US$7.65 billion, an increase of 30.3% while net income grew to US$2.76 billion, an increase of 100%.

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Politics & Government

Cadence Design Systems, Inc. announced that it has donated SystemVerilog data type and IP encryption technology to the IEEE P1800 Working Group. The company says the Working Group will incorporate the Cadence technology in the first release of the SystemVerilog standard, due later this year. Per the Press Release: “These donations enhance the data types that are currently available in SystemVerilog and enable existing encryption technology to be used to encrypt SystemVerilog code, resulting in enhanced language efficiency and usability … The Cadence donation provides enhanced data types that raise the level of abstraction in SystemVerilog, enhancing designer productivity and language usability.”

The Press Release adds this notation: “As the initial developer of the Verilog language, Cadence now provides design and verification platform support for SystemVerilog, VHDL, Verilog, PSL/OVL, SystemC, Verilog-AMS and VHDL-AMS. Customers can efficiently run SystemC to verify system function, SystemVerilog and Verilog to verify gate implementation and timing, VHDL for compatibility, PSL for complete assertion-based verification, and AMS for mixed-signal designs. All of these languages now run inside a single simulation interface, allowing customers to use any combination for design and verification to improve language interoperability.”

Victor Berman, Director of Language Standards at Cadence and DVCon 2005 Conference Chair, is quoted in the Press Release: “In response to our customers' needs, Cadence is driving support for a single Verilog standard that will give users the benefits of open interoperability, exemplified by our recent donations to the IEEE. Our design and verification platforms, especially the Incisive functional verification platform, are built around open standards that offer customers the flexibility and language choice needed to optimize their verification methodology.”

Fab Owners Association - Nine semiconductor companies announced the formation of a not-for-profit semiconductor manufacturing association - the Fab Owners Association (FOA) - with combined annual revenues of $7+ billion and production levels of approximately 500,000 8-inch-equivalent silicon wafers manufactured per month. The Fab Owners Association member companies include AMI Semiconductor, Cypress Semiconductor, Delphi Electronics, Fairchild Semiconductor, Intersil, LSI Logic, Micrel Semiconductor, ON Semiconductor, and ZME AG.

Mentor Graphics Corp. announced its membership in the ProSTEP iViP Association ECAD Implementor Forum (ECAD-IF), which specializes in the “harmonization and specification of ISO STEP data-models and data exchange interfaces (Standard for the Exchange of Product Model Data). ECAD-IF has previously made significant contributions to the detailed elaboration of the ISO STEP AP212 electrical system design & harness standard; more recently it has also been responsible for the development of the KBL automotive electrical harness standard, a specialized derivative of AP212.

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Citizenry

Aldec, Inc. announced that Quest Innovations B.V. is now a Preferred IP Partner in its IP Core Partner Program.

Anadigm announced the appointment of Connie Grennan as its CFO, reporting to President and CEO Bill McLean. The company says Grennan succeeds founding CFO Fred Worth, who announced his retirement last month. Grennan has 25+ years of financial management experience. Previously, she was at Andigilog, Inc., Micro-Photonix Integration Corporation, and CalComp.

Applied Wave Research, Inc. (AWR) and Auriga Measurement Systems, LLC announced an OEM agreement, whereby Auriga will embed AWR’s Microwave Office design software into the company’s soon-to-be-released measurement and model extraction test system.

Ansoft Corp. announced that its ePhysics EM-coupled thermal and stress-analysis tool was selected as one of EDN Magazine's "Hot 100 Products of 2004."

Aprio Technologies Inc. has named Mike Gianfagna to be President and CEO of the company. Clive Wu, previously CEO at Aprio, will continue as a member of the board of directors, and will now become the company’s CTO. Gianfagna has 25+ years in the EDA and semiconductor industries. Most recently, Gianfagna was Vice President of Marketing at eSilicon. Prior to that, Gianfagna was Vice President and General Manager of the System Level Design Group at Cadence. Gianfagna was also at Zycad Corp., at RCA Solid State, General Electric Solid State, and Harris Semiconductor (now Intersil). Gianfagna has a BSEE from New York University and an MSEE from Rutgers University.

Cadence Design Systems, Inc. and the Department of Veterans Affairs Hospital in Palo Alto announced The Fisher House Project at the VA Hospital to be the 2005 recipient of the Cadence Stars and Strikes Fundraiser. The Fisher House is the initiative of the Fisher Foundation, which helps build housing where families of veterans and active duty soldiers can stay, while servicemen and women receive treatment at a Veterans Hospital. There are other Fisher Houses around the United States, but there is no such facility currently at the VA campus in Palo Alto.

Cadence also announced that its Cadence Allegro Package Designer was selected as one of EDN Magazine's "Hot 100 Products of 2004."

The Design Automation Conference (DAC) announced the Exhibitor Liaison Committee (ELC) for the DAC 2005 in Anaheim, CA. The EDA Industry Chair is Limor Fix of Intel. Other members include: Jana Burke, Mentor Graphics; Donna Castillo, Cadence Design Systems; Ric Chope, Verisity Design; Larry Eberle, Synopsys; Tom Minot; Steve Pollock, Beach Solutions; Gabe Moretti, EDA Editor; Mindy Powers, CoWare; Dave Reed, Blaze DFM, Michelle Clancy, Cayenne Communications, DAC Executive Committee Chair Bill Joyner, IBM Corp./SRC and other members of the DAC Executive Committee, including Nanette Collins, Nanette V. Collins Marketing & Public Relations and Lee Wood, MP Associates."

DesignCon DesignVision Award Winners   -- The Award Winners in this first annual competition were announced on February 1st in Santa Clara. Here are the winners in each category. ASIC & IC Design Tools * Cadence Design Systems for First Encounter Global Physical Synthesis * Synplicity for the Amplify Family of Structured/Platform ASIC Synthesis products – Design Verification Tools * Novas for the Verdi Behavior-based Debugging System * Synopsys for the Magellan Hybrid Formal Verification Tool – FPGA & PLD Design Tools * Xilinx for Platform Studio – Industry Service * Accellera for PSL Version 1.1 * VSIA for the VSIA Quality IP Metric – Interconnect Technologies & Components * FCI for the AirMax VS Connector System – PCB Design Tools * Samtec for Final Inch – Semiconductors & ICs * Analog Devices for the VisualAudio Graphical Audio System Design & Development Environment * National Semiconductor for the Point-to-Point Differential Signaling Architecture & Chipset * NEC Electronics for the 90-nm ISSP Device – Semiconductors & ICs/IP Category * Virtual Silicon Technology for Mobilize Power Management IP – Structured/Platform ASIC Design Tools * eASIC Corp. for Structured eASIC * AMI Semiconductor for XPressArray-II – System-Level Design Tools * Amherst System Associates for the M1 Timing & Jitter Analysis Timing Software – Test & Measurement Equipment * Agilent for the Infinium DSO80000 Series Oscilloscopes & Inifimax II Series * Tektronix for the TDS5000B with Myscope
* Wavecrest for the SIA 3600 D Signal Integrity Analysis Solution.

The EDAA Lifetime Achievement Award 2005 has been awarded to Dr. Jochen Jess of the Technical University of Eindhoven, The Netherlands. The award is the premier acknowledgement given by the European Design Automation Association (EDAA), the principle sponsor of DATE. The award honors individuals who have made outstanding contributions to the state of the art in electronic design, electronic design automation and test of electronic systems over the course of their career.

EDN Magazine announced that Mike Santarini has been named a Senior Editor at the publication. Previously, Santarini was an editor at EE Times. Prior to EE Times, he was an editor at ISD Magazine. Santarini has a BA from Santa Clara University.

Emulation and Verification Engineering (EVE) announced that Venktesh (Venk) Shukla has been named to the Board of Directors for the company. The board also includes EVE CEO and President Luc Burgun, Philippe Granger, Robert Eckelmann, and Pierre Martini. Shukla was Senior Vice President of Marketing at Magma Design Automation, and before joining Magma, was CEO of Everypath, Vice President of Marketing at Ambit Design Systems, acquired by Cadence Design Systems, and served in an executive role at Cadence. Shukla also worked at Teradyne.

Hewlett-Packard Co. announced that Carly Fiorina has stepped down as Chairman and CEO. Robert P. Wayman, HP's CFO, has been named CEO on an interim basis and appointed to the board of directors. He will retain his CFO responsibilities. The company does not expect to make any additional structural changes or executive leadership changes at this time. Patricia C. Dunn, an HP director since 1998, has been named non-executive chairman of the board, also effective immediately. The board says it will begin a search for a new CEO immediately.

MatrixOne, Inc. announced that Gary Hall, the Company's Vice President and Corporate Controller, has been promoted to the position of Senior Vice President and CFO. Hall joined MatrixOne in 1999 and is responsible for all aspects of global accounting, financial reporting, and regulatory compliance. Previously, he worked at Deloitte & Touche.

Nascentric, Inc. announced the appointment of Scott Yore as CFO, reporting to President and CEO Vess Johnson. Previously, he was at Silicon Metrics, and was involved in the acquisition of the company by Magma Design Automation. Prior to Silicon Metrics, he was at CCI/Triad, and Ernst & Young.

Sequence Design announced the appointment of Mark Goldman to the newly created position of Vice President of Field Operations, responsible for the management of sales and field operations. Goldman has 30+ years' experience in high-tech sales. Previously, he was at TriCN as Vice President of Sales. Before that, he was at Cadence and CadMOS, as well as Duet Technology, Avanti, Silicon Architects, and Mentor Graphics.

Stelar Tools, Inc. announced that HDL Explorer has been nominated for an EE Times' Ultimate Product Award. The company says that its HDL Explorer design tool has been nominated in the Logic/Programmable Logic category

Synfora, Inc. announced it has been selected as one of five finalists in the "Emerging Company of the Year" category of the EE Times ACE Awards. The award will be given to a start-up chip or system company that has been in business less than two years, has demonstrated excellence in business and/or technology development processes, and has the potential to become a technical or market leader in the global electronics industry.

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Festivals & Fairs

** eScape to SystemVerilog Seminars – Mentor Graphics and Synopsys are presenting a series of technical seminars intended to show users of Verisity's e language now to transition to a standards-based verification methodology built on SystemVerilog … [The] technical seminars will provide practical demonstrations on how users of Verisity's e language can apply SystemVerilog to speed verification and find more bugs, faster."

Manoj Gandhi, Senior Vice President and General Manager in the Verification Group at Synopsys, is quoted: "Synopsys pioneered the SystemVerilog standardization effort with multiple technology donations and continues to lead with broad support in our design and verification tools. SystemVerilog's unified design and verification capabilities help enable customers to achieve significant productivity gains as compared to point-tool solutions."

Robert Hum, Vice President and General Manager in the Design Verification and Test Division at Mentor Graphics, is also quoted: "Many companies and organizations that have led the evolution in verification by using proprietary languages such as e are transitioning to a standards-based verification methodology built on SystemVerilog. Mentor Graphics has always taken the lead on supporting standards and continues to do so with its Scalable Verification(TM) solution based on SystemVerilog."

The seminars are booked into San Jose on March 2nd, into Dallas on March 3rd, and into Boston on March 4th. There will other dates/venues yet to be specified, elsewhere in North America, Europe, Israel, Japan, Korea, India and Taiwan.
(http://www.systemverilognow.com)

** DAC 2005 Nominations – Nominations are being accepted up until March 4th for the Marie R. Pistilli Women in EDA Achievement Award. The DAC Committee says this yearly tribute recognizes individuals who have visibly helped advance women in the EDA industry.
(http://www.dac.com/42nd/PDFs/mrpform.pdf.)

** ESC 2005 – The organizers of the Embedded Systems Conference in San Francisco say this is the 17th annual event, and is taking place March 6th to 10th. The conference is described as "the largest systems design event in North America. ESC San Francisco is one of the few places that bring players in the electronics systems design industry together with the newest technologies."
(http://www.esconline.com/sf/)

** EDN Magazine's 15th Annual Innovation Awards – The Innovation Awards ceremony and dinner will be held March 7th at the Mark Hopkins Hotel in San Francisco. Organizers say that Geoffrey Orsak, Dean of Southern Methodist University School of Engineering, and Walter Mossberg, The Wall Street Journal's personal-technology columnist will be the featured speakers.
(www.EDN.com/innovation)

** EE Times ACE Awards Gala will be taking place on Thursday, March 9th, at the Moscone Center in San Francisco. The evening will include dinner, the awards presentation, and after-dinner entertainment by comedian Richard Jeni. Tickets are available for $200 per person, and include dinner, the awards, Jeni, and a pass to the industry "after party" with music, cocktails and dancing.
( http://www.eet.com/ace/gala.jhtml)

** DATE 2005 – Organizers describe the conference – this year taking place in Munich on March 7th to 11th as "Europe's premier conference and exhibition for Electronic Design, Automation and Test offers delegates and visitors the broadest-ever range of information to system designers. The conference addresses research and development activities in the field of design technology and is more and more moving to a system design event focusing on common platform challenges for embedded systems." The conference will include 400+ presentations, 234 technical conference presentations in seven parallel conference tracks and others in the Executive Track, pre-conference tutorials on the first day, and workshop sessions on the last day of the conference, special days devoted to automotive system design, a PCB symposium, and an enhanced Designers Forum. In addition, organizers say a new feature this year is a 3-day track of submitted papers on Embedded Software.
(http://www.date-conference.com)

** PCB West 2005 – The conference is taking place March 7th to 11th at the Santa Clara Convention Center. Organizers say, "The PCB Design Conferences are the first and only PCB design-oriented conferences developed specifically to meet the needs of PCB engineering, design and manufacture professionals. Our conferences may have been imitated, but they have never been equaled or surpassed. Since 1992, PCB Design Conference West has been expanding the limits of PCB design by providing attendees with quality technical education taught by industry experts, a top-notch product and service exhibition and a wide range of networking opportunities."
(http://www.pcbwest.com)

** Synopsys Interoperability Award – Synopsys announced that nominations for the Tenzing Norgay Interoperability Award are due by March 11th. The Tenzing Norgay Interoperability Achievement Award will be presented to the EDA company whose work to make their products interoperable was critical to designers' success. The Award is presented to the company that: * Surpasses common levels of interoperability, * Contributes to overall industry advancement, * Provides a new view of the future, * Ensures customer success. Previous winners include Novas Software (2004), Silicon Metrics (2003), Mentor Graphics (2002) and CoWare (2001).
(http://www.synopsys.com/tapin/tnorgay)

** SNUG – Synopsys' 15th annual Users' Group meeting is happening in Santa Clara from March 14th to 16th. The keynote address will be given on February 14th by company CEO and President Aart de Geus. The event will include numerous tutorials and a vendor fair.
(http://www.snug-universal.org/northamerica/na_sanjose.htm)

** 2005 EDA Tech Forum - Mentor Graphics, as well as Altera, Artisan/ARM, Chartered Semiconductor, The Mathworks, VSIA, and Accellera will be sponsoring this series of conferences in the coming months. The next one is in Long Beach, CA on March 16th and will include keynotes from Gartner/Dataquest's Martin Reynolds and Irving Information Group's Larry Irving. All told, 18 conferences are scheduled for various venues worldwide in 2005 including: Dallas, Texas; Phoenix, Boston, San Jose, Ottawa, Dresden, Reading, Paris, Penang, Bangalore, Delhi, Beijing, Shanghai, Hsinchu, Seoul, Tokyo, and Kyoto.
(http://www.mentor.com/)

** ISoC – The 3rd International System-on-Chip Conference and Exhibition is putting out a call for papers. Deadline for submissions is March 20th. The conference will be held November 1st and 2nd in Newport Beach, CA. Organizers say the theme for the conference will be "SoC in Wireless Applications."
(http://www.savantcompany.com/SoC3-Fall2005/Call.htm)

** ISQED 2005 – This will be the 6th International Symposium on Quality Electronic Design, and will be happening March 21st to 23rd in San Jose. The topic of this year's meeting will be "Design for Quality in the Era of Uncertainty." Organizers say the conference is held in technical sponsorship of IEEE EDS, IEEE CPMT, and in cooperation with IEEE CASS, ACM/sigDA. The ISQED'05 conference spans three days, Monday through Wednesday, in three parallel tracks, hosting near 100 technical presentations, six keynote speakers, two panel discussions, workshops /tutorials and other informal meetings.
(http://www.isqed.org)

** HOT Chips 17 – The Organizing Committees of the HOT Chips conference is inviting papers for consideration for the upcoming conference on August 14th to 16th, being held once again at Stanford University. The deadline for paper submissions is March 25th.
(http://www.hotchips.org)

** Mentor Graphics User2User Conference – This will be the 21st annual Mentor Graphics Users' Conference, and it's happening April 27th to 29th in Santa Clara, CA.

The company says, "The event will feature two keynote speakers. Aviation pioneer Burt Rutan, chief designer of SpaceShipOne, the world's first private manned spacecraft, will present the first keynote. SpaceShipOne earned the $10 million Ansari X-Prize for its two successful launches into space within a 14-day time frame. The second keynote speaker will be Michael Sander of NASA's JPL. Sander leads the JPL efforts in support of the new NASA Exploration Initiative. In addition, Adam Savage and Jamie Hyneman of the Discovery Channel's MythBusters will also make an appearance."
(http://www.mentor.com/user2user)

** DAC 2005 – Please put this conference on your calendar right now: June 13th to the 17th at Anaheim Convention Center. "DAC is the annual event where the electronics design community meets for a week-long forum of information exchange on management practices, products, methodologies and processes. Attended by more than 12,000 developers, designers, researchers, managers and engineers from leading electronics companies and universities worldwide, it offers a robust technical program covering the industry’s hottest trends. Its vibrant exhibit floor includes more than 200 companies, many of whom are startups just introducing their first products. The conference is sponsored by ACM’s Special Interest Group on Design Automation, the Circuits and Systems Society and Computer Aided Network Design Technical Committee of the IEEE, and EDAC."
(http://www.dac.com)

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Peggy Aycinena authors EDA Nation, and owns and operates EDA Confidential at www.aycinena.com. She can be reached at peggy.aycinena@extensionmedia.com.

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