History & Geography
— "Princeton's Wayne Wolf"
Commerce & Industry
Economics & Finance
Politics & Government
Festivals & Fairs
Subscribe FREE to Chip Design!
First off, I would like to welcome John Blyler as the new Editor in Chief of Chip Design Magazine. John is taking over for Tets Maniwa, who is leaving the magazine to pursue other interests.
The EDA industry has always been, and will continue to be, a fascinating and dynamic space. Like Tets before him, John brings many years of engineering and publishing expertise to his tasks at Chip Design. The EDA industry has much to benefit from having him here to contribute to the ongoing conversation about the business and technology of electronic design automation.
Meanwhile, I'm sure John joins me in thanking Tets for bringing his many talents and energies to Chip Design throughout its first year of publication. I want to personally acknowledge the years that Tets and I have spent working together, both at Chip Design and at ISD Magazine. He has taught me an enormous amount—both about EDA and publishing—and I want to thank him, and wish him and his family all the best going forward.
And so, onto the December issue of EDA Nation. This month's edition is special because, at long last, I have had a chance to visit with Dr. Wayne Wolf, Professor of Electrical Engineering at Princeton University. Wolf received his BSEE, MSEE, and Ph.D. in EE from Stanford University in 1980, 1981, and 1984, respectively. Following on his Stanford years, he spent 5 years at Bell Labs in Murray Hill, New Jersey before settling in as a faculty member at Princeton.
Professor Wolf is widely read, as he has authored several crucial textbooks currently in use at colleges and universities around the world. His books include Computers as Components: Principles of Embedded Computer System Design, Modern VLSI Design, (on its third edition), and a newly released book on FPGA design.
After you have heard from Professor Wolf, please peruse the news. The items here cover mid-October 2004 to early December 2004 and include a number of interesting developments. Of special note on the business side: a new set of senior executives at Cadence Design and an impressive number of announcement regarding mergers and acquisitions, as well as various venture capital investments in new and existing EDA companies. Of particular interest is the Synopsys acquisition of Nassda, following on a number of years of contentious legal battles between the two companies.
On the technical side: The SPIRIT Consortium has followed through on its promise to release the first version of its IP reuse standards. That story will be an interesting one to follow.
This year has turned out to be a very busy one for the EDA industry. Although the revenues across the board are not yet as robust as many would like, there are certainly strong signs of life in the industry. Most definitely, a wide range of diverse and stimulating technical developments have emerged over the last 12 months. Given those trends, I believe we can look forward to an even more dynamic 2005.
A very Happy Holidays to all of you in the EDA Nation. I look forward to seeing you all back here in January.
Back to Top
Subscribe FREE to Chip Design!
History & Geography
"Princeton's Wayne Wolf"
Somewhere in the early 1980s, when I was a graduate student at Stanford, I took a class on VLSI design. Truth be known, I dropped that class midway through the quarter, but in recent years as I've seen Professor Wolf speaking at various technical conferences, I've often wondered if perhaps he'd been the TA in that VLSI class, way back when.
When I asked him that question, at the outset of our phone call in November 2004, to my delight he said, "I did TA the VLSI design course for several years, starting in 1979. If you took the course in that timeframe, then I was your TA because I was the only TA for the course." The rest of our conversation is as follows:
Q: Have you enjoyed living in Princeton after your many years at Stanford?
Wolf: It's actually better here because there's less traffic.
Q: How would you characterize the VLSI design course work at Princeton?
Wolf: About 2 years ago, I uprooted our VLSI course - which was more of a traditional Mead-Conway course - and redid it as an FPGA course. It's not a standard design course, in that we first talk about VLSI, which is sort of digital circuits; we look at what an SRAM is; we look at interconnect delay; and then, we look at FPGA architecture and use that to understand VLSI design. The students [come to] understand why FPGAs are designed the way they are. Then we go on, and do logic design with an FPGA twist. [Through all of this], the students learn how it is that logic design is fairly standard.
There are a couple of reasons why [this teaching strategy] makes sense, at least for a lot of schools. It's actually a lot easier to talk about some of these concepts when you've got something real in front of you. So, if you use an FPGA as the basic source material for a course, you can say to the student, "Here's a chip design for you to understand."
In reality, most Princeton students are not going to go on and become custom VLSI designers. A few of them might go out and do microprocessor design projects, but most of them who are going to do logic design, are going to do FPGAs. So, I decided to redo our design course in this way after listening to various colleagues talk about the decline in custom chip starts over the last couple of years. Certainly, there are custom chips being designed today - large and interesting chips - but not as many as there were in the 1980s. Teaching FPGAs in a VLSI course is a natural conclusion here.
Q: Does this mean that FPGAs are going to dominate the universe?
Wolf: First of all, FPGAs aren't the solution to all of the world's problems, but they are a huge business that's growing like crazy. So, it makes sense for students to understand FPGAs.
They definitely offer enough [technical complexity] to satisfy the needs of a basic course like ours. FPGAs are the right medium for teaching today.
There are probably some schools where it makes sense to teach a [more traditional design] course - schools like Berkeley, UT Austin, or Stanford where they have enough faculty to teach VLSI design and test, and they've got a large number of students who have a chance to really be working in this area. But for a school like Princeton, teaching [with FPGAs] makes more sense right now.
Speaking globally, there is a link between shifts in the technology and the shifting labor [patterns in engineering]. An increasing number of back-end chip designs are being done overseas. However, our using FPGAs in our courses has nothing to do with the cost of labor here in the U.S. versus overseas.
It's more about [having the students become familiar] with the components of design being used today. In telecomm, for instance, FPGAs are widely used for base stations, and so forth. If you're [designing chips] and your customers need high performance, but low volume, you'll probably use FPGAs for that product. In the 1980's, you could do that same design with an ASIC, but now that option's too expensive.
Q: Are the design tools you need for student projects readily available from the vendors?
Wolf: Actually that's another advantage of teaching the basic design courses this way. We use Xilinx tools. They're free, pretty well integrated, and easier for students to use and see the effects of using tools. You can run random, multiple designs using the tools, and you can [execute] place-and-route changes - all processes which are within easy access of the tools.
Q: As students move away from actual circuit design, are you concerned that their basic knowledge of transistors and electrical theory is lessening?
Wolf: Students at Princeton take courses on physics and transistors. The question is, can they use that knowledge to do something that's interesting? Part of the solution is to give them interesting courses where they can understand and learn the basics, and they can also have exposure to realistic problems. Our FPGA course is a good example where students can do something practically, and also learn some circuit theory in the process. [As always], it boils down to a question of breadth versus depth.
Q: For students, who do work on ASIC design in a course at Princeton, do they ever see their chips manufactured?
Wolf: The sophomore students manufacture something very small, with just a few transistors, and they test it. They're able to do all of that in one semester, but they get guided through the process. If you're talking about larger chips, however, we do have some testing facilities on campus. But, there are no more functional testing facilities on campus.
In the old VLSI course that we used to teach here, I didn't have the students fabricate their designs because it just took too long to get them back. [On top of that], there was no guarantee that the students would return for the follow-on course where they would actually test their chips. Again, this is another advantage to the short implementation cycle [associated with FPGAs]. Students have an actual chip in hand much faster.
Q: Where do your students end up after graduating with a degree in Electrical Engineering?
Wolf: Here at Princeton, as fair number of our EEs go into consulting work. They sometimes end up on Wall Street, where they use various sorts of rating algorithms in their work. However, some of our graduates get real engineering jobs, because there are actually a fair number of them who want to stick to engineering. They may go on to work at HP or AMD, and so forth.
Q: How large is the EE Department at Princeton?
Wolf: For Princeton, it's huge. In Electrical Engineering, we have the single largest graduate school enrollment - around 200 students. Those are mostly PhD candidates. You don't have to get a masters [in the process of getting a PhD], but you can get one if you want to.
Q: Is there cooperation between the EE and CS Departments at Princeton?
Wolf: We do get Computer Science students over here, and frequently the EE students go over there. I, myself, have a courtesy appointment in Computer Science.
Q: Where do you think Princeton is ranked among the various EE programs in the U.S.?
Wolf: Well, you talk to different schools and you get different rankings. I take those rankings [with a grain of salt]. At the graduate level, it's a lot more about the individual student and the individual researcher/faculty member [they're working under].
Q: What classes are you teaching currently?
Wolf: I have such a nice schedule. I'm teaching one class this semester, and I'll be teaching two next semester. A lot of my time is spent on research and writing proposals for my graduate and post-doc students.
Q: Where does your research money come from?
Wolf: The majority of the money at the moment comes from NSF, and some comes from the state of New Jersey as well.
Q; How has the enrollment of foreign students changed over the last several years?
Wolf: At the graduate level, we have more domestic students these days because of the economy. For a while, we were mainly getting students from the PRC, India and Taiwan, but those numbers had decreased. Now, they are starting to come back again. We also have students here from Turkey and Greece, and various other places in Europe.
Some of our foreign students are continuing to have visa issues, so we're very careful about sending them to international conferences. We always want to be sure they can return to the U.S. if they go [out of the country]. There was a while there, when we had some of our admitted students who were not able to get the visas they needed to come here to study. But, I hear rumblings that it's starting to get better.
Q: Have you seen a decline in overall enrollment in Electrical Engineering, as has been noted nationally?
Wolf: Yes, there has been a small decline in EE, but that [has stabilized]. A couple of years ago, financial engineering was au courant - trading algorithms and operations engineering. But, I think that has changed again.
Electrical Engineering departments face some very serious issues today. Most are going through some kind of identity crisis - whether they admit it or not - about what EE is and where it should go. I don't have the answer yet, but I think departments should talk among themselves, and the funding agencies, about where this field is going. Electrical engineering isn't in any danger of going away, however. I think that even after Moore's law, there will be [progress that can be made]. I feel strongly that we can exploit the transistors we've got today, for quite some time to come.
To that extent, I'm a bit contrarian. And, I certainly believe we don't have to abandon the existing fields in EE. For instance, you would think there are a lot of interesting problems in power. Certainly you have to ask, would Thomas Edison recognize all of the parts of the modern power grid? He probably would, but nonetheless, there are still good schools that [are actively engaged] in research into power systems. The power grid is one of those existing technologies that people, in general, don't really care about it. They don't want to know what's behind their power [distribution system]. They just know they want it to work. However, there are still many problems that need to be addressed in that area.
Q: What are the principle areas of research in EE at Princeton?
Wolf: There are people here who specialize in signal processing and in computer engineering. The real cutting edge today is biological machines, and there is some very interesting work going on here as well in that area. Also, there is important work being done here in nanotechnology. For the students, however, we offer a fairly traditional degree in EE.
Q: What are your own areas of technical interest?
Wolf: I'm interested in the physical nature of computing - low-power, real-time performance, cost, etc. My PhD was on layout compaction, but I'm not doing physical design anymore. Generally, I work in embedded systems, which includes a lot of work related in some way to a 'smart' camera. The work requires looking at the entire system, from the application down to the chips.
A 'smart' camera is basically a camera with a processor and algorithms that analyze the image or video. One possible application might be that you would have a bunch of cameras to cover the different parts of a room. If you stand in front of one of the cameras, it will tell you where you are in the room. The camera can follow you, and the computation of your location will move with you.
Our original motivation was to create a 'smart' room, a meeting room that's covered with cameras that have full knowledge of everyone in the room. That's clearly one application, but it's not the only application for our systems.
The [larger question is] is - if you want to understand a space, for whatever reason, one camera would never be enough. You would need multiple cameras, which require a way to handle all of that data. You don't want to be dragging that data back to the server, so we put the processing near to the camera. That way, you can actually install and operate these systems in the field. We're trying to make a decision with this system. It's a form of distributed processing, and I think the most interesting question then is what do you do with the information you gather [using the system].
Maybe in certain systems, for instance, you don't actually want certain people in the room, however people might get into that room by 'tailgating' somebody else as they swipe their [legitimate] security badge and enter the room. Eventually, I would like to have some kind of system that says who are the bad guys, who are the terrorists - but as far as I can tell, it's not yet possible to relate general activity or body gestures to a psychological state. So, if you want to just watch somebody, and say they're suspicious - I don't know of any way today to do that as yet. Certainly we know that watching for certain things, certain behaviors, can be useful - but not from a psychological basis.
Smart cameras, in general, have a lot of different uses - medicine, emergency response, etc. Any amount of information on the upper floors of the World Trade Center would have made it safer for the responders on September 11th, for instance. Cameras are getting cheaper thanks to advances in VLSI, so [we're beginning to be able to] afford putting multiple cameras on a subject. [Going forward], when you build buildings, you could install this stuff during construction [and the capability would be there when you needed it].
In general, however, I always try to be agnostic about the applications of the research we do here.
Q: Do you know how Princeton handles intellectual property developed by their graduate students?
Wolf: As far as I understand the law, the students here at Princeton own their course work, but any sponsored work - funded research - is a different matter. John Ritter is the head of our licensing program and I believe he does a good job. There are a fair number of departments here at Princeton who don't generate any IP at all, so it's really a department by department thing.
Q: Did you ever consider staying in industry rather than pursuing a career in academia?
Wolf: I was actually in industry for 5 years (if you call Bell Labs the real world) before I decided to teach. It was a big decision to [transition to academia], but I think it has allowed me to have more of an audience for my ideas. If you want to show your impact inside of a company, there are actually only a limited number of people you can talk to about your technology.
I've always been interested in designing big systems. We used to worry about 10,000 rectangles, whereas now it's 100 million transistors. From that perspective, I'd probably be [looking at the same problems] if I was still in industry. Either way, I would have been interested in climbing the abstraction level. At a university, you have the opportunity to bang your head on the wall and learn some new stuff.
Q: Do you think there's less politics in academia than there is in industry?
Wolf: The main difference is that, if you lose in politics in a company, you get fired. Of course, there are politics in academia, but university politics are kind of like the battle for Stalingrad, whereas industry politics are more like guerilla warfare - the sort of thing where you're solving the problem of the day.
Q: What do you do with your spare time?
Wolf: I spend time with my 2-year-old, who's really interested in understanding things. I also spend time cooking - I do several different types of cuisines. Besides that, I'm working on the 2nd edition of my Embedded Systems Book. My textbook on FPGAs just came out this June. That one took me about one and a half years to write, but it wasn't entirely from scratch because it was derived somewhat from my VLSI book.
Q: You seem like a pretty serious guy, so I'm wondering if you ever tell jokes when you're lecturing?
Wolf: Telling jokes requires delivery, and I'm not sure I've got what it takes. Although, other people always seem to keep laughing when I'm speaking, so maybe I'm funnier than I think.
[Editor's Note: To learn more about Wayne Wolf, and to determine if he has a sense of humor, check out his website: www.princeton.edu/~wolf/bio.html]
Back to Top
Subscribe FREE to Chip Design!
Commerce & Industry
ARM, Artisan Components, National Semiconductor, Synopsys, and UMC announced that the five companies are collaborating to deliver a comprehensive low-power, energy-efficient SoC technology demonstrator for the ARM926EJ-S processor. The "ULTRA" technology demonstrator for the ARM926EJ-S processor is being implemented in UMC's 130e Fusion process, a 130-nanometer process platform designed for the integration of high-speed and low-leakage transistors in a single CMOS process. ULTRA stands for UMC Low-power Technology Reference using the ARM926EJ-S processor.
AccelChip Inc. announced that the Jet Propulsion Laboratory (JPL) has selected AccelChip DSP Synthesis and AccelWare IP libraries to develop a digital filter for space-based radar applications.
Accelerated Technology announced it has combined its UML (xtUML) modeling tool with its prototyping product. The Nucleus BridgePoint for UML modeling suite and the Nucleus SIMdx prototyping environment provides a hardware-independent platform for developing embedded applications.
Agilent Technologies Inc. announced that Innovative Wireless Technologies (IWT) has selected Agilent's Advanced Design System (ADS) software and ultra-wideband (UWB) DesignGuide to help prove UWB design concepts for prototyping. Agilent says the multiyear agreement includes licensing for ADS, its circuit and system simulators, the UWB DesignGuide, and Agilent test equipment.
Agilent Technologies also announced a new budget analysis capability in its ADS 2004A software that the company says enables engineers to design RF systems more accurately, as it predicts RF system performance by considering specification tradeoffs, such as impedance mismatch versus gain, earlier in the design cycle.
Agilent also announced the availability of its ultra-wideband (UWB) Design Exploration Library. The company also announced that Daido Steel Co. Ltd. has selected Agilent's Advanced Design System (ADS) 2004A EDA software and the new UWB Library to help in the development of bandpass filters used for UWB transceivers.
Aldec, Inc. announced Version 4.3 of its Active-HDL 6.3 co-simulation and debugging environment for ESL design and verification. The release includes a direct kernel connection between Active-HDL's mixed-language VHDL and Verilog HDL compilers and the C/C++ compiler, so that the co-simulation environment for SystemC is independent of the entry language. The company says it has also redesigned the waveform viewer.
Aldec and Magma Design Automation announced availability of a design flow interface between Active-HDL 6.3 and PALACE version 2.4. The companies say the integration of the two products automates the data exchange of graphical design capture, mixed VHDL and Verilog verification and physical synthesis, to help provide an efficient solution for Actel, Altera and Xilinx designs.
Altium Ltd. announced a universal JTAG interface to help engineers use the company's LiveDesign tool with any third-party FPGA development board. The JTAG interface attaches to the parallel port of a developer's computer and includes a set of flying leads that connect to the target development board.
Altium also announced support for a range of FPGA daughter boards for its FPGA-based development board, the NanoBoard. The additional daughter boards cover devices from CPLDs to high-performance FPGAs.
Altium separately announced a new plug-in daughter board supporting the Xilinx Virtex-II Pro FPGA as part of a comprehensive FPGA daughter board release for Altium's "LiveDesign-enabled" FPGA-based development platform.
Altium also announced the release of the P-CAD 2004 PCB design system, which the company says includes 50+ new and enhanced features, including upgraded layout and automatic and interactive routing, improved support for CAM file editing and circuit simulation, and other enhancements for greater power and control over the PCB design process: a new interactive Advanced Route tool, and complete control over all interactive routing features, including the level of 'glossing' or trace cleanup the tool attempts during interactive routing.
Finally, Altium said it will expand the HDL capabilities of Nexar with support for Verilog. Also, the upcoming Service Pack 2 for Altium's DXP 2004 design systems, which includes updates for Nexar and the Protel board-level design system, will add syntax-aware code editing, parsing and compilation support for Verilog. Service Pack 2 for its Nexar software will include a 32-bit FPGA-based RISC processor to help to take the risk out of migrating systems to the 32-bit domain.
Anadigm has launched the first of a series of Configurable Analog Starter Kits that include ready-to-use EDA files, source code for dynamic configuration, and step-by-step instructions for implementing the circuit in a field programmable analog array (FPAA).
Applied Wave Research, Inc. (AWR) announced that Silicon Laboratories, Inc. has adopted AWR's Microwave Office and Visual System Simulator (VSS) design suites. Silicon Laboratories teams will use the AWR software to simulate RFIC chips and modules.
ARM announced that it has released its PrimeXsys Platform, based on the ARM1176JZF-S 32-bit processor core, to STMicroelectronics.
ARM also announced the Cortex-M3 processor, designed to for high system performance in cost-sensitive embedded applications. It is the first member of the new Cortex family of CPU cores.
Atmel Corp. and Mentor Graphics Corp. announced an extension of the OEM agreement between the two companies for synthesis, simulation, and verification tools from Mentor. The companies say the new agreement spans the spectrum of tools required for both FPGA and CPLD design.
Bluespec Inc. and Novas Software, Inc. announced that the companies have created a debugging environment for behavioral synthesis that allows hardware design engineers to debug high-level, untimed, behavioral source code. The environment allows interactive cross-probing and communication between Bluespec's Blueview design visualization tool and the Novas Verdi Automated Debug System.
Cadence Design Systems, Inc. announced that Azul Systems implemented a high-density, high-speed design using the Cadence Encounter digital IC platform and RTL Compiler.
Cadence also announced that PalmChip Corp. has qualified Cadence Encounter RTL Compiler for implementation of PalmChip's AcurX SoC platform. The companies say that using the tool, core IP blocks of the AcurX platform achieved up to 3x faster run times than with PalmChip's previous synthesis solution.
Cadence also announced a collaboration with IBM to launch Power.org, an open standards community to help IC designers develop SoCs using the IBM PowerPC Architecture, and dedicated to promoting the IBM PowerPC Architecture as the preferred open-standard hardware-development platform for electronic systems for markets such as consumer electronics, networking, storage, military and automotive.
Cadence also announced an assertion-based verification (ABV) solution as a part of its Incisive functional verification platform. The technology includes broad, native assertion support for Property Specification Language (PSL), SystemVerilog Assertions (SVA) and Open Verification Library (OVL). In addition, Cadence is also introducing an extended open-source library of assertions.
Cadence also announced the Encounter Diagnostics yield diagnostics tool, designed to help identify nanometer IC yield problems and locate root cause defects. The new tool supports all digital design styles and test vectors produced by ATPG tools.
Cadence also announced that Toshiba Corp. and Toshiba Microelectronics Corp. taped out a 24-million-gate chip using Cadence SoC Encounter. The chip is Toshiba's largest to date, and was designed using Toshiba's TC300 process for 90-nanometer technology.
Cadence also announced enhancements to its Encounter Conformal technology, Encounter Conformal 5.0, to provide verification capability to insure that the tapeout accurately reflects design intent. New capabilities in include FPGA support, clock domain checking and advanced datapath verification.
Finally, Cadence and Chartered Semiconductor Manufacturing announced that the companies have jointly qualified the Cadence Fire & Ice QX cell-based extraction tool for Chartered's advanced nanometer processes.
Chronology, a division of Forte Design Systems, announced TimingDesigner version 7.0, an interactive timing analysis and diagram product. Version 7.0's project manager feature helps exchange timing information, and helps users manage the specification and analysis of interfaces for digital IC and board designs. Designers can organize multiple diagram components within one project; components and blocks are arranged and displayed in a single tree, with a summary list of all constraint violations in the project diagrams. Designers can also merge two diagrams from different components, to automatically create an interface to account for component connectivity, as well as to manage signal duplication and propagation delays.
CoWare Inc. and LSI Logic Corp. announced availability of ZSP SystemC-based models for use with the CoWare ConvergenSC design environment. LSI Logic says it developed cycle- and transaction-accurate SystemC-based models for each of the available ZSP cores and, through joint cooperation with CoWare, integrated the ZSP models into CoWare's ConvergenSC Model Library.
CoWare and Forte Design Systems announced an integrated SystemC-based solution for ESL design to implementation. The integration of CoWare's SystemC-based ConvergenSC SoC design tools and Forte's Cynthesizer SystemC behavioral synthesis product aim to unite system architecture, simulation, and synthesis in the flow. Users can explore/validate a design's system architecture in ConvergenSC, then synthesize to RTL Cynthesizer, and verify the RTL in a system context with the same SystemC model.
CoWare also announced a new release of its SystemC-based ConvergenSC SoC design tools. New features allow for faster modeling and debug of IP models, platform subsystems, and SoC designs in SystemC, with an open environment that helps integrate internal tools and IP into the system-level flow. The new development environment includes a SystemC integrated development and debug environment (IDE) based on the open Eclipse C++ development environment for embedded software. In addition, ConvergenSC supports the latest release from OSCI, SystemC version 2.1.
Denali Software, Inc. announced an IP core, and design and verification IP software that use ARM's AMBA AXI interface. The product, PureSpec-AXI, uses technology from the PureSpec product line to provide for pre-silicon verification of functionality, compliance and system-level verification of designs utilizing the AMBA AXI architecture. Denali's new IP core, Databahn-AXI, and uses Denali's Databahn DDR controller IP, and provides developers with a native AMBA AXI interface for its DDR-based memory controller cores.
The Embedded Microprocessor Benchmark Consortium (EEMBC) and Patriot Scientific Corp. announced EEMBC has published the benchmark scores for Patriot Scientific's IGNITE 2FX 32-bit processor. The processor was tested against the EEMBC Consumer benchmark suite in a 600-MHz simulation, and achieved an out-of-the-box score of .01808 Consumermarks per MHz
eSilicon Corp. announced that it collaborated with Aarohi Communications and Synopsys in the tapeout of a complex chip design, and subsequent first-pass functional silicon.
HelloSoft, Inc. and Toshiba America Electronic Components, Inc. (TAEC) announced an enhancement to HelloSoft's VoIP software suite, which has been optimized for the Toshiba T6TC1XB-0001 embedded controller.
Hong Kong Science and Technology Parks Corp. (HKSTP) and Synopsys announced that HKSTP has licensed Synopsys' DesignWare IP cores portfolio.
IMEC says it has developed an integrated low-cost, low-power, pulse-based ultra-wideband pulser designed in 0.18-micron CMOS logic technology. The transmitter is 0.6 x 0.6 mm, operates between 3 and 5 GHz, and is flexible in both center frequency and bandwidth.
Impulse Accelerated Technologies, Inc. announced a new edition of its CoDeveloper C to RTL design tools, which support for Altera's SOPC Builder and the Quartus II, Version 4.1 design software. CoDeveloper is a tool to describe, debug and test mixed hardware/software applications using standard C development tools such as Visual Studio and GCC/GDB - and compile those applications directly to Cyclone or Stratix devices without writing low-level VHDL or Verilog.
Infineon Technologies announced that their 150-MHz TriCore TC1130 microcontroller, which the company says is a 32-bit chip capable of running the Linux OS, has achieved an "exceptional" score of 95.2 Automarks in tests against EEMBC's automotive/industrial benchmark suite.
The Joint Development Project (JDP) between Silterra Malaysia Sdn. Bhd. and IMEC announced functional SRAM chips at Silterra's wafer fabrication facility in Malaysia. The device was an 8-megabit SRAM, and was fabricated in the all-copper, foundry compatible 0.13-micron CMOS process technology jointly developed by both companies.
Kilopass Technology, Inc. announced that its XPM technology is now available for use in ASICs and SoCs using standard logic CMOS 90-nanometer silicon processes, in addition to its current products that are based on 0.18, 0.15, and 0.13-micron processes.
Magma Design Automation Inc. and Cadence Design Systems announced that Magma's IC implementation system now supports the effective current source model (ECSM) from Cadence.
Magma also announced that DongbuAnam Semiconductor has standardized on SiliconSmart CR and SiliconSmart IO characterization and modeling technology. The companies say the tools will be used for timing and low-power characterization of DongbuAnam's next-generation nanometer libraries.
In addition, Magma and Mentor Graphics announced an interoperability agreement to integrate the Mentor's TestKompress embedded deterministic test (EDT) tool into Magma's RTL-to-GDSII design system. Mentor and Magma will "provide mutual customers with an integrated IC implementation flow that includes comprehensive DFT capabilities to ensure design closure and testability of nanometer designs."
Magma also announced that NEC Electronics America, Inc. verified a multimillion-instance nanometer design, using Version 4.2 of the Blast Fusion physical design system, complete with Magma's third-generation routing technology.
Finally, Magma announced that a "fully-validated" RTL-to-GDSII design enablement kit for the IBM-Chartered Semiconductor Manufacturing jointly developed 90-nanometer process platform is now available online.
MatrixOne, Inc. announced the Synchronicity Developer Suite V4.1, which introduces a new DesignSync package and DesignSync CTS (Custom Type System). DesignSync CTS allows customers to create a plug-in to recognize and manage data from other EDA tools that are not supported "out of the box."
MatrixOne also announced that Elettronica, a manufacturer of defense equipment and systems, has completed implementation of MatrixOne's PLM platform.
Mentor Graphics announced that the Platform Express SoC design creation tool now supports the SPIRIT 1.0 specification for IP design reuse (see below).
Mentor Graphics also announced additional functionality for the Calibre platform - Calibre Transition, Measure and Analyze - which the company says will address DFM requirements. Mentor also outlined its roadmap for future Calibre DFM tools, to include optimization for manufacturing at various stages in the design flow: design, verification and analysis, tapeout and test.
Mentor Graphics also announced that ATI Technologies Inc. is using Mentor's VStationTBX verification accelerator.
Mentor Graphics also announced that the Institute of Computing Technology (ICT) of the Chinese Academy of Sciences has selected the VStationPRO emulation system as the verification platform for its Goodson series CPU chip.
Mentor Graphics also announced that NEC Electronics has adopted Mentor's analog mixed-signal simulator, ADVance MS tool for development of large, high-speed I/O interface circuits for NEC's analog and mixed-signal SoC products.
Mentor Graphics also announced the availability of two new iSolve speed adapters from its family of emulation products supporting the USB and PCI Express industry standard protocols.
Mentor Graphics also announced a collaboration with Xilinx to supply Expedition and PADS users with reference data, which allows them to more efficiently implement the multi-gigabit transceiver (MGT) technology available in Xilinx FPGAs.
Finally, Mentor Graphics announced the XtremePCB design tool that allows multiple members of a PCB design team to work simultaneously on a design from a single database on a global network, whether they are in the same office or dispersed geographically.
OASIS Tooling has announced support of the OpenAccess platform version 2.2.
PolarFab says it has improved its 6-inch complementary BiCMOS (c-BiCMOS) RFBC/ABC3 processes to provide reduced die sizes and decreased design times. Three digital cell libraries have also been added to the company's RFBC/ABC3 standard cell library portfolio in order to reduce design times.
Also, PolarFab and Mentor Graphics announced the availability of a design kit (DK) which supports the PolarFab PBC4 BCD process technology. The DK is available for use with Mentor's Analog/Mixed-Signal (AMS) IC Design Flow. Apogee Technology Inc. says the company has taped out a next generation mixed-signal chip using the PBC4 kit.
PowerEscape, Inc. introduced its second generation products, PowerEscape Architect and PowerEscape Analyzer. The tools provide for power optimization strategies for both hardware and software engineers, by indicated the ideal memory architecture to the system architect while also indicating power bottlenecks in embedded code to the software developer.
QualCore Logic said it has added two new IP cores to its product portfolio. The first is a digital Serial ATA Host Controller with OCP Interface. The second is high-speed analog dual serializer/deserializer (SerDes) core for SXGA/SXGA+/UXGA application that utilizes a Low Voltage Differential Signaling (LVDS) I/O.
QuickLogic Corp. announced it now has a "Wireless Application Portal" on the company's website, which the company describes as a "comprehensive resource that discusses the challenges associated with wireless system design and provides users with solutions to these challenges, particularly related to 802.11a/b/g Wi-Fi."
QuickLogic Corp. also announced a partnership with Renesas Technology Corp. that the companies say will enable low-power products for the expanding WiFi market. The technology consists of Renesas' SH processor and a programmable companion bridge from QuickLogic for connectivity to miniPCI and Cardbus based WiFi modules or chipsets.
Sequence Design announced that Q-DOT has selected Sequence's Columbus-AMS RLC parasitic extraction tool for inductance and capacitance extraction.
Sequence Design also announced that S3 Graphics used the company's PhysicalStudio optimization software to reduce timing and noise violations on various S3 Graphics' designs.
Finally, Sequence announced a "major milestone" in recent power optimization efforts with Toshiba, which says it signed off on a wireless design using Sequence's MTCMOS (Multi-Threshold CMOS) technology.
Silicon Dimensions, Inc. announced Chip2Nite 2.0, whose features include a new DRC suite, auto-macro placement and block floor planning capability, improved statistics reporting, and a 5x to 10x improvement in "typical" database load times critical for prototyping and what-if analysis.
SoftJin has released a free suite of IC design layout data exchange libraries and tools for use by IC designers and EDA product companies, including GDSII and OASIS readers, writers and GDSII-to-OASIS translator, in source code form. The suite is named Anuvad, and includes tools to handle the OASIS format.
Sonics Inc. announced its new SonicsMX product for the design of low-power SoC devices for wireless and handheld products. SonicsMX provides physical structures, advanced protocols, and power management capabilities. SonicsMX is the result of a collaboration between Sonics and Texas Instruments, which verified that Sonics' SMART interconnect is suitable for low-power operation such as TI's OMAP platforms.
SMSC and TransDimension announced that TransDimension's high-speed USB controller IP, a ULPI interface block, and SMSC's USB3300 ULPI stand-alone physical layer transceiver (PHY), are the first products to pass the high-speed USB Implementers Forum (USB-IF) compliance testing using the new ULPI interface.
Stelar Tools, Inc. has introduced HDL Explorer, a rapid RTL closure tool. HDL Explorer provides a combination of new design creation, and exploration and editing of new and legacy designs and testbenches using best-known methods (BKMs). HDL Explorer is designed to let designers and verification engineers find and fix errors, and define and manage the design/verification interface in new or existing HDL designs. HDL Explorer is the first in a family of products that Stelar will be bringing to market.
Stelar Tools also announced that it has integrated Verific Design Automation's HDL Component Software with its graphical and textual design environment. Verific's HDL Component Software has C++ source code-based Verilog and VHDL parsers, analyzers and elaborators, and acts as a front end to Stelar's toolset.
Stone Pillar Technologies Inc. announced that Micrel Inc. has adopted the DesignRuleBuilder component of the company's Silicon Insight toolkit for semiconductor technology development.
Synopsys, Inc. and Shanghai Hua Hong NEC Electronics Ltd. (HHNEC) announced that HHNEC has adopted Synopsys' Proteus optical proximity correction (OPC) software. HHNEC is a joint venture between NEC Corporation, Jazz Semiconductor and Shanghai Hua Hong Group.
Synopsys also announced that NVIDIA Corp. has adopted Synopsys' Galaxy 2004 test tool for its designs.
Synopsys also announced that STMicroelectronics used the Galaxy Test flow to "significantly increase its fault coverage and reduce tester time on its latest high-volume printer chipset."
Synopsys announced the DesignWare VIP (verification IP) suite for the AMBA 3 AXI protocol, which resulted from a between Synopsys and ARM.
Synopsys also announced that Sasken used Synopsys' Galaxy Design Platform to develop a reference flow to enhance implementation and signoff for its various complex designs.
Meanwhile, Synopsys and KLA-Tencor announced that they are collaborating to develop a compact yield analysis and modeling system for Toshiba Corp. The new modeling system will enable Toshiba to improve parametric yields on its sub-100-nanometer SoC products.
Synopsys also announced that it now supports the Intel Xeon processor with Intel Extended Memory 64 Technology (Intel EM64T) for 64- and 32-bit computing, with the Red Hat Enterprise Linux version 3 operating system, using its Galaxy design and Discovery verification technology.
Finally, Synopsys said that Micron Technology, Inc. has chosen Synopsys' SiVL silicon-versus-layout software to help implement advanced DRAMs, flash memories, CMOS image sensors, and other semiconductor components.
Synfora, Inc. announced A new release of PICO Express, a tool for application engine synthesis (AES). This version of PICO Express provides for faster IP integration and verification, and includes FPGA synthesis scripts for industry-standard tools to support FPGA prototyping for system verification.
SynTest Technologies announced that its DFT-PRO 100 and 200 Series of ATPG starter packages include the DFT tools for comprehensive ASIC testing. The tools operate on scan-inserted netlists and include tools for testing DFT rules' violations, ATPG, and test pattern formatting.
Tensilica Inc. announced that ATI Technologies Inc. has licensed the Xtensa configurable processor.
Tensilica also announced that Seiko Epson Corp. has licensed the Xtensa configurable processor for next-generation imaging products.
Teseda Corp. and Yokogawa Electric Corp. announced that they will work together to verify transportability of Standard Test Interface Language (STIL) DFT data between the Teseda OpenDFT WorkBench engineering software and production test platforms.
Teseda also announced the OpenDFT initiative "to exploit the full power of design-for-test (DFT), uniting design, test, and manufacturing to cut weeks from time-to-money and improve device yield and profitability." Teseda says it has worked with EDA and ATE vendors to develop the OpenDFT WorkBench software to bring DFT-Intelligent interactive validation, debug, and diagnosis to ATE platforms.
In related news, Teseda, in cooperation with Agilent Technologies, announced the development of the Teseda OpenDFT WorkBench software for the Agilent 93000 SOC Series platform.
Thomson announced that the company has licensed ARM OptimoDE signal processing technology for the development of broadcast video processing ICs.
Toshiba Corp. and Xilinx announced a strategic foundry relationship whereby Toshiba will manufacture Xilinx FPGA products. The companies say they have already achieved functional 90-nanometer first silicon at Toshiba's 300-mm fab at Oita, in Kyushu, Japan. Subsequently, Toshiba will start volume manufacturing in Q1 2005.
Meanwhile, Toshiba Corp. and ARM announced that Toshiba has licensed the ARM1136J-S processor. Toshiba says it will use the processor to develop ASICs for products such as consumer electronics and network systems.
TransEDA announced version 2.5 of its imPROVE-HDL formal property checker. Improvements aim to enhance the use of assertion-based verification (ABV) methodologies for SoC design. In addition to reading PSL assertions from an external file, imPROVE-HDL v2.5 now supports PSL in both VHDL and Verilog embedded in the design.
Verific Design Automation announced that it is shipping "the first commercially available" SystemVerilog parser. The parser supports the entire SystemVerilog 3.1 language definition, with the exception of SystemVerilog Assertions, for which it supports 3.1a.
ViASIC Inc. announced the availability of its new 0.13-micron ViaMask library for TSMC and TSMC-compatible processes. The company says the new library is silicon-proven and produces a 10-percent increase in density, and a higher performance than the previous version.
X-FAB Semiconductor Foundries AG says it has a new, patented PIN-diode module for its 0.6-micron BiCMOS technology (XB06). The company says it's now possible to integrate PIN diodes (PIN = positive intrinsic negative) with CMOS and BiCMOS transistors on a single chip.
Xilinx announced the EasyPath FPGAs, described as "the industry's only customer-specific and flexible solution for volume production priced lower than structured ASICs."
Xilinx also announced two new devices in the CoolRunner-II CPLD product family, the CoolRunner-IIA available in 32 and 64 macrocell densities. The XC2C32A and XC2C64A devices incorporate an additional I/O bank to support voltage level translation and device interfacing. Xilinx is also offering the two devices in smaller footprint, lower cost packages.
ZMD announced a sub-1GHz, IEEE 802.15.4 development kit for ZigBee applications, the ZMD44101DK, which lets developers perform detailed evaluation of ZMD's low-power ZMD44101 RF transceiver using a graphical interface.
Back to Top
Subscribe FREE to Chip Design!
Economics & Finance
Cadence Design Systems, Inc. announced total revenue for the third quarter of 2004 of $302 million compared to $269 million in the same period last year. On a GAAP basis, Cadence recognized net income of $20 million, or $0.07 per share in the third quarter of 2004, compared to a net loss of $14 million, or $0.05 per share in the same period last year. Using a non-GAAP measure, earnings in the third quarter were $52 million, or $0.19 per share, on a fully diluted basis as compared to $34 million, or $0.12 per share, on a fully diluted basis, in the same period last year.
Mentor Graphics Corp. announced third quarter pro forma diluted earnings per share were $.05, on revenue of $162 million. On a GAAP basis, the company reported a loss of $.08 per share, driven lower primarily by special charges for in-process R&D associated with the acquisition of 0-In Design Automation. Revenue grew 3% over the year ago quarter, while bookings grew 2%. By geography, bookings in PacRim climbed 20%, North America was up 5%, and Europe was down 10%. Japan was flat, but continued at bookings levels nearly double the historical rate of the late 1990s. Revenue by region was 40% Americas, 30% Europe, 20% Japan, and 10% Pacific Rim.
Company Chairman and CEO Wally Rhines was quoted in the Press Release: "Although growth in the third quarter was slow, it was primarily due to the timing of major orders. Year-to-date bookings have grown over 8% and we expect an all-time record level in fourth quarter and full year bookings growth of 10%."
Nassda Corp. announced financial results for the quarter ended September 30, 2004, the fourth quarter of Nassda's fiscal 2004. Revenue for the quarter ended September 30, 2004 was $11.0 million, a 31% increase from $8.4 million for the quarter ended September 30, 2003 and was substantially unchanged from $11.0 million for the quarter ended June 30, 2004. Net income for the quarter ended September 30, 2004 was $175,000, or $0.01 per diluted share, a decrease of $148,000 from $323,000, or $0.01 per diluted share, for the quarter ended September 30, 2003 and a decrease of $891,000 from $1.1 million, or $0.04 per diluted share, for the quarter ended June 30, 2004. Total revenue for fiscal 2004 was $41.5 million, an 18% increase from $35.1 million for fiscal 2003. Net income for fiscal 2004 was $2.6 million, or $0.09 per diluted share, a decrease of $1.0 million as compared to net income for fiscal 2003 of $3.6 million, or $0.12 per diluted share.
TransEDA reported 40% growth one year after the merger with TNI-Valiosys.
X-FAB Semiconductor Foundries AG announced sales revenues increased by 27 percent to EUR 38.3 million, with an operating result of EUR 2.4 million in the third quarter. This compares to an operating loss of EUR 8.2 million in the same period of 2003. Earnings before interest and taxes (EBIT) also improved to EUR 1.3 million, following negative earnings of EUR 7.8 million in the third quarter of 2003. Net income as of September 30, 2004 was EUR 6.1 million, with EUR 0.4 million attributable to the third quarter. In the previous year, the company reported a loss of EUR 15.4 million for the first nine months and a loss of EUR 8.4 million for the third quarter. Sales revenues in the first nine months of fiscal year 2004 totaled EUR 105.3 million, up 26 percent versus the same period last year.
Denali Software Inc. announced it is a new member in the ARM Connected Community, whereby Denali will have access to resources to help developers get "ARM Powered" products to market faster.
EMA Design Automation and the Chronology Division of Forte Design Systems announced a strategic partnership. EMA says it will provide exclusive distribution and support throughout North America for Chronology's TimingDesigner timing analysis product.
Emulation and Verification Engineering (EVE) announced that Crescendo Technologies Ltd. has become EVE's exclusive distributor in China. Under terms of the distribution agreement, Crescendo Technologies will market and support EVE's products throughout China.
LSI Logic announced the formation of the RapidChip Platform ASIC Partner Program, a cooperative effort between LSI Logic and third-party providers of IP, design services and EDA tools. The 13 initial companies participating in the program include: ARM, Arrow, Denali Software, GDA Technologies, Memec, PLDApplications, Pinpoint Solutions, Synplicity, Silicon Infusion, TeraSystems, Daito Electron Co., Innotech, and Reptechnic Design.
Synfora, Inc. has named Design Automation Solutions, Inc. (DASI) as its channel partner for the South Central U.S. The companies announced that Scott Spurlin and Doug Peterson will manage the DASI team for Synfora.
Tower Semiconductor Ltd. has named QualCore Logic Inc. to be a member of the Tower Authorized Design Center (TADC) program. The program helps Tower's customers by linking Tower Semiconductor to design firms to provide hardware designers with support for the Tower fabrication flow.
True Circuits, Inc. announced it has signed Amos Technologies as an authorized sales representative in Israel.
Aprio Technologies Inc. formally announced the company, its funding, and the company's intent to play in the DFM space. Prior to the November 1, 2004 announcement, the company was in a "stealth mode." Aprio says initial products will be announced soon. Aprio was founded in January of 2003 by Clive Wu and Daniel Ho. Randy Smith joined the company in December 2003. The company has had two rounds of funding, with a total to date of $10 million. Previously, Aprio CEO & CTO Wu was Engineering Vice President at Numerical Technologies. Wu has a PhD from Stanford, and has authored 10+ patents on resolution enhancement technology (RET) and DFM. Daniel Ho is Aprio's co-founder and Vice President of Engineering and Operations. Previously, he e was a founding member of Ambit Design Systems, and also worked at both Valid Logic and Cadence Design Systems. Randy Smith is Aprio's Vice President of Sales and Marketing. Previously, he was a founding member of Tangent Systems, later acquired by Cadence. Smith also served in senior positions at TriMedia Technologies, Artisan Components, Gambit Automated Design, and Celestry Technologies.
Bluespec Inc. announced that it has secured $4.5 million of additional funding, with the round led by inside investors Atlas Venture and North Bridge Venture Partners. Bluespec says its total funding now stands at $8.5 million.
Silicon Design Systems, Inc. announced the addition of Gemini Funds as an investor, and said the company has expanded the amount of its series B investment funding to $9.2M. Gemini joins Carmel Ventures and Infinity Partners in the recently closed Series B funding led by Carmel Ventures. Gilo Ventures II led the Series A funding, and also participated in Series B. Tali Aben from Gemini is joining the Silicon Design Systems Board of Directors.
Xoomsys Inc. announced that it has secured $7 million in its first round of venture financing, which included funds from Benchmark Capital and Morgenthaler Ventures. The company also announced that Naren Gupta, Vice Chairman of Wind River Systems, and Buno Pati, Founder and CEO of Numerical Technologies have also invested in Xoomsys. Alex Balkanski from Benchmark Capital and Bob Pavey from Morgenthaler Ventures will join the Xoomsys Board of Directors. Balkanski is a General Partner at Benchmark Capital and previously headed up C-Cube and DiviCom. Pavey is a General Partner at Morgenthaler Ventures. He is past president of the National Venture Capital Association. Buno Pati will serve as Chairman of the Board.
Beach Solutions announced it has acquired VCX Software, Ltd. VCX runs the www.theVCX.com. Beach says it is committed to enhancing theVCX.com portal and supporting the numerous commercial and informational websites that utilize the VCX Gateway search engine. Terms of the agreement were not disclosed. The VCX staff, technology and IP are transferring to Beach.
LogicVision, Inc. announced that it has entered into a definitive agreement to acquire SiVerion, Inc. by issuing two million shares of its common stock and $2 million in cash at closing, plus a contingent future payment of up to $2 million. SiVerion will become a business unit of LogicVision, will retain all its employees, including its president Thomas Martis, and will continue its operations in Arizona. Gregg Adkin, a general partner of Valley Ventures, SiVerion's primary investor, will join LogicVision's board of directors. The terms have been unanimously approved by the boards of directors of both companies, and the transaction is expected to be completed in Q4 2004, pending approval by SiVerion's stockholders.
Synopsys, Inc. announced the acquisition of Cascade Semiconductor Solutions, Inc. The companies say that Cascade's digital IP complements Synopsys' PCI Express Verification IP and PHY (Physical Layer of the PCI Express protocol), and creates "a complete PCI Express IP solution." Synopsys and Cascade say that together they have PCI Express design wins at 25+ companies.
Synopsys also announced it has acquired "certain assets" and hired the engineering team of LEDA Design. LEDA Design has 80+ digital and mixed-signal IP design engineers and support personnel located in Yerevan, Armenia, who will now join the Synopsys DesignWare IP engineering team. The terms of the transaction were not disclosed.
Synopsys also announced that its Board of Directors has renewed its stock repurchase program last renewed in December 2003. Per the Press Release: "Under the renewed program, the Company may repurchase Synopsys common stock with a market value up to $500 million (not including amounts purchased to date under the program) on the open market. Purchases may be made beginning immediately and ending at such time as the authorized funds are spent or the Company discontinues the program. All purchases shall be made at prevailing prices and will be funded from available working capital. The repurchased shares may be used for ongoing stock issuances, such as for existing employee stock option and stock purchase plans and acquisitions. During fiscal 2004, Synopsys acquired a total of approximately 16.9 million shares, at an average price of approximately $25.02."
Perhaps most significantly, Synopsys announced it has signed agreements to acquire Nassda Corp. in an all-cash transaction at $7.00 per share and, subject to the closing of the acquisition, to settle all outstanding litigation by Synopsys against Nassda and certain Nassda officers, directors and employees. The aggregate purchase price will be approximately $192 million, or approximately $92 million net of Nassda's estimated cash at closing. In addition, upon closing, the Nassda officers, directors and employees who are defendants in the litigation between Synopsys and Nassda will make settlement payments to Synopsys in the aggregate amount of $61.6 million.
The definitive agreements for the acquisition have been approved by the boards of directors of both Synopsys and Nassda, as well as by a special committee of Nassda's board. The acquisition is subject to approval by the holders of a majority in interest of Nassda's outstanding common stock. Certain directors, officers and employees of Nassda who own in the aggregate approximately 60 percent of Nassda's outstanding common shares have agreed to vote in favor of the transaction. The acquisition is further subject to approval by a majority of votes cast at Nassda's upcoming special meeting of stockholders, excluding votes cast by the defendants in the litigation between Synopsys and Nassda, certain associated parties of the defendants, and Nassda's officers and directors. The acquisition is also subject to customary regulatory approvals and other closing conditions.
Rex Jackson, Vice President and General Counsel of Synopsys, is quoted in the Press Release: "This acquisition successfully resolves the litigation between our two companies and sends a strong message of Synopsys' commitment to protecting and preserving its intellectual property, By acquiring Nassda rather than continuing through the courts, Synopsys can preserve Nassda's products and continue long-term support of Nassda's customers."
Back to Top
Subscribe FREE to Chip Design!
Politics & Government
AccelChip Inc. announced its membership in the Fabless Semiconductor Association (FSA). AccelChip says it is joining the FSA as an associate member.
Denali Software, Inc. announced that Co-founder and CEO Sanjay Srivastava has been named to the nine-member EDAC Board of Directors. Srivastava will be filling the 2004-2006 board seat vacated by Bernie Aronson, the current president and CEO of Kilopass, who was previously CEO of Synplicity.
The Embedded Microprocessor Benchmark Consortium (EEMBC) says it plans to add an energy consumption metric to the performance scores it provides for embedded processors tested against its application-focused benchmarks. The consortium has formed two working groups to establish methodologies for the energy consumption benchmarks. One group will address energy measurements for hardware platforms and devices, and will be headed up by Shay Gal-On of PMC-Sierra. The second group will address energy measurements using simulation for IP processor cores, and will be headed up by Moshe Sheier of CEVA. The consortium has also engaged David Kaeli, Associate Professor in Northeastern University's Department of Electrical and Computer Engineering and director of its Computer Architecture Research Laboratory, to guide EEMBC's energy benchmark developments. EEMBC Kevin Kranen, Director of Strategic Programs at Synopsys, has also been actively involved in this process.
EEMBC also announced that IPFlex Inc. has become a member of the consortium. EEMBC says that IPFlex will be a full member of the consortium's Board of Directors.
Open Core Protocol International Partnership (OCP-IP) announced an updated version of their OCP 2.0 compliant transactional models implemented in SystemC. The models standardize the way OCP- based communication is modeled at various abstraction levels. The updated OCP SystemC transaction channel models include a speed-optimized transaction layer 2 (TL2) channel. The new release also includes an OCP monitor and layer adapters.
OCP-IP also announced four new members including: 3plus1 Technology, AccelChip Inc., Hantro Products OY, and Synfora.
In conclusion, OCP-IP announced the launch of a Japanese version of its website. The new version of the website allows Japanese visitors to access the organization's information and materials in their native language. OCP-IP OCP-IP says that Governing Steering Committee member Toshiba helped with creation of materials for the new website.
The SPIRIT (Structure for Packaging, Integrating and Re-using IP within Tool-flows) Consortium announced the first public release of the approved SPIRIT specification. The SPIRIT Version 1.0 is designed to allow SoC designers to have access to an industry standard for IP reuse that will enable them to select, configure and integrate SPIRIT-compatible IP from multiple vendors using various SPIRIT-compatible EDA tools and design environments.
The persistent goal of the SoC industry to automate large parts of the system integration process has been plagued by the absence of an industry standard data format for IP integration and configuration. Consequently, most IP integration flows remained proprietary or labor-intensive, hindering adoption. By allowing IP integration data to be expressed in a standard XML format, the SPIRIT specification provides the vital link that will allow IP from multiple vendors to flow seamlessly into multiple tool flows. The standardization will give SoC designers the twin benefits of a richer IP pool coupled with a wider choice of design environments. SPIRIT will also give a real competitive edge to IP providers and tool vendors that adopt the standard. IP vendors will benefit from a standardized way of making their deliverables compatible with customer design flows, and EDA vendors will have a large pool of IP that can be automatically imported, configured and integrated using their design tools.
Back to Top
Subscribe FREE to Chip Design!
Cadence Design Systems, Inc. announced the addition of three executives to its management team: Jim Miller, Ajay Malhotra and Craig Johnson. In addition, the company announced a new role for Ping Chao.
The Implementation and Design & Verification divisions will be consolidated into a single organization, and will be led by Miller in the role of Senior Vice President of Development. Previously, Miller has held engineering and management positions at Intel, Broadcom, and Silicon Spice.
Malhotra will serve as Senior Vice President of Product Marketing. Previously, Malhotra was co-general manager of Enterprise Marketing and Planning in Intel's Enterprise Platforms Group.
Johnson will serve as Vice President of Business Development, and will lead strategy and business development. Johnson was most recently director of Strategic Marketing in Intel's Enterprise Platforms Group. The three new executives will report directly to Fister.
Chao, Executive Vice President and former General Manager of the Design & Verification Division, will assume the role of senior advisor to the executive chairman and executive team.
Catalytic Inc. has named Roderick (Rod) O'Reilly as Vice President of Sales. Previously, O'Reilly served as Vice President of Sales at Segue Software. Prior to Segue Software, he was at LightSpeed Semiconductor, Ikos Systems, Automated Images, and Sun Microsystems. Before Sun, O'Reilly was at Daisy Systems and Fairchild Semiconductor.
Golden Gate Technology, Inc. announced that Dennis Heller has been named as CEO. The company also reminds readers that it recently received $9 million in first-round venture funding. Dennis Heller has approximately 20 years of EDA experience, including executive and management roles at Avanti, Synopsys, and IKOS Systems. He began his career as a microprocessor designer. Heller has a BSEE and MSEE from the University of Wisconsin. Michael Burstein, company co-founder and CEO, will serve as CTO.
Ipextreme announced that Trent Poltronetti is now their Vice President of Marketing, reporting directly to company President and CEO Warren Savage. Previously, Poltronetti was with Synchronicity up through the acquisition of the company by MatrixOne. Prior to Synchronicity, he was at ARM, and prior to ARM, he was part of an investment banking team at a technology brokerage that helped ARM secure early funding. Poltronetti has a BSCE and an MBA from the University of Manitoba.
Jasper Design Automation announced the appointment of Craig Cochran as its Vice President of Marketing. Previously, Cochran served many years in managerial and marketing roles at Synopsys. Prior to his marketing career, Cochran was an applications engineer, a circuit designer and software engineer. He has a BSEE from the Georgia Institute of Technology.
Jasper Design Automation also appointed Nafees Qureshy to be Vice President of Engineering. Nafees has 15+ years of experience in EDA tools development. Previously, he was Senior Director of Engineering at CoWare. Before joining CoWare, Nafees ran his own software consulting company, and prior to that, spent 10 years at IKOS Systems. Before IKOS, he worked at Schlumberger Technologies. Nafees has a B.Tech. in EE from the IIT, Bombay, and an MS in CS from Arizona State University.
In conclusion, Jasper Design Automation has named Craig Shirley to be Vice President of Worldwide Sales and Support. Prior to joining Jasper, he was Vice President of North American Sales at Verisity Design. Before joining Verisity, Shirley held management positions at Avanti, Aspect Development, Quickturn Design Systems, Ready Systems Corp., and Viewlogic Systems. He began his career at Intergraph Corp. Shirley has a BSCE from Auburn University in Auburn, AL.
QualCore Logic announced it has hired 50 additional engineers over the past year. The company says its team now has 60+ analog engineers split between a design center in Hyderabad, India, and the QualCore Logic design center and corporate headquarters in Sunnyvale, CA. The company also says it plans to expand that headcount to 100 in 2005.
Summit Design, Inc. announced that Emil Girczyc has been named President and CEO. He takes over for Charles Hale, Chairman of the Board at Summit Design and former acting CEO for the company. Girczyc has 20+ years of experience in EDA management, serving previously as President and CEO at 0-In Design Automation, VP of Marketing at Cadabra Design Technology, in management positions at Synopsys, and positions as Audesyn and BNR (now Nortel). Girczyc also taught Computer and Electrical Engineering at the University of Alberta and Carleton University.
Synopsys announced it has appointed Jay Greenberg as Senior Vice President of Marketing. Greenberg has 30+ years of experience in marketing. Prior to joining Synopsys, he was Founder and President of Green Mountain Solutions, a consulting organization. Prior to Green Mountain, he was Vice President of Strategic Marketing and Business Development at TSMC. Prior to TSMC, he was Vice president and Senior Partner at the Thomas Group.
Tharas Systems, Inc. has named Richard Curtin as Senior Vice President of Marketing and Business Development. Curtin has 20+ years of marketing, sales and business management experience in the electronics and EDA industry. Prior to Tharas, he was COO at @HDL, Senior Vice President of Sales and Marketing at Xpedion Design Systems, and CEO at Simpod. Curtin also served at Frontline Design and Viewlogic Systems. He started out his career as an ASIC design manager. Curtin has BSCE from Boston University, an MSEE from Cornell University, an MBA from Pepperdine University. He is a co-holder of two US patents in the areas of signal processing and arithmetic computation.
VaST Systems Technology announced that Linda Prowse Fosler has been named Vice President of Marketing and Business Development. Previously, Prowse Fosler was Vice President of Marketing and Business Development for Esterel Technologies, a senior executive at IKOS Systems, and General Manager of the Verification Solutions and New Technologies Group for the Mentor Emulation Division after IKOS was acquired by Mentor. Before IKOS, Prowse Fosler was Vice President of Software Quality at Cadence, and held various positions in software engineering at Tandem Corp. and Hewlett Packard.
Aldec, Inc. announced that its Active-HDL product has been selected as "the most easy-to-use HDL simulator with the best price for its value." The company says the award is part of the first annual FPGA Journal Awards sponsored by FPGA and Programmable Logic Journal. Winners were selected based on feedback from design engineers in several formal surveys and studies held over the course of the year.
Apache Design Solutions announced that it was selected for Silicon Strategies' 60 Emerging Startups list. The companies are selected by the editors of Silicon Strategies, and selection is based on various criteria including technology, intended market, maturity, financial position, and investment profile. The startups are chosen from companies in semiconductors, fab equipment, packaging, foundry, materials, MEMS and EDA software.
eASIC Corp. announced that the company was named to the "Top 100 Most Innovative Companies" by Red Herring Inc. Finalists were selected from 1,200+ entries.
EMA Design Automation announced the Rochester Business Alliance ranking them #1 in the Rochester Top 100. The company says this makes EMA the fastest growing privately held company in all of Rochester, New York.
Back to Top
Subscribe FREE to Chip Design!
Festivals & Fairs
VLSI-Design Conference - This is the 18th International Conference on VLSI Design, and it will be held in Taj Bengal, Kolkata, India from January 3-7, 2005. Co-located with the conference will be the 4th International Conference on Embedded Systems. (vlsi.nj.nec.com)
ASP-DAC - This is the 8th annual Asia & South Pacific Design Automation Conference, being held this time around in Shanghai, China from January 18-21, 2005. Co-located with the conference will be the 3rd Asian University Workshop on Semiconductor Design. (www.aspdac.com)
IEEE ISSCC 2005 - The International Solid State Circuits Conference is taking place from February 6-10, 2005 in San Francisco, CA. This is the companion conference to IEEE's International Electronic Devices Meeting, which takes place every December. (www.isscc.org/isscc/)
DATE 2005 - Europe's principle conference and exhibition for Electronic Design, Automation and Test happens each year in either Paris, France, or Munich, Germany. This time around it will be in Munich from March 7-11, 2005. (www.date-conference.com/)
ISQED 2005 - This will be the 6th International Symposium on Quality Electronic Design, and will be happening March 21-23, 2005 in San Jose, CA. The Topic of this year's meeting will be "Design for Quality in the Era of Uncertainty." (www.isqed.org/)
Back to Top
Peggy Aycinena authors EDA Nation, and owns and operates EDA Confidential at www.aycinena.com. She can be reached at email@example.com.
Subscribe FREE to EDA Nation!
Click here to receive EDA Nation into your email box every month and Chip Design Magazine at your door every other month.