Welcome to EDA Nation, an on-line periodical with news and commentary on the EDA industry. Hosted on the Chip Design website (www.chipdesignmag.com/edanation), the intention here is to provide monthly updates on the industry—as well as some analysis—in a concise and useful format.

As the technology sector rebounds (albeit slowly for those who are impatient), the number of editorial platforms is increasing as well. This newsletter represents part of that upturn in the publishing sector and intends to augment and enhance the technical information and analysis made available to readers of Chip Design Magazine, Extension Media's bi-monthly print publication under the direction of Tets Maniwa as Editor-in-Chief.

Tets has always respected the engineers, sales and marketing folks, and managers that constitute the citizenry of the EDA Nation. I second that notion. In that spirit, I look forward to hearing from all of you regarding this newsletter, just as Tets encourages response to Chip Design Magazine.

Honest and open discourse in an industry—or a nation—is that which makes an industry and a nation strong. Thank you for joining in on the conversation.

Peggy Aycinena
August 2004

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The September 2004 issue of EDA Nation includes a challenge. The lead article is extremely lengthy, but if you can give it the time, the read is well worth the effort. John Sanguinetti is a household name in the EDA industry and this is his profile.

Currently, John is serving as the industry's poster child for Multiple Myeloma, a rare blood cancer and the subject of a lot of intense medical research. As such, John will be the guest of honor at an industry fund-raiser in San Jose, California, on September 15, 2004.

However, that's not what makes John's story here compelling. The reason you should rise to the challenge and read this thing in its entirety is because John Sanguinetti is more appropriately the poster child for EDA - a Ph.D. technologist, an entrepreneur, a long-time player in Silicon Valley, and someone who has influenced and been influenced by the trends and characteristics unique to the EDA industry.

If you're involved in the EDA industry, this is more than John Sanguinetti's story. This is your story.

Peggy Aycinena
September 2004

October is a time of change. Spring and summer have come and gone, and autumn heralds the coming of winter. More than any other time of year, people tend to be looking back wistfully to the seasons just past, while also looking forward with determination - preparing themselves for the challenges and vigorous sport of the winter months.

This month's lead article is about Cadence Design Systems, its future and its past - topics seemingly analogous to the season. The first interview here is with the newly appointed Cadence President & CEO Mike Fister, who is looking forward to the challenges and vigorous sport of building Cadence to be an even bigger player in the EDA industry and the larger semiconductor supply chain.

The second interview, the other part of the autumnal experience, is a conversation with the original CEO of Cadence, Joe Costello, who has just been named by the EDA Consortium as this year's winner of the prestigious Phil Kaufmann Award. When people speak about Costello's era, it's often in wistful terms as his tenure at Cadence from 1987 to 1997 coincided with the glory days in EDA, those years when the industry was expanding rapidly and optimism abounded with regards to the business and technology potential in electronic design automation software.

Voices of the past and future not withstanding, my own impression in talking to these two men is of their remarkable similarity. They are both agile in their thinking, seemingly unfettered by conventional (read "formulaic") wisdom, and both bring a great deal of intense energy and confidence to the table - confidence in technology, confidence in a future based on that technology, and most importantly, confidence in their own abilities to shape and influence that future by shaping and influencing the technology.

They both seem equally able to say to the pending season of winter - 'Bring it on!

Meanwhile, no matter that the economic news out of EDA, and some companies in particular, is hardly something to write home about - the number of technical announcements coming out of the industry rages on! So grab that cup of java and come along for the ride.

Peggy Aycinena
Contributing Editor

First off, I would like to welcome John Blyler as the new Editor in Chief of Chip Design Magazine. John is taking over for Tets Maniwa, who is leaving the magazine to pursue other interests.

The EDA industry has always been, and will continue to be, a fascinating and dynamic space. Like Tets before him, John brings many years of engineering and publishing expertise to his tasks at Chip Design. The EDA industry has much to benefit from having him here to contribute to the ongoing conversation about the business and technology of electronic design automation.

Meanwhile, I'm sure John joins me in thanking Tets for bringing his many talents and energies to Chip Design throughout its first year of publication. I want to personally acknowledge the years that Tets and I have spent working together, both at Chip Design and at ISD Magazine. He has taught me an enormous amount—both about EDA and publishing—and I want to thank him, and wish him and his family all the best going forward.

And so, onto the December issue of EDA Nation. This month's edition is special because, at long last, I have had a chance to visit with Dr. Wayne Wolf, Professor of Electrical Engineering at Princeton University. Wolf received his BSEE, MSEE, and Ph.D. in EE from Stanford University in 1980, 1981, and 1984, respectively. Following on his Stanford years, he spent 5 years at Bell Labs in Murray Hill, New Jersey before settling in as a faculty member at Princeton.

Professor Wolf is widely read, as he has authored several crucial textbooks currently in use at colleges and universities around the world. His books include Computers as Components: Principles of Embedded Computer System Design, Modern VLSI Design, (on its third edition), and a newly released book on FPGA design.

After you have heard from Professor Wolf, please peruse the news. The items here cover mid-October 2004 to early December 2004 and include a number of interesting developments. Of special note on the business side: a new set of senior executives at Cadence Design and an impressive number of announcement regarding mergers and acquisitions, as well as various venture capital investments in new and existing EDA companies. Of particular interest is the Synopsys acquisition of Nassda, following on a number of years of contentious legal battles between the two companies.

On the technical side: The SPIRIT Consortium has followed through on its promise to release the first version of its IP reuse standards. That story will be an interesting one to follow.

This year has turned out to be a very busy one for the EDA industry. Although the revenues across the board are not yet as robust as many would like, there are certainly strong signs of life in the industry. Most definitely, a wide range of diverse and stimulating technical developments have emerged over the last 12 months. Given those trends, I believe we can look forward to an even more dynamic 2005.

A very Happy Holidays to all of you in the EDA Nation. I look forward to seeing you all back here in January.

Peggy Aycinena
December 2004

Welcome to the January issue of EDA Nation. This past year was a complex one in many places around the world, with news and headlines reflecting the stunning developments in politics, war, economics, weather, earth science, and oceanography, just to name a few. Dramatic, frequently tragic, and occasionally beyond comprehension - for many, those headlines defined 2004 and caused them to welcome 2005 with a sense of relief. “That’s enough of 2004! Let’s get on with 2005!”

Meanwhile, there were significant developments within the EDA Nation in 2004. Although the headlines in EDA were rarely on the scale of the larger events sweeping the globe, many of the stories within the industry were interesting, intriguing, and compelling in their own way on both the business and the technical sides of things.

In my estimation, 2005 promises to be even more interesting for those who track EDA. Acquisitions and new management teams at various companies will continue to fuel the business headlines, while news and developments in the areas of verification, DFM, ESL, and embedded software will further amuse and amaze those who track those technologies.

Appropriately then, this month’s article spans both the business and the technology paradigms within EDA. The main article is a discussion with Jeff Jussel, Vice President of Marketing at Celoxica (Abingdon, Oxfordshire, U.K.). These days Jeff is carrying around a nifty set of PowerPoint slides that help to articulate Celoxica’s position in the market. The slideshow details Jeff’s and Celoxica’s take on electronic system level design (ESL), how ESL interfaces with EDA, and how Jeff’s subsequent definition of behavioral synthesis differs from that of Celoxica’s competition.

Of course, you might be inclined to ask why any set of slides from a VP of Marketing warrants being the basis for an article in a technology newsletter that purports to be both objective and impartial. Well, either you’ll have to take my word for it, or you’re going to have to track Jeff Jussel down and have him walk you through those slides in person - or, you could read the article. No matter which way, however, I’m telling you the slides are plain long nifty and they provide a great starting point for a point/counterpoint discussion of ESL and All That Jazz.

Happy New Year to everyone here in the EDA Nation. I sense a strong undercurrent of optimism in the industry at the outset of the year, and I believe the next 12 months offer a lot of promise for the folks who work here. Now, if we could just get the rest of the world to follow suit…

Peggy Aycinena
January 2005

February and March are busy months for those who like to attend technical conferences - especially if you like conferences in Silicon Valley. Of course, the semiconductor industry spans all geographies on the globe, so only looking at things from a vantage point in Silicon Valley can be highly misleading. Nonetheless, people continue to look to this place for guidance and/or signposts of change and growth in the design automation industry. Hence, this month’s article on DVCon 2005.

DVCon is an intimate gathering of friends and enemies - people who work and compete for design starts, tools customers, and language dominance. It’s held each year around this time, and usually takes place at the DoubleTree Hotel in San Jose, CA. This year’s 3-day meeting was a good, solid gathering of the tribes - and although there were moments of rancor, in general, things went smoothly. Companies may be arch competitors, but on an individual basis - engineers and technologists have an easy way amongst each other, which lends a certain ambiance to meetings like DVCon.

I attended a number of different events at DVCon, but missed many other events of equal importance. This article details one keynote and two panels that pretty much define today what’s happening - for better or worse - within EDA. Mentor Graphics CEO Wally Rhines gave a well-received keynote address on Tuesday morning, February 8th. EDA Editor Gabe Moretti moderated a panel on Quality in Design on February 9th, in the early afternoon. And Dataquest’s Gary Smith moderated a panel on Catching up in ESL to close out the conference late that same afternoon.

Of course, DVCon showcased a lot more content that just these three items, but if you need to see the whole conference, it’ll be on-line starting February 23rd, on the DVCon website. All told, DVCon manages to portray a pretty detailed picture of where things are in hardware design. These days, that picture includes compelling evidence that a) things are inexorably moving up to higher levels of abstraction, b) verification technology is undergoing a marked consolidation, and c) achieving quality designs is not getting any easier.

I enjoyed my several days at DVCon. I learned a lot and believe that knowledge will be an asset as I head off to DATE in Munich next month. Across the paradigms of hardware/software, RTL/ESL, North America/ Europe, and global/local design & implementation - the interface between DVCon and DATE offers up a point/counterpoint that mirrors the situation in chip design today, here half way through the first decade of the new Millenium.

Peggy Aycinena
Editor

Can you believe it? The second quarter of 2005 is already at hand. Where did the first quarter go? More importantly, was technical progress made in its passing? Hopefully, if the number of conferences which convene worldwide in the first quarter of each calendar year is any indication, the answer to that question is: Yes. Technical progress has been made – even over the course of these past 90 days – and you, yourself, probably contributed to that progress.

Of the many first quarter conferences of note each year, DATE – the Design Automation and Test in Europe Conference – is one of them. Some 4000+ people were on hand in Munich for DATE 2005 in March, and some of the very hot topics under discussion there included DFM and ESL – Design for Manufacturing and Electronic System Level Design. Next month here in EDA Nation, we'll talk more about DFM. This month, the conversation is about ESL.

There are lots of questions swirling around ESL – Is it here? If so, what is it? Who's doing it? And who's buying the tools that fall into that category?

But ESL is more than an assemblage of questions. It's more like a state of mind. So from an EDA perspective, the better question might be – Which companies have, or are about to, assume the ESL State of Mind?

If his high-profile appearances at DATE in Munich are any indication – he moderated 3 different panels at the conference – Dataquest's Gary Smith may have the answers to some of these questions. Hence the conversation included in this month's article in EDA Nation starts, to a certain extent, with Gary Smith and continues from there.

By the way, when I say this article is a conversation, I really mean a conversation. There are 10 companies and an industry analyst chiming in here, and that makes for a pretty darn interesting read. As is often the tradition here, however, the conversation is long.

So before getting started, go get that requisite cup of java. You're going to want to stay alert through the whole thing because if you do, you'll be a better conversationalist yourself going forward. That is, if you're interested in ESL, its nuances, and the role it's playing today and tomorrow in electronic design.

Peggy Aycinena
Editor

Chapter 3—Rajeev Madhavan

"Fathers and Sons"

Chapter 1—Evolution and Revolution

Everything and nothing changes from generation to generation. We don't need great Russian novelists to tell us that. Fathers more often than not represent the status quo, whereas children, or their friends, more often than not represent change. What is it about the newer generation that it's always so anxious to pursue change? Is it change merely for change's sake, or is it because the ways of the fathers have become tired and staid, the world has moved on and the old ways no longer apply?

For some, these are the questions that haunt the EDA industry today. And the questions are more than just academic. A lot of money is riding on the answers. EDA investors, EDA shareholders, EDA executives, EDA junior executives, the rest of the EDA staff, EDA analysts, journalists, and—last but not least—users of EDA tools, all await resolution: Is it change for the sake of change or are the ways of the fathers too tired and staid to apply to the brave new world we live in?

I think these were the issues I was trying to unearth in several conversations on Monday, July 26th. First I had a marvelous chat with the ever-engaging Wally Rhines, CEO at Mentor Graphics Corp. Following that, I had an equally stimulating conversation with the ever-energetic Rajeev Madhavan, President and CEO at Magma Design Automation.

Mentor Graphics was founded in 1981. Today, Mentor has 3700 employees and most recently reported $670 million in annual revenues. Magma was founded in 1997. Today, Magma has 530 employees and is reporting something in the order of $150 million in annual revenues. Both Magma and Mentor are publicly traded.

Chapter 2—Wally Rhines

Q — New technologies are emerging—FPGAs, structured ASICs, ESL—how does Mentor position itself in new markets while still protecting established markets?

Wally — "Of necessity, Mentor does actually develop products internally for new markets. [Because] we are less well established than our leading competitors, we need to pursue new opportunities and take advantage of new markets. The only way an EDA company can grow is with new applications, new methodologies, and new customer bases—or totally new markets. And, we need to grow in order to generate satisfactory profitability for our shareholders and to provide benefits to new users."

"In FPGAs, we're the only major EDA company who has made a substantial investment in this area. Marketing and supporting FPGA products requires a different kind of selling channel and marketing approach. You need to be able to make money on the sub-$10,000 sales, [and we can do that because] Mentor has two distinct sales channels. One is a direct channel where Mentor employees make the sales call, and one is the indirect channel where specialists and resellers of Mentor tools make the sales call—third parties who are willing to call on the small companies."

"When we acquired Model Technology [in 1994], the economics of their technology allowed us to be able to approach the smaller markets. ModelSim built up a worldwide channel of sales reps for us—highly skilled distributors—and we've built upon that. So now we have about a quarter of our revenue going through that sales channel and we've augmented it [to approach] the FPGA market."

"In the structured ASICs market, we support those customers with platform-based design tools. There's a class of ASICs that's basically a fixed-base set of functions, where you customize three-to-eight layers of metal. That device can also be referred to as a platform ASIC. We haven't done what Synplicity has done [to approach the structured ASIC market], but we have done tools for platform-based design."

"Now, it's true you can distinguish between structured ASICs and platform ASICs—but at the same time, there are probably 10 other categories as well within this technology. Some approaches have FPGAs in standard products; others have standard products in FPGAs. Or you have people generating new architectures for programmability, or reducing programmability in existing architectures. Whenever you see these kinds of things happening, it means the providers and the customers are searching."

"That's when EDA companies are faced with two approaches. The first is to be engaged in the market, to have strong positions in FPGAs, for instance, or in synthesis, or simulation, or analysis. To see what's working and to introduce new products to support it. That's the way products are best defined—you have something to offer and you interact with customers to have them help you figure out how to make it better."

"The other approach is to wait and see how things sort themselves out in the marketplace, and then go out and acquire the winner. This second approach hasn't been a good one for Mentor. Am I bragging or complaining? A little of both. If I had a 10x market cap, I might rely more heavily on acquisitions, but I don't. Our discipline at Mentor is geared more towards product development."

"As far as ESL is concerned, you should check with Dataquest. I believe their numbers indicate that we're pretty well established as number one in that space. Our major competitors have made a lot of moves in that area, but ESL requires you to move above the HDL basis of design. We're definitely doing that. We're providing verification with software and hardware—we've been quite successful in that market for 6 or 7 years—and we're also providing products for C-based design. ESL is definitely [a reality at Mentor]."

Q — How do you sell the tools? To management or to engineering?

Wally — "We have to do both, although whether you're selling bottom up or top down depends on the different cultures within the customers and the different economic cycles, which have a strong influence [on the process]. Traditionally, Asian and European companies have exerted more high-level management decisions with regards to purchasing EDA tools. The U.S. has always tended to be a more bottom-up culture, except with the caveat of where interoperability has forced higher levels of decision making."

"With the downturn in 2002, some of the larger companies became sufficiently troubled that financial controls started to override engineering judgement. Contracts were not renewed or were re-negotiated without paying attention to the engineering viability of the products. It was clearly a penny wise and pound-foolish mentality. As customers become less price sensitive, however, they can again make decisions based on the technical capability and advantages of the tools they're buying."

Q — Power and signal integrity are the agonies that accompany the ecstasies of 65 nanometers. Why don't we just stop at 90 nanometers, resolve the outstanding problems there, and leave well enough alone? Does it make good business sense to be pushing the envelope?

Wally — "Let me give the Edmund Hillary answer … because it's there. Leading-edge technology tends to pay the bills in the EDA industry. If you look at who buys the most expensive EDA tools, who adopts the new methodologies, it has historically been those who have pushed the frontiers of integrated circuits. They may be a minority, but they include companies like Intel and TI. These days, those types of companies don't believe they have the choice to make their own tools. There's such an economy of scale in solving [CAD tool] problems for next generation technology, that companies like Intel and TI can't afford the development costs. As an EDA company, Mentor is solving problems where we're listening to the inputs of many diverse users of our technology. We solve problems that the single user hasn't anticipated as yet."

"This is a phenomenon that you'll see in more industries than just EDA. Cirrus Logic, for instance, used to give this presentation describing how—for every generation of disk controller—Seagate Technology would develop their own disk controller, but would also engage Cirrus to develop [a competing design]. For seven generations in a row, Seagate chose the external solution. That's because internal design groups develop solutions for the next generation, but don't anticipate a generalized solution."

"It's been the same for the evolution of the EDA and the semiconductor industries. Having you own team develop tools in-house is very expensive. EDA companies are able to solve custom design problems with generic design solutions. This is a law of economics that's unlikely to change."

Q — Wally, would you rather be working at a start-up where there's free soda and popcorn?

Wally — "Actually I went straight from my Ph.D. at Stanford to 21 years at Texas Instruments, so I've never actually been in a start-up. Although, Mentor does offer free coffee and free popcorn. We have always tried to preserve some of the things that are associated with start-ups. We have a putting green for employees, an exercise facility, and on certain days you can get a hair cut or a massage at the office. We also provide a very fine child development center."

"But none of this is why people work at Mentor. People are primarily looking for the opportunity in their work to do things that are unique and challenging. The software industry has always allowed people to make a difference in technology. That's why people work at Mentor."

"Why don't I go to a start-up? Well, by definition I would rather be working where I am. I have had plenty of opportunities to do other things—lots of opportunities, for instance, to go back to managing semiconductor companies. But, I don't feel a strong temptation to do that. The kind of thing I do at Mentor is my creative outlet, because we do act like a start-up."

"I am aware in all of this that once you become a large company, it takes an enormous amount of effort just to stay even. But we're still a young company and we're continuing to grow in several markets, mostly by taking market share from our competitors. When a company has good cash flow and good earnings, it should let its investors put their money into growth opportunities [available to the company]. Of course, when opportunities are not plentiful, just as Microsoft is currently doing, that cash should be returned to the shareholders."

Q — The Big Guys in EDA are accused of a) inhibiting innovation to protect legacy markets, b) inhibiting innovation by buying small companies and letting those technologies wither, and c) inhibiting innovation by only partnering with big customers. Do the accusations become tiresome and annoying for Mentor Graphics? Is it the tolerable price of success to always be the target of broad-brush criticism?

Wally — "I think it is the price of success that there will always be critics. [That's exacerbated by the fact that] people tend to broad brush groups into the same buckets, companies are placed into generic categories. There is validity in the criticism that large companies are guilty of not developing technology internally, and only grow through acquisitions. But how many de facto industry standards are developed by start-ups? Usually, they're developed after the company has reached [a certain size]."

"Calibre from Mentor Graphics is certainly the de facto industry standard for physical verification—it's one of a half dozen products that are now industry standards that were developed after Mentor became a large company. And certainly, the same thing is true of PrimeTime at Synopsys as far as being a de facto standard that emerged from a large company."

"[In the end], it's a question of what process a company finds to be the most efficient for developing technology. If waiting, watching, and acquiring technology is a [way to establish] leadership, companies should do so and accept the criticism."

"For Mentor, however, we don't have that luxury. It's true that in the early 90's, we had fallen way behind and had to jump start our internal development by doing quite a few acquisitions. But historically, Mentor has always been a product development company, and I made the decision when I came to Mentor from Texas Instruments in the early 90's that we would be much less open to acquisitions."

"I believed and still do, that once you have the culture [for internal development] that Mentor always had, the company has to take advantage of the development skills it has in-house. Today, Mentor is 5-to-10 times the size of our next largest competitor, but even as a big company, we've been able to preserve our ability to innovate. I know we would be able to preserve that ability even if we were to grow to twice or three times our present size. Why? Because you always dance with the girl you brought to the party!"

Q — Rajeev, I'm often hearing Magma referred to these days as one of the "Big Guys" in EDA. Is that affecting your business or technology initiatives? Was it more fun when Magma wasn't so much on the radar?

Rajeev — "Actually, from the very first product launch, we've been on the radar. That hasn't changed in any way, shape, or form. There are two big EDA companies who like to see us make mistakes—we're up against two Goliaths—and a third who sits on the fence and congratulates the other two. Since the early days, it has always been about bashing Magma."

"But also from the very beginning—if John Cooley or anybody else attacked us on things that were wrong with our products, we've always gone after fixing those issues and correcting them. That's just one of the things that we've needed to do to succeed. We're [almost a] 600-person company with very small carpets. It's not easy to sweep things under the rug here. As long as we feel the pressure, it's extremely good for Magma and we'll continue to develop really excellent technology. From a business point of view, that's actually our only option."

"And of course, we need to continue to win benchmarks. We need more people to do that. We have over 90 openings right now—we're continuously trying to bring in good people, but the fact is that it's difficult. We're looking for people with specific experience in various areas of work, particularly in research, and often with Ph.D's. People who have lots of publications are the ones getting noticed and often getting hired."

"But in any case, I'm actually happy that the other big three vendors continue to describe us as a start-up. Our technology is simply better. Perhaps that's what makes us a start-up. We're a start-up with over 500 people and run rates of $150 million this year! Do we still give out free soda like a start-up? Yes, in that way it's still very much a start-up mentality here!"

"It was more fun before in one area, however, I will say. Today suddenly, we have issues of globalization and [responsibilities] as a growing financial organization because of things like Sarbannes-Oxley. You get the idea that corporations now are needing to spend money on all of this because of the failure of Enron and WorldCom—and as a company we're having to do even more. We've always done what we had to do to provide complete reporting, even before [all of these regulations]. Nonetheless today the reporting requirements are [very costly to implement]."

Q — Is it still easy to communicate among people and groups at Magma, like it's always rumored to be in a start-up?

Rajeev — "We want to retain open communication in the company as much as possible. We enforce this notion quite a bit at meetings and so forth. However, it's always a problem to keep people candid as a company grows. So on a quarterly basis, we call everyone together and we beat each other up. In fact, we did a restructuring about a quarter ago. We divided the company into four groups, so we could continue to be brutally honest with each other."

"The four new groups include physical verification, design for manufacturing, front-end design, and IC implementation—with R&D shared across the four groups. Now the onus is on the head of each of those groups to make sure we understand the customer requirements in these areas and [to be honest and to speak openly with the senior management at Magma]. All of this is important for scaling the company, both on the technology side and the business side. We haven't reached the point [where people are afraid to share the truth with the management]. In fact, if we ever reach that point—well, we just won't!"

"I'm not saying that every one fits into the culture here at Magma, but as long as I'm here, I won't have it any other way. People must be free to be honest. Greg Walker, Roy Jewell, Saeid Ghafouri, Venktesh Shukla, and I—everyone except for Hamid Savoj—have been CEOs in the past. We all understand the need for open discussion here. When you have four or five people in an organization that have the proven skills to be at the helm at any given point in time, that's a very powerful position to be in."

Q — Quite candidly, and considering the current global economic picture, would Magma ever consider re-locating corporate headquarters to India?

Rajeev — "That would be impossible. The application knowledge is here. No doubt, there will be a growing number of customers in India, but it will be a long time before India or any other place in the world can reach what Silicon Valley has to offer. I owe a lot to Silicon Valley and this is where Magma belongs."

"There are entrepreneurs who come to me with that kind of model—starting an EDA company in India. But the skillsets [available there] are nowhere near what we need, even in generic software, let alone EDA. Culturally as well, there's no expertise in India for building start-ups. Maybe there will be 10 to 15 years from now. Right now here in North America, we're so inwardly bound and worried about losing jobs in the short term—we're making this a bigger issue than it needs to be. Instead, we should be trying to build businesses. We should be creating business leaders, not fighting a global economy."

Q — How does Magma position itself in new markets while still protecting established markets?

Rajeev — "At this stage in Magma, I spend quite a bit of my personal time on these questions. As a company, we're driven by two things. First of all, we have an extremely good relationship with our customers. A few of them are always doing cutting-edge designs and they give us ideas of where the industry is going. In the old days, [innovation in EDA] was driven by entrepreneurial hunches. That was the driving force. Today, it's what the customers have to say that drives us."

"The second thing is that we're pretty much an entrepreneurial friendly company. If you came to us and told us that you had a technology that was 10x faster, for instance, than the existing simulation technology—we would be interested. We're game to attack each and every opportunity in the various markets."

"With respect to the specific markets you mentioned, FGPAs and structured ASICs—we started a dialog 14 or 15 months ago and then bought Aplus Design Technologies. We made [this move into] the structured ASIC market even before it was being used as a word. People were telling us that SoC design was going to be platform-based and would include standard cells, FPGAs, etc. We saw that the fabric was being put into place [for that style of design]. So we made the strategic investment in Aplus, and looking at the last two quarters, we believe we're now number one in structured ASICs."

"Now, it's not our place to tell our customers, 'Thou shalt use structured ASICs, or standard cells, or FPGAs.' It's up to our customers to determine for themselves how to mix and match these technologies. But we have a very strong technical team and, unlike everybody else who say they have a structured ASIC flow, we actually have one."

"So, we have three types of acquisitions. There's the acquisition aimed at basic raw technology like the Aplus deal. In that instance, we're not buying the company for the source code, but for its experience. We then implement their talent into our flow development team."

"The second type of acquisition is in the category of infrastructure—acquiring libraries, for instance, to make sure that data is available so that tools from Magma, Cadence, and Synopsys can be used very quickly."

"The third bracket of acquisition is related to what I call revolutionary or world-shattering technology. For instance, Mojave came to us with very impressive technology and an excellent team. It was clear that what they were putting together was really revolutionary. That has been the first and only acquisition we've done in this category, but it shows that Magma is willing to play in each of these areas. This third type of acquisition is the most forward-looking. It is not so much driven by what the customers demand as by an incredible technology."

"Cadence likes to buy technology that's already up and running. We prefer to do it in the early stages of a company. For us, it's the whole package. Meanwhile, of course, we still think we have a culture at Magma where we can get new tools out."

"Most EDA companies have had one success and then go and buy everything else. We're certainly going to do what's necessary [in the area of acquisitions], but we're also doing a lot of new things. A software company can't grow purely through mergers and acquisitions. If you think it's difficult [to integrate designs] in hardware, it's even more difficult in software. And EDA software is much more complicated than most software. And from the cultural side of an acquisition, it's even worse [trying to merge companies]. How do we in EDA think we can build a cohesive culture within a software company by just slapping things and organizations together?"

Q — Power and signal integrity are the agonies that accompany the ecstasies of 65 nanometers. Why don't we just stop at 90 nanometers resolve the outstanding problems there, and leave well enough alone? Does it make good business sense to be pushing the envelope?

Rajeev — "We have done lots and lots of designs at 90 nanometers, and 65 nanometers is already here. In our view, by the time we announce our October/November releases of our tools, we will be completely done with 90 nanometers. That doesn't mean there won't be more work to do, but fundamentally we've done lots of chips at 90 nanometers. We know about the noise, the routing—the entire process is pretty much done. Power was a great learning experience for Magma, and our solutions were pretty much customer driven."

"Sometime between now and February, we're going to put a public face on a number of different things. We'll be getting a series of launches out the door, and will have more announcement and releases between now and January/February 2004 than we had in the entire history of the company. Just [having the bandwidth] to be able to communicate all of those developments to Wall Street and to EETimes is quite a challenge of its own."

"In all of this, I'm not saying that at 65 nanometers there won't be any issues. Clearly at 65 nanometers, yield is going to be an issue—we've already announced partnership with PDF Solutions to address these things. But as a start-up that's going up against two Goliaths—simply put, we're at a confidence level such that in our guts we believe we'll meet the expectations placed on us to deliver [solutions at] 65 nanometers. Although we're not going to talk about it until it's here, there's no use shying away from it. We have the confidence to deliver!"

The Epilogue—with apologies to Turgenev and Hemingway

The four of them stepped down off the stage where they had been sharing the limelight. The Sage One turned quietly to the Upstart. "You don't know the leaders in this industry well enough," he murmured. "You find fault with their point of view, but what makes you think it's not a product of the very technology that you're championing?"

"The leaders are good fellows," said the Upstart, "but their day is over. Their song has been sung to extinction. We have to move on. I can see we have to move on."

The men, whose day was over, stood nearby and listened for a minute or two, then quietly returned to their offices. One rang the other on a private line. "So it seems that you and I are behind the times. Our day is over," one said to the other.

The other responded impatiently, "In what way is he so different from us? And how on earth has he gone forward? It's those venture capitalists and analysts who have knocked such ideas into his head. I'm sure that in spite of all his staff and investments, he knows precious little about this industry."

The first one said, "No, brother, you mustn't say that. He's clever and he knows his subject."

"And so disagreeably conceited," the second one continued.

"Yes," observed the first. "He is conceited. Evidently one can't manage without it, and that's what we've failed to take into account. We thought we were doing everything to keep up with the times. We studied the designs. We tried to run model companies. We ourselves have even been described as rebels at times. We've read. We've listened. We've tried in every way to keep abreast of the demands of the day. Yet some say our day is over. I, however, continue to think it's barely begun."

"Exactly!" the second one replied. "Our day has barely begun!"

The conversation ended and the first one leaned back in his chair. He looked out his window and saw the highway that rose and fell past the last house in the distance. The banks of red dirt on either side of the road were sliced cleanly away and the second-growth timber stood on both sides. Their branches moved in the breeze. A storm was brewing.

"John Sanguinetti - A Profile"

Prologue - The trombone

This article is the result of several conversations that I had with John Sanguinetti over the course of a week in August 2004, during which he talked about his lengthy career and the many observations and conclusions he has drawn from his complex experiences. Our conversation concluded with a discussion of his diagnosis and treatment for Multiple Myeloma.

John Sanguinetti was born and raised in Maryland, where he began to play the trombone early on. That fact ended up having a lasting impact in EDA because in choosing a college, John looked for a school with a great college band and a spectacular music program. That turned out to be the University of Michigan, a place that John discovered also had a pretty good engineering program as well.

John spent 4 years in the Michigan marching band - even today he goes back now and then to attend football games - but he left the trombone behind during his graduate school years. Today however, John’s an active participant in the Peninsula Symphony Orchestra where he’s been a member of the brass section for over 20 years.

Chapter 1 - 1966 to 1977

My intention was to only spend 4 years in Ann Arbor and then to move on, but it didn’t work out that way. After I got my BSE in Applied Math, I applied to some of the top schools in Computer Science for graduate school. I got into Berkeley and Michigan among other places, but chose Michigan because they promised the doctorate would only take me 3 years - Berkeley promised 4 years. As it turned out, it ended up taking me 7 years at Michigan.

During those 7 years, I spent a lot of time working at the Computer Center on the Michigan campus, and it was there that I developed an interest in operating systems and design methodologies. I subscribed to top-down design philosophies and discovered there had only been a handful of operating system design projects reported up until then done in that style. That was back in the late 1960’s and early 1970’s, and operating systems were not as complicated as they are today. The hardware was much simpler and operating system design methodology was simpler as well.

My advisor at Michigan had come up with a formal modeling language for systems that could handle concurrent processes. Essentially, the language was an extension of regular expressions to determine if things would deadlock given certain circumstances. My thesis work entailed adding some features to the language, so that you could predict the performance of the operating system.

My scheme produced a sequence of messages that could be instrumented to determine in advance how long it would take to get from one state to another - it was kind of esoteric. Along the way, I wrote a compiler and a simulation run time library for this language, which was in essence a process-oriented simulation language. Overall, my graduate research work ended up accomplishing its objective - I got my degree, but it wasn’t terribly significant, or so I thought at the time. I was convinced that there would never be any practical application for my work.

Chapter 2 - 1977 to 1982

So I ended up staying for 11 years at Michigan and at the end of that time, I had a Ph.D. and a wife - not necessarily in that order. As I was finishing up my Ph.D., my wife was finishing medical school at Wayne State in Detroit. Following on that, she accepted an internship in Boston and I accepted a job working for DEC [Digital Equipment Corp.] on Route 128 outside of Boston. I arrived at DEC just a few months before the company’s first VAX shipped in September 1977. My job at DEC was to do performance analysis for them, primarily on their existing PDP-11 product line.

In one instance, the company was going to build an algorithm into the controller to optimize disk head movement, but my simulation model, in Simula, showed that effort was unnecessary. That work was significant because it would have cost them about half a million dollars at the time to do that controller. In any case, nobody at DEC really thought of me as a software guy. I was doing a lot of formal analysis about head seeking and was closely associated with the hardware guys in the company. That was my first close association with hardware designers.

Two years after we arrived in Boston, my wife finished her internship at Tufts in Boston, I left DEC, and we went back to Detroit where she did her residency in Ob-gyn. I returned to the university and took a job in the Computing Center in Ann Arbor, and that’s where we stayed for the next three years.

Chapter 3 - 1982 to 1986

My wife and I had made a deal after moving back to Michigan from Boston, that the next time we moved it would be my turn to decide where we landed. At that time, I had just read a paper in Computing Surveys by Mac MacDougal at Amdahl, who was one of the first people to do extensive simulation of computing systems at Control Data. Mac had gone to Amdahl in the mid 1970’s and was somebody I felt I could really learn from.

So after my wife finished her residency, we came to California and my wife set up one of the first all-women-doctor Ob-gyn practices in the Bay Area. Things have really changed since then - more than half of the OB-Gyns in the Bay Area are women today - but there were very few in 1982.

I started at Amdahl and began by doing performance analysis once again, trying to determine how fast the new machine would go - working usually in conjunction with the architecture group at the company. At Amdahl, performance was everything, and of course things had to be completely IBM 370 compatible. Incidentally, in those days, PC meant “Plug Compatible.”

Nobody was going to buy an Amdahl machine unless it was faster than an IBM. My group was creating benchmarks that were representative of customer workloads - it was before there were standard benchmarks in the industry - and analyzing the results.

Those were pretty heady times and the group that I was in was really quite good. Amazingly enough, some of the people in that group ended up staying at Amdahl for 20 years - even after the company became Fujitsu - but I only stayed for 2 years.

When I got to Amdahl in 1982, Silicon Valley was buzzing with talk of start-up companies. It was just after the first IBM PC had been announced and everybody and his brother were making an ‘almost-compatible’ PC. That was before the BIOS was cloned, making true compatible machines possible. I made some good friends at Amdahl, including one who was leaving to join a start-up. I had no idea how to go about it, but I wanted to join a start-up as well.

It was at that time in 1983 that I joined the Peninsula Symphony Orchestra as a trombone player. There was another trombone player in the brass section named Jim Jaffe, who was one of 8 founders of a company called Elxsi. Other founders included Joe Rizzi, who later became a partner at Matrix, and Thampy Thomas who went on to found NextGen after Elxsi.

Elxsi was making a super minicomputer to compete with the VAX from DEC and had about 300 employees. Unfortunately, although it looked like a start-up to me, it really wasn’t - it had been going for five years. The company was in that stage of having to do market development and getting product out into the hands of customers and it wasn’t succeeding. It was a zombie - not really alive, but not dead either.

In any case, I joined Elxsi and essentially did the same thing I had been doing at Amdahl. Eventually, I ended up doing both performance analysis and architecture at the company. Over time, however, I realized that Elxsi was a failed start-up and so I left after only 2 years - but not before I saw the folly of having a company name that nobody could pronounce or spell.

Chapter 4 - 1986 to 1990

In 1986, a headhunter told me about The Dana Group, which eventually became Ardent Computer, and then Stardent Computer - a company that was going to make a mini-supercomputer. In the mid 1980’s, this machine would target 8 megaflops on Linpack and a few hundred thousand triangles-per-second graphics performance. It would have computational processing applications and use a graphics subsystem to draw the results. Using the Ardent computer as a graphics supercomputer that rendered locally, meant you wouldn’t need to buy a Cray to get that kind of compute power and you didn’t need to buy an SGI workstation to render the results.

Even though Ardent didn’t last, it was a really heady experience to be involved with a real start-up of that size. I was the 24th employee to join the company and it was completely different from anything else I’d done up to that point.

While at Ardent, I did some modeling of the bus protocols to get the throughput we needed. Then, after just two months, they started parceling out the tasks involved in product development - designing the interface chip, the memory chips, the vector unit chips, etc. They asked me what I was going to do, and I said, “Well, what do you need me to do?” They said they needed design verification and I accepted the task.

My first job was to select the language. At the time it was Endot versus Verilog - VHDL wasn’t on the market. I did an evaluation of the two languages and chose Verilog because I liked it better. I knew we would need to write a translator from the netlists in the Valid format - Daisy, Mentor, and Valid were up and running in those days - and that’s how I got into design verification. I wrote behavioral models of the whole system - we could run an entire system simulation with my models.

I consulted the spec and the design engineers to write the behavioral models before we plugged in the netlist models. It was top-down design the hard way. At the time, people at Gateway told me that we were doing more sophisticated and complete modeling than any of their other customers even though the entire effort at Ardent consisted of just a couple of other guys and me. I never did know if they told that to all of their customers or not. That was in 1986 and ‘87.

The whole process was very interesting for me because it was starting to look remarkably similar to the software design methodology I had worked on in my dissertation back at Michigan. I knew that over the years that method had never gone anywhere in the software world, that people had talked about top-down design for software systems, but it had never really worked. However, here we were at Ardent doing exactly that with hardware design. In fact, Verilog was just a process-oriented simulation language, not all that different fundamentally from the language I had used in my dissertation.

I was writing a lot of Verilog in those days - we were all working on Sun workstations at that time. When we got our own machine working, anything that had been ported onto a MIPS platform, including VerilogXL, could be run on our machine. We were running other tools as well, of course.

Synopsys had come out in 1988, and we started to use Design Compiler. We got a beta of the product from Synopsys on a 1/4-inch tape. I just stuck it into the machine and ran it a couple of times. I wasn’t a hardware designer, so I didn’t actually use it, but I did install it and told everyone where it was on the system.

The excitement about Design Compiler was pretty high. Our group accepted it right away and was quite confident that it was the right thing to do. Like a lot of people, we knew that Design Compiler was a significant product. It was exciting to see that top-down design methodology for hardware was becoming a reality with a translation tool that could go from RTL to a netlist in a way that didn’t have to be done by hand.

Meanwhile, even beyond the technology, my experience at Ardent was really a life-changing one. I went from working 40 hours per week at Elxsi, to working 60-to-70 hours per week at Ardent. When I had interviewed at Ardent in 1986, my wife was on call with her Ob-gyn practice every other night and every other weekend. We had a 6-year-old at the time and I had to be at home with her when my wife was at the hospital.

So I told the Ardent guys during my initial interview that I couldn’t work on Saturdays. They grumbled a bit, but agreed. The first week I was at the company, Ben Wegbreit, the engineering VP, asked me to come in on Saturday just to show him what I’d been doing. So I did and I brought my daughter in with me. When I got there and looked around, absolutely everybody else was there working. I was amazed.

The next Saturday, I ended up coming in again, and as it worked out, I was there for 44 out of the next 52 Saturdays. A lot of that time, my wife was busy at the hospital delivering babies, so my daughter spent a lot of time at work with me. The whole thing was a complete culture shock to me.

People really worked hard at Ardent - Gordon Bell was there, Allen Michels was CEO, Ben Wegbreit was VP of engineering, and Jon Rubinstein was chief engineer. Richard Lowenthal, one of the best engineering managers I’ve ever met, was recently mayor of Cupertino. Steve Johnson who had written the Portable C Compiler at Bell Labs was there, as well. And Steve Blank, one of the most creative guys in the Valley, was VP of marketing.

We had a collection of extremely high-powered people at Ardent, all working 70 hours a week or more. Despite that, however, the company utterly failed. The machine was too complicated and too expensive. It was clear by 1989 that Ardent wasn’t going to make it, and when that situation became obvious, it was a downer for everybody.

From Ardent, I went to NeXT along with Jon Rubinstein even though I knew it wasn’t the place I ultimately wanted to be. The NeXT operating system was really nice (it turned into Mac OS X) and the machine was okay, but the company had 400 people, which was the wrong direction for me.

By then, I had figured out that over the course of my career, each company I had joined was an order of magnitude smaller than the previous one. When I was at DEC, they had 50,000 employees. Amdahl had 4000 employees, Elxsi had 300, and Ardent only had 24. NeXT was going in the wrong direction for me with 400 employees. I’d realized that my next company would have to be just me and one other person.

For that reason alone, I knew it wasn’t going to be a long-term proposition for me at NeXT. I wanted to be in an environment like at Ardent, but at a company even smaller than Ardent. Now I had to figure out how to get there.

Chapter 5 - 1990 to 1993

I was reading EE Times one day in September of 1990, and saw a 2-paragraph article that said a meeting of OVI [Open Verilog International] had been postponed. OVI had been established in May of that year by Cadence in order to put the Verilog specs out in the public domain. Seeing that article was the first I heard of OVI or that Verilog might be made public. Before that, the specs for the language were a Cadence trade secret and it was illegal for anyone else to sell a Verilog simulator.

Within 5 seconds of reading that article, I knew that this was the opportunity I’d been looking for. I’d been using Verilog for 5 years at that point and was really an expert with the language. In addition, I had a very low opinion of Cadence’s simulator, VerilogXL, because it was so slow running the behavioral models I wrote.

I had written a simulator for my dissertation and knew that an interpreter was nearly always 10 times slower than a compiler. I knew this was my opportunity to create a product to compete with VerilogXL. In fact, I felt that anyone with a reasonable education could do a better job of producing a Verilog simulator, but I also knew that if I tried and failed it would be beyond embarrassing. It was time to put up or shut up.

So I spent the next 8 months getting ready to start Chronologic Simulation based on my idea. While I was still working at NeXT, I wrote a prototype simulator at home from 11 PM to 1 AM every night for two months. When I finally got something that worked, I started trying to recruit people to join me in a new company based on the idea.

Through that process, I learned a lot about starting a company. At first we had three guys, but just before we incorporated in May 1991 one dropped out. That left Peter Eichenberger and me, but as far as I was concerned, this was going in exactly the right direction. A company with just two people.

It was just really exciting to start a company. We rented a little office in Los Altos - the office didn’t have any insulation and barely had any heat - and we worked there on our Verilog compiler. We were delighted when it began running and ran models 10 times faster than VerilogXL, sometimes as much as 50 times faster.

All of this was definitely a life-changing experience for me. I became a CEO and we had a product, VCS, all in about 17 months from the start of the project to our first customer ship. I had made a bet that I could make a real product, and had pulled it off. The fact that it was self-funded added to the sense of accomplishment.

At the time, nobody actually believed that Verilog had a future. Everybody thought that VHDL would take over, except the Verilog users. I was a user and I knew full well that nobody using Verilog was going to switch to VHDL unless he had to - Verilog was easier to use and there was no advantage to VHDL.

Still, I can’t tell you how many people told me to make a simulator for VHDL and not for Verilog. Andy Rappaport and Ron Collett both told me that point blank - do it for VHDL instead of Verilog because that’s where the future is.

Anyway, I tried to get advice from everyone that I knew as we started the company. I had lunch with a guy I had known at Ardent who was then a partner at Sequoia Capital. He was very helpful and when I told him about the company, he said I was right, they would never fund something like that. He also told me that they had just funded Redwood Design Automation and that Redwood had told him they’d be doing $100 million worth of revenue in 3 years - that’s how much market potential they had.

Well, by chance, I had an appointment with the VP of engineering from Redwood that very day, right after my lunch with the guy from Sequoia. I drove to San Jose for that appointment and had a nice talk with him. I asked him if he had really told the VC that they’d have revenues of $100 million within 3 years. He said yes, but that in reality they thought it would only be $50 million. When I heard that, I decided to be wary of Redwood Design.

It was such a telling moment to hear of someone giving a VC a number that was double what they actually expected to make. As it turned out, Redwood Design had a number of problems and we always loved to compete with them, because we beat them every time.

In any case, we never tried to get VC funding for Chronologic and so we were entirely self-funded. No one got paid for the first 15 months. But again, with my wife practicing medicine, I was okay. I have always said that my wife was the Chronologic VC.

Over all, we had 5 people at Chronologic who worked for absolutely nothing for a non-trivial amount of time - you really can’t do that anymore - but it paid off in the end because when we finally started making money with the company, we owned all of the equity. I was president and there was never any issue of external investors telling us what to do. As it turned out, that was a mixed blessing. It also gave the founders what I called “moral authority”. We had the right to make decisions about the company because it was our creation. We couldn’t be second-guessed, except by ourselves.

We released our product, VCS, in November 1992 after having had 3 beta customers for the product up to that point and it just took off!

We made $1 million in the first 2 months, paid out in just 5 checks from 5 customers including NeXT, SUN, Supermac, BBN, and Kubota Pacific. Our customers were mostly people that I knew - BBN was the only customer that didn’t have somebody there that we knew. We’d been living on a shoestring for so long that when I went to pay the bills for the company in the first week of January in 1993, the company account was down below $1000. A day later we got a check for $500,000 from Cyrix, and another million and a half arrived in January and February 1993. It was very exciting.

In any case, although we were seeing fairly big sales numbers at the outset, they represented a small number of transactions. So although for the first 4 or 5 months, we were doing pretty well, things then slowed down. We did have a sales guy and then started to build up a sales pipeline, but that took an additional 4 or 5 months to accomplish.

Chapter 6 - 1993

Most of the people that I knew through previous employers were in the design business, so at the beginning of Chronologic I was pretty naïve about the EDA industry. That situation turned out to play a big role in what happened next. As I didn’t have many contacts in EDA, I decided to join the OVI board of directors in mid 1993 - after being active on one of the technology committees of the organization, something I had done just to keep an eye on things.

However, I didn’t run for the board until I was absolutely certain I would be elected. There were usually the same number of board seats, or sometimes one less, as there were companies paying the full membership. Board members were determined by an election. There was a certain element of “popularity contest” in these elections, so there were people who would have been good to have on the board who were never elected, though this happened rarely. That’s probably the same in most organizations.

So in 1993, when I was confident of the outcome, I wrote a check to OVI for $10,000 and made an election speech - probably the first one ever given at OVI. Previously, OVI had made politically correct statements to the effect that Verilog was not in a language war with VHDL. Each language had its own place in the scheme of things. However, I got up and said I didn’t believe any of that. Verilog was superior, there was a language war going on, and I was on the Verilog side. After the election, Venk Shukla said, “It’s good to have a real Verilog bigot on the board.” I wore that title proudly.

Nonetheless, virtually all the analysts were still saying VHDL was it, that Verilog would die out. They were still sure that everyone would be switching over. I couldn’t convince anyone that it wasn’t going to happen, and they just kept asking me what I was going to do with VCS when VHDL dominated.

I had a particularly memorable interview with Gisela Wilson of IDC - who told me flat out that she didn’t believe our efforts had any future whatsoever. “You’re selling a fast Verilog simulator,” she told me. “But if all you have is speed what are you going to do when Cadence catches up?” I told her that I didn’t think Cadence would catch up. She wasn’t impressed.

In any case, by June of 1993 we had a repeatable sales cycle and we went to our first DAC. When you’re a company of 13 people, everybody goes to DAC and it was an exciting time.

DAC was in Dallas that year. When we got there and looked around, we saw for the first time that we really had a company and should start acting like one - not like an engineering group. The Chronologic board at that time consisted of Peter, Gordon Bell, and me - we had all met at Ardent. I talked to Gordon after DAC and he said we definitely needed some business help to grow the company.

So I called Allen Michels, the former CEO at Ardent, and asked him if he would be interested in being on my board. He said he’d come up from Phoenix and see what he thought about the company. He visited us for a day in Los Altos, and told me that the first thing we needed was a VP of sales. So we brought in a candidate to interview.

After the interview, Allen told me not to hire that guy, but to hire him. When I got over the shock, I made Allen COO for Chronologic, and while I still managed product development, marketing, and administration, Allen managed the sales people. I’d already hired Simon Davidmann to handle our European sales and we had a distributor in Taiwan and Israel, though not Japan. When Allen joined Chronologic in August 1993, he hired a sales guy in Massachusetts and two more in Silicon Valley.

He also hired a marketing director, Lisa Schmidt, signed up a Japanese distributor, and overall brought discipline to the sales process. Of course, given that it was Allen, it wasn’t a whole lot of discipline, but Allen knows how to handle people and how to handle a sales organization. By the end of 1993, we had about $5 million in sales, almost $2 million in the last quarter alone.

Still there were people who were sure that Verilog was going to fall into disuse - people like Dataquest and others who were doing surveys and talking to the management of EDA companies. But when we talked to the engineers directly, they didn’t say they were going to switch to VHDL at all. So even though we didn’t get much respect from the industry, the Chronologic business was doing just fine. VCS really was 10x faster than VerilogXL and 20x faster than the fastest VHDL simulator on the market.

Joe Costello was head of Cadence when Chronologic announced our first product. People thought that Cadence would respond by speeding up their own product, which of course they did. I actually went to a Cadence shareholder meeting after mailing a poster-sized copy of our first VCS ad to Joe Costello and went up to him afterwards to introduce myself. He was pretty cordial although he definitely knew about my product. He said the poster would be good motivation for his engineers. That’s something I doubt I would ever do again.

Lucio Lanza was on the board of Cadence at the time, and he told me later that he had recommended that Cadence acquire Chronologic. I didn’t believe the industry would have allowed them to, in reality, because it would have convinced everybody that Verilog wasn’t really an open language. That would have had the affect of Cadence being the only vendor with a Verilog simulator. I personally felt that we would always be competing with Cadence.

Chapter 7 - 1994

By the beginning of 1994, we were becoming relatively well known. We had done some advertising and established the fact that VCS was the fastest simulator on the market. That’s when people started believing that we really did have a future. Not only was there no reason to switch to VHDL, now there was a good reason not to leave Verilog.

As an aside, the DOD had mandated the use of VHDL back in the late 1980’s. Europe has always liked to follow standards - particularly back then - so when the DOD declared VHDL to be the standard, Europe pretty much embraced it. Europe was dominated by a few large companies and it was pretty easy for them to make policy for the region and enforce it. Even today, Europe is the last bastion of VHDL use. The same was true in Japan, although to a much lesser extent.

In any case, it took until the IEEE Verilog standard came out in 1995 to say that the tide had really turned in favor of Verilog over VHDL. OVI had launched its standardization process in 1994 and we participated actively in the committee that did the work. That standardization was OVI’s biggest achievement.

People continue to have a misconception about how IEEE standardization actually occurs, believing that it’s some kind of remote process. But that’s not true at all. You get approval to form a standard committee within IEEE and then you go about doing the work. In the mid 90’s, the IEEE 1364 Verilog committee looked just like the OVI language committee, same people but with different rules and the only ones participating were the ones with an interest in the future of Verilog.

For us at Chronologic, we had a vested interest in making sure that the undefined behavior of the language remained undefined. We didn’t want to have any behavior defined in the standard that would limit our implementation options. Race conditions result from a lack of event order specification in the language and typically we were doing those events in a different order in VCS than in VerilogXL. So we spent a lot of effort on what should be defined and what shouldn’t in the IEEE standard. The Cadence people didn’t seem to care - no one from Cadence joined the IEEE committee or regularly attended the meetings. The only real push back we ever got on that committee was from someone who wanted to clone VerilogXL and didn’t understand how you could do things differently from Cadence.

It was becoming apparent by 1994 that a significant change was occurring in the industry, and we started getting feelers about an acquisition. We got a low-ball offer from Synopsys, which we didn’t have any trouble turning down. A month later, we got a better offer from Viewlogic - that one was also not great - and we turned it down as well.

When Allen Michels joined the company, he didn’t know anything about EDA, so he called his brother-in-law, a stockbroker, to do research into the industry. The brother-in-law knew about Cadence, Synopsys, Mentor, Viewlogic, and Quickturn - the public companies. Allen came back to me and said, “EDA is a lousy industry. Each company has its day in the sun and then it’s done. You better make hay while the sun shines. The sun is shining now, so we either need to go public or be sold.”

We felt we were on a roll, but had no guarantee that it would continue. Allen was still hearing from all of the opinion makers that VHDL would overtake Verilog, and thought that within a year there was a good chance we would peak and then decline. So we started the IPO process for Chronologic at the beginning of 1994. We contacted an investment banker, I wrote a prospectus, we consulted with lawyers, and then we started getting the offers. Allen felt at the time that we would probably be acquired before going public. And, he felt that given a choice between going public or selling, getting acquired was the superior option.

In hindsight, had I known more about the industry myself I would have known it’s far better to go public before you get acquired. I can’t blame Allen - his advice was valid for a lot of EDA start-ups. He was an influential guy, but I should have been able to say, “No. Let’s not hurry.”

So we ended up telling Viewlogic we would accept their offer of $25 million in March 1994 and that’s when things got interesting. Later that day, we got a frantic call from Synopsys. We met with them on a Sunday morning and the meeting included about 11 people on the Synopsys side of the table and 3 of us on our side. We told them what Viewlogic had offered and said, “If you offer us $30 million, we’ll accept on the spot.”

It seemed like pure arrogance when they offered us the same $25 million that Viewlogic had offered. Synopsys hadn’t made a lot of acquisitions back then, and they had a reputation for being a day late and a dollar short. The fact that they offered the same amount as Viewlogic was a real problem for us, so we went back to our office, talked it over, and chose Viewlogic.

The deciding factor was that Viewlogic told us that we would continue to be an independent operating subsidiary. We’d remain in our same offices and there’d be no changes. The truth is that Synopsys was more honest with us. They told us that we’d become Synopsys, we’d be moving over to their offices and Chronologic would cease to exist. I felt afterwards that Aart de Geus [Synopsys CEO] had been much more honest with me at the time than Viewlogic was because that’s what actually happens in an acquisition. The acquired company ceases to exist - it’s only a matter of time - but I didn’t know that in 1994.

In any case, we signed a letter of intent with Viewlogic, as well as a ‘no-shop’ agreement. When I told Aart that we had signed with Viewlogic, he still wanted to talk although I couldn’t. A couple of days later Synopsys sent us an offer that was substantially better than their first offer.

My lawyer said to tell Viewlogic that, as a result, the deal with them was off completely - to tell them that’s just how business goes. Instead, when we informed Viewlogic of the situation during a phone call with Alain Hanover, CEO at Viewlogic. His response was to say that he’d sue each of us “personally for every penny you have” if we backed out of the deal.

Remember that at the time, both Gorden Bell and Allen Michels were on the Chronologic board of directors and both of them were really shy of lawsuits, having been through some unpleasant ones. They told me they didn’t want to be involved in any lawsuits, even though I didn’t really think it would come to that and neither did my lawyer. But I wasn’t very adventuresome either, so we decided to just go ahead and go through with the deal with Viewlogic. That, in turn, was the subtext of the next year that I ended up spending at Viewlogic.

You could ask, how often does someone find themselves in the position of starting a company, which becomes dramatically successful, negotiating with various people offering to buy the company, and eventually living through an acquisition? It’s not that unique, but it seldom happens to one person more than once. All told, the aftermath of the acquisition turned out to be the worst experience of my life.

By 1994, Viewlogic wasn’t growing the way they had been growing in the years prior to acquiring Chronologic. They knew that they were topping out, although we didn’t. Meanwhile nobody - including us - could see how great VCS’ growth potential was.

There were other problems. I realized only after the Viewlogic deal was over that in most acquisitions, the founder of the company being acquired or the guy who created the acquired tool rarely sticks around. Usually, that’s by mutual agreement. The person who has sold his company says it’s time to move on and the acquiring company wants him out of the way.

My situation at Viewlogic was more unusual. The whole reason we had chosen Viewlogic over Synopsys was because we believed we could continue on at Chronologic the way things had been before. I really wanted to keep doing what I was doing, I was happy doing it. As I say, that was the rare situation in EDA mergers.

Viewlogic, however - with Hanover and Gene Robinson, VP of sales, running the company - really didn’t want me there. Given a choice, they would have preferred that I leave. So I never knew at the time if the things they were doing were consciously done with the thought of driving me away or not.

I was definitely under stress while I was there. The notebooks that I kept at the time have an entry that says that the Viewlogic purchase was an okay deal - could have been better - but it was all right. But, it rapidly became apparent that it was not an okay deal.

It turns out that most of my battles with Viewlogic over the next year, following the acquisition, had to do with their sales people. We only had 6 people in sales and Viewlogic couldn’t see how those 6 could make any difference compared to their 80 sales people. But our 6 people sold more than all of their 80, because they focused only on VCS and knew the customers.

In addition, Viewlogic didn’t have any products in their portfolio that were as expensive as VCS was. A single license for VCS was $40,000, while Viewlogic’s most costly product at that time was only $20,000. The sales process for VCS was different from the other Viewlogic products.

Overall in marketing and sales, Viewlogic management didn’t want to do anything that didn’t have pay-off other than consolidating their power. Hanover was absolutely behind Gene Robinson and neither of them liked the idea of our having any autonomy at all.

Had I known more about EDA, none of this would have happened. I would have known that in EDA, there’s no such thing as an independent subsidiary. I would have seen that Aart de Geus was being honest in his dealings with us regarding that, and I would have known that Viewlogic did not have the potential that Synopsys did. Also, I would have realized that Chronologic was worth far more than $25 million.

But of course, it would have taken until the end of 1994 to do an IPO. We had projected our sales for 1994 at $10 million, but in fact we generated $16 million. So as it turns out by the end of 1994 we would have had enough revenue to do a credible IPO. We really were in that year 3 revenue “hockey stick” in 1994 where revenue takes off dramatically. It was a lost opportunity all the way around.

I’m pretty certain any IPO we attempted would have been pre-empted by a purchase by Synopsys. We would have been able to get at least double what we got for the company, particularly as we would have seen the spurt in revenue growth. I have a good friend who’s a VC and when I first started Chronologic, I told him my business plan for the company was to write a simulator and sell to Synopsys. It took a circuitous path for that to come to fruition, but that was the conclusion that was inevitable.

So 1994 was a pretty heady year and a terrible year at the same time. Just one month after the acquisition, it became apparent that I had made a terrible mistake. Viewlogic’s overall business was stagnating, just as we were beginning to gather steam. Their response was to try to consolidate more control over us, the response of an insecure management. By early 1995, Viewlogic had missed their Q4 numbers, their stock had plummeted and the company management was in disarray.

Chapter 8 - 1995 to 1998

By 1995, things were bad. At this point, everybody at Chronologic felt we’d been lied to and mistreated. Allen Michels left at the time of acquisition. I called him and asked him what to do and he sent me to see a lawyer in L.A. who told me I had a case.

We had a meeting of all of the management at Chronologic. The lawyer told us, “If you file a lawsuit against Viewlogic, the remedy will be to nullify the acquisition.”

So we notified Viewlogic that we wanted changes. Then things went from bad to worse. In May ‘95, Viewlogic filed a lawsuit against me personally, then we filed our lawsuit. Then they added to their lawsuit everybody at Chronologic who was a plaintiff in our lawsuit against them. When that happened, the entire management of Chronologic, short of Peter, left within a single week.

At any rate, our lawsuit wasn’t a good idea and it didn’t get very far in court. It turns out there was a clause in the acquisition agreement that said any representations by Viewlogic not included in the acquisition agreement had no effect. That’s a standard clause in these things and we couldn’t get around it.

Even today, it’s still annoying that someone can misrepresent things legally. My advice to anyone in a similar situation would be to get all your understanding in writing in the acquisition agreement, but that’s easier said than done. At the time, I never thought I’d have the opportunity to take advantage of these lessons, however I have told other people who have benefited from our experience.

In any case, as part of the acquisition, Viewlogic wanted me to sign a 4-year non-compete agreement and I said this one’s not worth fighting about.

By 1995, I regretted signing the non-compete. I definitely felt that there was an element of coercion in the non-compete agreement that I had agreed to. I should never have signed it. In fact, if I had challenged it in court, it would not have held up because the time span was so much longer than the norm. But I didn’t mind too much at the time because I wanted to try some other things and I didn’t think I wanted to be in the EDA business again anyway. Even then, I didn’t consider myself an EDA guy. I’d been an EDA guy at that point for not quite 3 years. After that, it took me a long time to decide that EDA really was the industry I wanted to be in.

The years after my departure from Chronologic were more difficult than I could have imagined - they were just really hard. At first, those of us who left Chronologic formed a consulting company in trying to move forward. We rented a little office down the street in Los Altos from where we had been in business as Chronologic, and we worked doing verification projects for various people.

Eventually, however, Mike McNamara, Todd Massey and Chong Guan Tan went off and founded SureFire, at which point we closed the consulting company.

The web was beginning to blossom at that time, so I thought I’d write an on-line Verilog course. I was of the opinion at the time that that was the modern way to write a book. I ended up spending about 6 months writing the HTML-based training course, thinking I would sell on-line access to it. Although the commercial aspects never amounted to anything, it was a pretty decent effort. It was hosted for a long time on the ISD Magazine website, but they gave it back to me when the magazine folded. Today I pay the hosting fees, the course is free, and it still lives on-line. Surprisingly enough, it still gets about 600 registrations per month.

Meanwhile, I was only 47 and still fairly energetic - I certainly wasn’t ready to retire. So I went off with a guy I knew from the Ardent days. He was an ME and we started a company together doing MCAD software. His idea was that there was no MCAD language comparable to Verilog as a description language. But after two years of effort, we decided the idea was just a research project and not a business proposition. It was a good distraction for two years, but the biggest benefit I got from it was the realization that I wanted to go back to EDA.

During the Chronologic years, I had driven my daughter to school every day as she moved through the 5th, 6th, and 7th grade. Our conversations were usually about the company. She and my wife knew all about the company as it was growing and were deeply involved. Our family dinner table conversation was all about the growing business. After it all ended, and despite the MCAD project, I went into a really deep funk and my family knew it.

Finally, my wife said that anything would be better than what had been going on with respect to my attitude about things. I said I couldn’t just pull a switch and change my mood, so she said I should start another company if that’s what it would take - it was either that or move out. The non-compete agreement I had signed with Viewlogic was about to expire, so with my home life as motivation, I decided it was time to start CynApps [Cynthesis Applications, Inc.].

Chapter 9 - 1998 through the boom

CynApps changed everything. I didn’t want to write another Verilog simulator, nor to start another company like Chronologic, but I did want to try again. I really wanted to be a significant player in the industry, raise my sights, and do something more dramatic than Chronologic.

Andy Goodrich was a friend from Michigan and a graphics chip designer. He showed me a C++ class library he had written to use for hardware design. I thought this had promise, so I spent a couple of months in the beginning of 1998 experimenting with it to decide if it was really viable.

I needed access to some real hardware models, so I asked Jon Rubinstein - who was by then the VP of engineering at Apple - if he could help. Apple had just laid off a large part of their engineering staff and had plenty of spare workstations and cubes, so he gave me a contractor’s badge and access to their design group. It was their darkest time, just before the iMac was introduced and the company turned the corner, but it was quite pleasant for me. I convinced myself that you could design real hardware in C++ and this was worth pursuing.

Andy was up for a new venture, so I then talked to Randy Allen about the idea. He said we could get rights to the Kubota C Compiler, which he had received personally when Ardent folded. He said we could turn the compiler into a high-level synthesizer and combine it with the C++ class library. And that’s what we did.

The three of us founded the company - Andy Goodrich, Randy Allen and myself. I’d known Randy from Ardent and Chronologic. He’d been hired by Synopsys, after his time at Chronologic, to develop a VCS clone - which was legal because he’d never been asked to sign a non-compete agreement. That project ended when Synopsys acquired Viewlogic and got VCS. Randy became our VP of engineering at CynApps. He’s now the CEO of Catalytic Compilers.

So the tale of CynApps unfolded. We could see that designing at a higher level of abstraction, in C++, was going to succeed eventually, so we oriented our activities at CynApps around that concept. To do that, we needed to have enough products to be the dominant player in the front end of the design flow. Doing a single point tool like we’d done at Chronologic was interesting, but I wanted a product family that we could build a franchise around - a whole new design methodology.

I used to be fond of saying that if you wanted to create a significant EDA company, there was the Synopsys model and the Cadence model. You can plan to do a Cadence-type business model, but you can’t plan to do a Synopsys-type business model. In the Synopsys model, you had to develop a tool that’s key to the design flow and become a monopoly. In the Cadence model, you had to collect enough components of the design flow to be a major player. My goal with CynApps was to make a new Cadence - I wanted to do the acquiring this time.

To do that, I knew we needed to do things differently than at Chronologic. First of all, this time I took investment money. That had become a necessity by 1998 - people’s attitudes about start-ups had changed and you couldn’t get people to work for nothing at that point. Also, although my situation was different because my wife continued to grow her medical practice and provide household support, my co-founders at CynApps couldn’t afford to live on nothing.

We also needed to add people quickly, but people wanted stock in the company and they wanted to be paid as well. Those were the rules of the game in 1998. So, I had to look for investors. There were two investors high on my list, Prabhu Goel, the founder of Gateway, and Lucio Lanza, a partner at USVP. Prabhu wasn’t interested, but Lucio was - USVP became our VC for the first round of funding.

Actually, raising money isn’t hard if you’ve had a success before. I got a number of angel investors along with Lucio and USVP, and Lucio joined the board. So we started with one institutional investor and 7 private investors. Altogether we got $1.8 million, which seemed like a lot compared to the zero dollars we started with at Chronologic.

Lucio and all of the subsequent investors were very supportive. Contrary to the popular conception of VCs being controlling and rapacious, I never had that experience. We were lucky to have matched our business with VCs who understood the EDA industry. Lucio had been an early EDA participant at Daisy and then Cadence, and he was always sympathetic to our efforts. He understood our development needs and never lost faith that, if we succeeded, there would be a big payoff.

When we were ready to get an office and get started, we got help from Nvidia. I had known Chris Malachowsky, one of the founders of Nvidia, from my Chronologic days. When Chronologic was up and running, I had gotten a call from Jen-Hsun Huang, the founder of Nvidia, who said if I would give them some Verilog licenses, they’d pay me later when they got their funding. Cadence wouldn’t give them a break, but I did, and true to their word, 6 months later they paid me. They became a great customer.

Nvidia was the first all-VCS shop. Jen-Hsun and Chris were really grateful for my help at that time and we were always friendly afterwards. In 1998, they offered to give us free office space for CynApps in the Nvidia building. I’ve always thought that was one of the striking things about the Valley. The good things you do often come back to you.

We stayed at Nvidia for about 5 months, but they were growing so fast, they eventually needed the space. So, we went off to an office over on Mission College Blvd. in Santa Clara in 1999. We got a fairly nice office at a reasonable price and repeated a theme that you often saw in the Valley, a bigger office than was necessary at the time with unused space. In our new offices, we gave space to a company that USVP was funding. Procket was a 2-man, next-generation router company that ended up being a really high flyer during the boom. Procket turned into our first customer at CynApps.

I’m quite sure that this sort of thing can only happen in the Valley - not in North Carolina or Texas.

Initially, we thought we’d sell the Cynlib library for $1000 a license. Then the open source movement caught on and we decided that in the era of open source, selling Cynlib at that price just wasn’t worth it. So, we made Cynlib, our C++ library, open source. We released Cynlib in September of 1999. I told Synopsys we were going to release it under an open source license, but they weren’t interested in doing that with SystemC, which was very similar to Cynlib.

Our release of Cynlib may have been the first open source EDA product released by an EDA company, and it did have an impact on SystemC. Synopsys talked to us about joining the SystemC effort about two months before we released Cynlib, but there were personality issues with the people who would have had to work together and we decided to go our own way. In hindsight, this was a mistake.

In October 1999, Synopsys released SystemC under a community source license, not open source. Eventually Synopsys did release a true open source license for SystemC, but only after a lot of sturm and drang.

We had several other products, aside from the free class library, including a translator from Verilog to C++. We knew we wouldn’t make a lot of money selling these products, but until the synthesis product was ready, this was what we had to sell. Meanwhile, a few customers were buying our methodology and we would say, “For your project, we’ll charge you $100,000 and give you all the software we have.”

It turns out the most useful of the products was the free Cynlib library. However, none of the customers complained. They were buying methodology, and actually got their money’s worth.

So at that point was CynApps a product or a services company? I think calling yourself a product company at a certain phase in the life of a company is really a statement of intent more than anything else. I always used to say that when you don’t have a product, you sell services.

Verisity had gotten started selling methodology and so had CoWare. They got paid to have their AEs go into a customer’s site and stay there, but it wasn’t for several more years before their software was robust enough to sell without the AEs. I used to be critical of this model, but it’s a valid way to get a business started.

Lucio and Gordon, who was again on my board, urged us to acquire a small behavioral synthesis company in Pittsburgh called Dasys at about the same time as we raised a second round of financing. This added some of the best behavioral synthesis experts in the world to our engineering team. Sam Lee from Infinity Capital led the second round. He’s another VC who really understands the EDA industry, having been a user himself at LSI and then the first VC at Ambit.

Lucio and Sam stuck with us through thick and thin. That is what led us to our eventual merger with Chronology [not to be confused with Chronologic] which Lucio himself engineered. The merger was a good thing for the company, and importantly allowed us to get additional financing. Also through the merger, we got some very good people. The disappointment of the merger was that the Chronology verification products, which we thought would provide a strong revenue stream, didn’t survive the bust.

Meanwhile, as it turned out, the high-level synthesis and technology part was much harder to do than we had thought. The synthesis development effort took much more time and resources than we had anticipated and our plans for the other products in our suite of tools had to be pared down. Without high-level synthesis, design in C++ isn’t very compelling, and the other products couldn’t stand on their own.

By 2001, we were selling methodology, but not much. We were working on the synthesis product, but it was still a long way from customer-ready. With the merger with Chronology in 2001, we were now Forte and we had verification products to add to our methodology sale. We had also added a new CEO, Jacob Jacobsson. Then the bust hit.

Chapter 10 - From boom to bust and back

With the merger of Chronology and CynApps we had about 65 employees, but after the bust it was apparent we couldn’t support that many people. We went down to about 30. Meanwhile, sales of the lower priced verification products were falling off, while our more expensive methodology sales were going to zero.

At the height of the boom in the summer of 2000, we had moved into offices on Technology Drive. At that point, we were paying top dollar for a lot more space than we needed, but our expected growth didn’t happen. In 2002, we told the landlord that we would go broke if we had to keep paying rent at the agreed to rate. Our landlord said, “Tough.”

So we just stopped paying the rent and basically got kicked out. We were given three days to vacate and in those three days, Jacob, our CEO, found better quality office space three blocks away and ended up paying less than a third of what we had been paying. It may not be as much of a fire sale today as it was then, but ours was a typical story in the Valley in 2002.

When you’re in product development, it’s not so bad to live through a downturn. Nobody’s buying anything, but it doesn’t matter, because you don’t have anything to sell. We had expected to make sales from other things than the synthesizer, but because of the downturn our existing products simply stopped selling.

By the middle of 2002, we weren’t selling any of our existing products, and the synthesizer was clearly where our future was. So we cut everything else off and concentrated on that. The value of focus is something you learn over and over again in this industry.

Importantly in 2002, we were able to raise another round of funding, which we did by saying the money was just going to the development of the synthesizer. And that’s when we really started turning the corner. By Q4 of 2002, we got a purchase order from Sony and then things started to look up. The product, which was now called Cynthesizer, was still very immature, but we were getting to the point where it worked.

Today the Cynthesizer really works, we have 38 employees, and we are still relatively careful with hiring. We would be even smaller except for all of our customers in Japan. Innotech told us last year they were going to stop distributing non-Cadence products, so we hired some AEs and the Innotech sales guy and formed a KK. As a result, we have more guys in Japan at this point than a company at our stage normally would.

What’s coming up over the next 18 months? Well, it looks to me like consumer electronics is going to continue to do well, and most consumer electronics is done in Japan. Having said that, there’s competition for the Japanese coming out of Korea and Europe. We have customer engagements in all those places. We don’t yet have any customers in China.

The U.S. market is somewhat softer in C-based design as yet, because the U.S. isn’t doing designs in general that are as algorithm intensive. The design organizations in the U.S. that are doing algorithm intensive designs developed their own C-oriented design methodologies several years ago, and aren’t ready to change over to a standardized one. They don’t yet see the value, but they will. Are the existing EDA companies working to inhibit that move? I doubt it. I don’t believe in conspiracy theories - people in this industry generally don’t do that.

There is one last portion of my story to tell. Right after Viewlogic acquired Chronologic, Joel Paston introduced me to Rajeev Madhavan. Joel had met Rajeev on one of the OVI committees. Rajeev told me that what Chronologic did to Cadence, he could do to Synopsys. He had access to code from BNR and needed some funding to make a synthesis product to compete with Design Compiler. So I introduced Rajeev to Allen Michels and Gordon Bell, and we put together the first seed round for Ambit. I stayed in contact over the next year with Rajeev and went with him to various fund-raising meetings. Rajeev had to spend an inordinate amount of time raising money to keep the company going. We got to be good friends.

When Rajeev left Ambit, it was another one of those contentious events. I ended up trying to mediate between the two parties for several months. Eventually Rajeev sued and Ambit counter sued. So much for my political skills. When Rajeev started Magma I encouraged him because I thought that getting on with his life was the best thing for him to do. Another lesson from Chronologic.

Epilogue - Multiple Myeloma

I was diagnosed with Multiple Myeloma in the fall of 2001 by way of a blood test, which showed elevated protein with a monoclonal protein spike. The web said at the time that the median prognosis for the disease is 33 months from time of diagnosis. That prompted me, among other things, to start writing my memoirs, which will cover the 1980’s, and 1990’s in Silicon Valley. I’ve heard a number of things said about that era that I know to be incorrect and many of the details of the story are beginning to be lost. I want to get this stuff written down, so that the part of the record that I know about is recorded accurately.

I had a bone marrow transplant last fall because even though at that point I wasn’t symptomatic, the cancer level was dangerously high. A transplant is the normal treatment if you’re healthy enough to go through it. It takes 4 or 5 months to prepare by taking various drugs, and then you have the transplant followed by stem cell re-infusion. It’s pretty amazing that it works, but is a blunt instrument at best and only produces a remission of a few years.

The transplant was done at City of Hope National Cancer Center in Duarte, in Southern California. They’ve got a nice program there with a set of apartments on the grounds. The whole treatment was done as an outpatient procedure, where I walked over from the apartment each day for the 4 or 5 hours it took per session. I had a Hickman catheter inserted in my chest, which I found to be the most annoying part of the whole thing. With my wife taking care of me, I made it through the transplant with no complications and no infections, which is relatively rare. It took me about four months to fully recover from the transplant.

I exercise regularly, riding a bike once a week - I actually started riding in the 1980’s - and work out several times a week. I’m probably in better shape now than I’ve ever been.

When we were researching options with respect to Multiple Myeloma, my wife looked around for an oncologist. The one we went with had another patient who was the chief scientist at Finisar, a local optical component company. He was only 39 when he was diagnosed - just after the company had gone public - and he decided he would start a fund to raise money for Myeloma research.

He got $750,000 per year for 3 years to fund three different research organizations looking for treatments for the disease. He raised money primarily from a few of the winners from the Finisar IPO. I told him I knew some winners too, and that perhaps I could raise some additional funds. So I started working on that project around the end of 2001. The Myeloma Research Fund, the MRF, has been administered since its inception in 2001 by the Peninsula Community Foundation. It’s an extremely efficient way to fund cancer research.

There are three groups being funded by the MRF - Dr. Ken Anderson at the Dana-Farber Cancer Center in Boston, which is associated with Harvard, Dr. Bill Dalton’s group at the H. Lee Moffett Cancer Center in Tampa, and Dr. Jim Berenson, at Cedars-Sinai and UCLA, who has recently established the Myeloma and Bone Cancer Research Institute in L.A. The fund-raiser being hosted by the EDA community on September 15th in San Jose will go toward the research those three groups do. The idea for the September event was Venk Shukla’s from Magma.

I’ll be at the event and it may be a little awkward because I look pretty healthy. I’m afraid I won’t look like a very good poster child for cancer research. People who know me will only notice a difference in that my hair is now curly. It grew back that way after the transplant. Otherwise, I look perfectly normal.

There are a lot of new drug treatments being researched right now for Multiple Myeloma including drug cocktails that involve thalidomide and dexamethasone in lieu of chemotherapy. They’re effective, but have a limited duration of effectiveness. They have their share of side effects, but they have fewer global side effects than chemotherapy drugs.

There are other drugs as well, including Velcade, a proteazome inhibitor to which about 75 percent of patients respond. None of these drugs remain effective for a long time, but while they are, the results are encouraging. I’m convinced that these new types of drugs are the future of cancer therapy.

My wife and daughter have been very supportive through all of this. It’s been a tremendous benefit to me that my wife is a doctor. I turn to her for advice and information, and her ability to navigate the health care system has certainly been a benefit for me. It hasn’t been easy for her, though, since she knows all the bad things that can happen and has a tendency to assume that they all will. I just trust in research and hope I’ll be one of those who outlives the distribution curve.

I’ve been about as lucky as you can be with my family in all aspects of my life.

[Editor’s Note: My conversations with John Sanguinetti have been among the most interesting I’ve ever participated in. I appreciated his candor, and wish him continued success in his battle with Multiple Myeloma.]

"Bookends at Cadence—Fister & Costello"

* Prologue - The official word from Cadence

You can skip this bit if you already know that...

Mike Fister is President and Chief Executive Officer of Cadence Design Systems, Inc. Prior to joining Cadence, he spent 17 years at Intel Corporation, where he was most recently Senior Vice President and General Manager of the company's Enterprise Platforms Group.

Previously, Fister served as Vice President and General Manager of the Performance Microprocessor Group, where he managed Intel's IA-32 processor development organization and was responsible for the design, development and marketing of IA-32 processors, including the last versions of the Intel486 and the entire line including the Pentium Pro, Pentium II, Pentium III, Celeron, Pentium II Xeon, and Pentium III Xeon processors. Prior to this role, Mike held many other product development positions at Intel and has a long legacy of successful technology development and product delivery.

Fister is a graduate of the University of Cincinnati where he received a BS and MS in electrical engineering in 1977 and 1978 respectively. He spent his early years in a variety of executive and engineering management positions at Wyse, Machine Vision International, and Cincinnati Milacron. He currently sits on the Board of Directors of Autodesk Corporation.

Chapter 1 - Mike Fister

Mike Fister was named President & CEO at Cadence this past spring, just in time for DAC 2004. Fister's appointment caused quite a stir at Cadence, and in the industry, because change always does. We spoke by phone on September 15, 2004 - the same week as the Cadence Users Group Conference in San Jose.

Q: How is the Cadence Users Group Conference going?

Fister: [Very well], although I've only been able to be there for a little bit this week.

Q: Presuming you've moved in from out of the area to take over at Cadence, how has the relocation to San Jose gone for you?

Fister: Our home is in Portland, Oregon and [we still have children in the area], so I'll be commuting down to San Jose. [But it doesn't matter where I am because] I'm very much a work-all-the-time person, which means I work about 100 hours a week. But, I've always loved what I do and I'm very committed to our Cadence team, [so it's not going to be a problem].

I'm also a big bicycle rider. I ride a lot in Oregon, and it's great that there's lots of biking in this area as well.

Q: Where were you born and where did you grow up?

Fister: I was born in Savannah, Georgia, but I grew up in Cincinnati. My father was a EE - he was infamous in the [design of the] instrumentation in jet engines at GE. So, I grew up wanting to be like Dad. I attended the University of Cincinnati, where I got my BSEE and my MSEE.

[While I was in college], I did an engineering co-op at Intel, where I worked on the 4040 and 4004 and got a lot of notoriety for some special stuff I did on those products when they were first coming out. So, after I got my MSEE, I went to work for Intel full time.

[At one point], I left Intel to join a small company working in the area of robotics. We were working on machine vision and the problems were pretty intriguing. We developed non-traditional computer architecture approaches [to the problem] based on an abstract algebraic approach - not a statistical approach. It's the computer architecture guys who [usually succeed in applying] these techniques to problems like traditional data processing, vision, and control.

After I left the start-up, I went back to Intel to develop microprocessors and micro-controllers, where several thousand of my buddies and I built product lines that you're probably typing on right now. We pursued the thoughtful evolution of products through to today's Pentium III and IV, which allowed us to change the world. I'll never be able to fully show the total strategy behind all of that - you've just got to meet guys like me and some of my colleagues to understand. It was a very considered evolution of those products - different products [to address the needs] of many different types of users.

We always planned the microprocessors at Intel with architectural innovations that would also show a product continuum. The why and the sense of the product flows were always implicit in the success of those product lines, because in the design process, it's the approach you're taking and knowing what kind of product you want to build. And, of course, always at the root [of everything] is a design method that's dependent on the human dynamic in the tools.

All of that left me interested in going out and trying to help our industry supercharge the inevitable, which is to be increasingly more dependent on the computer. You can see how I'm a logical guy to a fault.

Although I was trained as an engineer, I've always been more interested in how people think as opposed to how to get things done. My old man derives a formula [to solve a problem] when he needs it, whereas I develop a theory. Electrical engineering training is at the root of everything I've done, even in this adventure into EDA. Because in the design process, it's the approach you're taking which is just as much a part of the thing as what kind of product you want to build.

As the world continues to evolve, the complexity and dynamics increase - we'll have larger and larger devices, devices with crazy performance [metrics], and products that combine mixed signal with analog/digital stuff.

All of us are going to increasingly benefit from the companies in our industry. I have an organizational approach for integrating that experience and [helping to push that process forward].

Q: At the Gartner/Dataquest Semiconductor Conference this week, Intel CTO Patrick Gelsinger said that everything in design revolves around Platform, Package, and Power. Would you agree?

Fister: For me, it's more about the social issues.

Q: At that same conference, Gartner Analyst Jim Tully closed by summarizing the three major themes he saw at work in the industry - Consumer, China, and Consolidation. What do you think?

Fister: Yes, there is going to be further consolidation in the industry. At Cadence, we're very thoughtful about that and the roles we are going to play in doing that. We're busy trying to integrate disparate technology and [looking to achieve] a better, holistic tool set rather a tool for each domain.

And while we're bragging about our demonstrable [technology], we're also walking the talk about Open Access. [The ability to develop tools in an open environment promises] incredible rewards to the industry. We want to be the driving force behind Open Access - to drive our tools for interoperability, which may [actually] help drive our competitors' tools. So, it's a bold move for us, because we're daring ourselves to be good. But it's promising a new era in open industry participation - and a breath of fresh air.

Also, there are issues about licensing that we're addressing. There are a number of different business models that can go in a number [of different directions]. I'm very open to the view of trying the different things that will link us to the manufacturing ability of our customers, so we're also very concerned about] tools for manufacturability. [Many customers] have an idea that yield is more than the raw counting of dies, but [also in considering] the goodness of the product. However, you don't know how good it is, until you get to the end of the [manufacturing] loop. That's the reason why design is inexplicably linked to manufacturing.

A company must never stand still in its technology or its business model. Our leadership in the industry means we're going to lead the industry and [at the same time] compete with ourselves. We will be innovating not only in the technical areas, but also in business areas with relationships that we've formed with key customers - relationships, which are very methodical, while also allowing us to sustain our [leadership in the industry]. [All in all], we are all about trying to help our customers.

By the way, this may sound like a Cadence commercial, but it really isn't. [Laughing]

Q: How do you feel things are going in the EDA industry?

I'm a business pragmatist. I believe product lines should be the drivers - I'm not a technology zealot like some. At Intel, we were always careful about the evolution of the technology and timing of the technology, so that the product flow and the timing were very thoughtful. From Intel's standpoint, it's the product guys who are the most powerful manifestation of what the industry is doing.

In the EDA industry, we [frequently and unfortunately] get people to delve into unbelievably deep detail about stuff that doesn't have a lot of relevance to what the customer is trying to do. My fiber is [all about] looking at the problems that people are trying to solve - it's about a timing process synchronization. I want to look at the domains that will be the most relevant to users of our tools, [particularly] on a two-to-three year cycle.

As an example - somebody's attacking a mixed-mode design with analog, digital, high performance specs - there may be a technology that's preserved or reserved to do all of that, but laboring through and debating whether our technology is better than somebody else's ability to solve the problem is largely an academic exercise. I want to train our technology into a useable tool kit that attacks the application domain. I want to see [our customers getting] more value out of the holism of the approach - an entirely differently mentality.

In the quest for leadership in EDA, however, some people have decided to base their [position] totally on a technical foundation that sounds like techno-babble to customers. In fact, however, EDA is all about time to market, managing complexity, and garnering value for the integration of what our customers are doing.

When the Apple guys built the best MP3 player in the world, they weren't trying to say that they wanted to integrate this magnetic storage with that interface and [so on]. They were saying they wanted to create a package [with these specific features] that would fit into a pocket. They worked with the rest of the industry to integrate [specific technologies] to create a product that was smaller, sleeker, and cooler. And that's where our efforts should be directed.

I want us [to work with the customers, who are working] with hierarchical flows at 90 nanometers. It's a Fister passion that we're going to be in that thin strata of people, who actually talk to our customers' customers, because those are the penultimate "What?" guys. They'll give us the insight as to whether or not our tools and technology are relevant. We'll benefit [by adding] more value to our tools, our technology, and our services.

Q: When will Cadence buy Wind River?

Fister: [Big laugh] I haven't thought that much about it.

Q: A VC recently told me that the Cadence organization of late has been nothing short of a train wreck - a place of internal squabbles and contentious fiefdoms. How would you respond to that criticism?

Fister: Cadence has grown by acquisition and that's the [source] of some of that criticism. People wonder if we're going to be able to fully integrate those acquisitions - so it's fair to ask those questions. But, our post-acquisition retention characteristics are very strong and very high. Ping Chao is one of those guys and is a key member of the acquisition team.

I would tell you that, coming into this thing, we could be a better-integrated team, but we've got some very positive things going on at Cadence. My reputation is one of being a special person who's able to [communicate] inclusivity, camaraderie, and teamwork.

So, watch the situation at Cadence play itself out. We're going to bulk up the team in a few spots, and I know you're going to be impressed with the [additions to the team]. The people we're bringing in will be a great complement to the [existing structure], just like I was a complement to a great team.

Oh yeah - and we're going to have fun!

* Chapter 2 - Joe Costello

Joe Costello and I last chatted back in October 2001, as I was writing up an article profiling his career. This time around, when we spoke by phone in late September 2004, the conversation was prompted by Costello having been selected to receive this year's Phil Kaufmann Award. Here are the highlights of our visit.

Q: So, Joe - why the Kaufmann Award and why now?

Costello: [Laughing] Well, I got this message from my assistant that [Synopsys CEO] Aart de Geus had called. So I called him back, not having any idea of why he wanted to talk to me. Of course, all kinds of things go through your mind, so when I reached him and he said, 'I've been chartered to tell you that you've been chosen to receive the Phil Kaufmann Award,' I was definitely surprised!

I haven't been involved in EDA, except tangentially, since 1997. Although obviously, I still think about the industry a lot because I've been on several Boards of Directors since then, and am still sitting on Barcelona's Board. Also, I continue to be on the Engineering Advisory Board at U.C. Berkeley assisting [Engineering Chair] Richard Newton.

Anyway, my receiving the Kaufmann Award is one of those really great things for me. I was just beaming when Aart told me and thinking what a tremendous honor it is. It's fantastic! I think that in the group of people who have received the honor before me, it's kind of like Where's Waldo. And I'm Waldo!

Q: Are you as disaffected today with the EDA industry as you appear to have been in the past?

Costello: I'm really not thinking about EDA much these days, but I think it's true today even more than before. I don't think electronic design automation gets the value it deserves, because it still creates more value than it gets. Between the tools, the technology, and the services in EDA - people are still trying to work out the value equation.

It's not horrible, though - it's not ridiculously undervalued. I mean, we don't pay our schoolteachers anywhere near enough. Those services are horribly undervalued! EDA is not as undervalued as that, but still…

Q: Can the EDA industry evolve and improve?

Costello: Yes, it can evolve, although right now the market's a bit stagnant. It feels like it's sliding laterally, but things can happen during times of big change - which happens when markets emerge with a new view of things.

How do we grow? I still believe the way to change growth and value in an industry, is to deliver solutions, not just tools and technology. The difference is really understanding the customer's problems inside and out. What are the core objectives of your customer's business? What are their hopes and dreams on the one side, and their anxieties on the other side?

EDA is still coming at things with, 'We've got pliers, and here's a saw, and here's a plumber's helper.' But none of the customers are saying, 'I've got a hammer question.'

The customers are saying, 'We have a problem that requires a comprehensive solution.'

Q: When will the EDA industry link their financial success to that of their customers?

Costello: I agree. If you wanted to crack these things, tie your revenues and your profits to your customers' successes. That would change the equation and create opportunity for growth. Essentially what the EDA industry does today is, they limit their upside by protecting their downside. How many EDA vendors have their payments tied to the actual success of their customers?

When I pushed into services at Cadence, it was when we were trying to make that happen, although there's a limit there. In electronics and other industries, you may actually get push back in the other direction, because sometimes customers act the same way. You see them saying, 'I'll have my smart guys take your technology, and we'll do it on the cheap.' So, you see it in both directions.

The 90's were definitely the go-go years for software. Boards of Directors loved their companies to sell software. It was like selling drugs, because there were such high margins. You could sell very expensive packages with big labels like ERP, CRM, EDA, and you could make a lot of money that way through expensive sales channels and high prices.

Selling services is something different, however, and people are looking for something different today. Customers are saying, 'I already have a lot of software, and it didn't really work for me. I paid a lot, but didn't get real solutions.'

These days, people have changed the phrase 'Total Solution' into a political sound bite, but if you tie your revenue to your actual customer's success, people won't keep buying your software unless you really provide a solution. I'm talking about the kind of pro-active success that creates a real bond between a vendor and a customer. Something that people feel proud of, and that you can measure.

Q: Does it strike you as interesting that people often say that things in EDA were so much better when 'Joe' was around?

Costello: I did my piece in EDA and I'm not there anymore. So I don't really think about it.

Q: Okay - so, what are you going to talk about in your acceptance address at the Kaufmann Award dinner in October?

Costello: I'll probably talk about all of this stuff we've been talking about here. Of course, they'll say it's just the same old Joe, but I've seen this stuff succeed in other business segments. And, of course, now that I've worked in the MCAD industry, I've seen how much easier folks have it in EDA than in MCAD, where things change so much more slowly.

In EDA, Moore's Law forces the customer to continuously upgrade the technology, so it's a nice business-forcing function for the EDA industry. In MCAD, there isn't a Moore's Law, which forces the [MCAD vendors] to look at what the true value of their software is. In MCAD, you have to prove that you're solving a really big pain for your customers. If you're not, you're not going to get diddly from them.

It's completely different in EDA. What EDA needs today are leaders who have a higher motivation to move things forward. It's not just money that motivates people - it's the pride of making a change and making the industry better.

Q: Why do you think there aren't more women in EDA?

Costello: Well, generally people come into EDA from EE, and it's scary, but there just aren't many women there. I heard this story from Richard Newton that people claimed there was no gender bias in a college application for an electrical engineering program. But it turned out that there was this one question on the application that asked high school seniors if they had ever done any serious work on a computer science or technology project in high school.

It turns out, that by eliminating that one question on the application, the school was able to change their screening and increase their acceptance rate for women students to 30 to 40 percent. Because, although the women applicants did well in science and math, the gender bias showed up in that one question.

The hopeful things, however, is that there are more and more women going into business, even though EDA is biased towards engineers who tend still not to be women.

But really, if you want to be successful in running one of these companies, it just doesn't make any sense for somebody to try it who's not completely immersed in the technology. After all, that's the only way you're going to understand your customers and your own guys. If you don't have that technical background, it's really difficult to lead the company.

The flip side is, you can surround yourself with those kinds of people, the technical people. But even if you surround yourself with fabulous people, you're the one who's got to make the final decisions, and you shouldn't find yourself having to flip a coin to make important decisions.

Q: What do you think about the concern these days over the outsourcing of high-tech jobs?

Costello: I understand the underlying issues - most people are hysterically highlighting the thing right now. But instead of attacking it, we should embrace it. People outsource all sorts of things, so the important thing is how does our country, our economy, and our industry deal with it?

On the flip side, we need to be cautious in the U.S. We've gotten fat, dumb, and happy here. We need to step up the pace in this knowledge-based industry. The only thing that sets us apart is our education, the educational level of our population. We need the government to encourage education, and for people to take advantage of the educational opportunity they have here.

An engineering and science education is an extremely powerful foundation for people. I was not a practicing engineer for a huge number of years, but the foundation I got through that experience helped me to know how to approach problems and analyze things.

I strongly encourage that everyone be exposed more to that kind of education than they are today. A science and engineering foundation is an incredible platform that's extremely useful later in life, whether it's in management, sales, or even the arts.

What people get paid highly for in our society is Sales and Marketing - and even Finance. All of those people tend to get paid in our society more than our engineers, although many times engineers have a higher IQ. But the first group brings the higher value add to the thing, and just as we treat entertainers and athletes as celebrities, there's a personality thing that's required to be a success in Sales and Marketing. The thing that engineers can get paid for is innovation, which is always highly valued.

Q: What do you predict going forward to the technology sector?

Costello: My forecast says move to China, for the reason that things are happening there at a really incredible rate. Maybe some of the environmental things there aren't as good as they are in the U.S., but there are really smart people there and the market is really growing there. I mean, where do you think the next great innovations in cell phones are going to come from?

China has had some successes and some failures, but it's an exciting and a formidable place. We've got to take advantage of that, and I mean all players - whether you're in manufacturing or in electronics.

I say, don't play sour grapes and put up walls because of fears of outsourcing to China. We used to have it easy here in the U.S., but look at this summer's Olympic games. America didn't win at basketball and China was Number 2 in the overall number of medals won. That's where the world is going.

Q: So, are you looking forward to the EDAC Awards dinner?

Costello: Absolutely! I'm going to bask in the award, although I hope it isn't too obvious. [Laughing]

My number one message at the dinner will be, 'Get closer to your customers. It's true that sometimes customers can be mean spirited, arrogant, or cheap - picking away about small costs. But in general, you've got to embrace those customers. There's a whole new generation of semiconductor companies, and a whole new generation of things happening. So, there's a new generation of EDA that needs to be managed. There's an opportunity here for both sides to make a change. Break out of your defensive arrogance, and make things happen!' [Laughing again]

They probably all know I'll say these things, so you've got to see that it took a lot of guts for EDAC to give me this award!

"Princeton's Wayne Wolf"

Somewhere in the early 1980s, when I was a graduate student at Stanford, I took a class on VLSI design. Truth be known, I dropped that class midway through the quarter, but in recent years as I've seen Professor Wolf speaking at various technical conferences, I've often wondered if perhaps he'd been the TA in that VLSI class, way back when.

When I asked him that question, at the outset of our phone call in November 2004, to my delight he said, "I did TA the VLSI design course for several years, starting in 1979. If you took the course in that timeframe, then I was your TA because I was the only TA for the course." The rest of our conversation is as follows:

Q: Have you enjoyed living in Princeton after your many years at Stanford?

Wolf: It's actually better here because there's less traffic.

Q: How would you characterize the VLSI design course work at Princeton?

Wolf: About 2 years ago, I uprooted our VLSI course - which was more of a traditional Mead-Conway course - and redid it as an FPGA course. It's not a standard design course, in that we first talk about VLSI, which is sort of digital circuits; we look at what an SRAM is; we look at interconnect delay; and then, we look at FPGA architecture and use that to understand VLSI design. The students [come to] understand why FPGAs are designed the way they are. Then we go on, and do logic design with an FPGA twist. [Through all of this], the students learn how it is that logic design is fairly standard.

There are a couple of reasons why [this teaching strategy] makes sense, at least for a lot of schools. It's actually a lot easier to talk about some of these concepts when you've got something real in front of you. So, if you use an FPGA as the basic source material for a course, you can say to the student, "Here's a chip design for you to understand."

In reality, most Princeton students are not going to go on and become custom VLSI designers. A few of them might go out and do microprocessor design projects, but most of them who are going to do logic design, are going to do FPGAs. So, I decided to redo our design course in this way after listening to various colleagues talk about the decline in custom chip starts over the last couple of years. Certainly, there are custom chips being designed today - large and interesting chips - but not as many as there were in the 1980s. Teaching FPGAs in a VLSI course is a natural conclusion here.

Q: Does this mean that FPGAs are going to dominate the universe?

Wolf: First of all, FPGAs aren't the solution to all of the world's problems, but they are a huge business that's growing like crazy. So, it makes sense for students to understand FPGAs.

They definitely offer enough [technical complexity] to satisfy the needs of a basic course like ours. FPGAs are the right medium for teaching today.

There are probably some schools where it makes sense to teach a [more traditional design] course - schools like Berkeley, UT Austin, or Stanford where they have enough faculty to teach VLSI design and test, and they've got a large number of students who have a chance to really be working in this area. But for a school like Princeton, teaching [with FPGAs] makes more sense right now.

Speaking globally, there is a link between shifts in the technology and the shifting labor [patterns in engineering]. An increasing number of back-end chip designs are being done overseas. However, our using FPGAs in our courses has nothing to do with the cost of labor here in the U.S. versus overseas.

It's more about [having the students become familiar] with the components of design being used today. In telecomm, for instance, FPGAs are widely used for base stations, and so forth. If you're [designing chips] and your customers need high performance, but low volume, you'll probably use FPGAs for that product. In the 1980's, you could do that same design with an ASIC, but now that option's too expensive.

Q: Are the design tools you need for student projects readily available from the vendors?

Wolf: Actually that's another advantage of teaching the basic design courses this way. We use Xilinx tools. They're free, pretty well integrated, and easier for students to use and see the effects of using tools. You can run random, multiple designs using the tools, and you can [execute] place-and-route changes - all processes which are within easy access of the tools.

Q: As students move away from actual circuit design, are you concerned that their basic knowledge of transistors and electrical theory is lessening?

Wolf: Students at Princeton take courses on physics and transistors. The question is, can they use that knowledge to do something that's interesting? Part of the solution is to give them interesting courses where they can understand and learn the basics, and they can also have exposure to realistic problems. Our FPGA course is a good example where students can do something practically, and also learn some circuit theory in the process. [As always], it boils down to a question of breadth versus depth.

Q: For students, who do work on ASIC design in a course at Princeton, do they ever see their chips manufactured?

Wolf: The sophomore students manufacture something very small, with just a few transistors, and they test it. They're able to do all of that in one semester, but they get guided through the process. If you're talking about larger chips, however, we do have some testing facilities on campus. But, there are no more functional testing facilities on campus.

In the old VLSI course that we used to teach here, I didn't have the students fabricate their designs because it just took too long to get them back. [On top of that], there was no guarantee that the students would return for the follow-on course where they would actually test their chips. Again, this is another advantage to the short implementation cycle [associated with FPGAs]. Students have an actual chip in hand much faster.

Q: Where do your students end up after graduating with a degree in Electrical Engineering?

Wolf: Here at Princeton, as fair number of our EEs go into consulting work. They sometimes end up on Wall Street, where they use various sorts of rating algorithms in their work. However, some of our graduates get real engineering jobs, because there are actually a fair number of them who want to stick to engineering. They may go on to work at HP or AMD, and so forth.

Q: How large is the EE Department at Princeton?

Wolf: For Princeton, it's huge. In Electrical Engineering, we have the single largest graduate school enrollment - around 200 students. Those are mostly PhD candidates. You don't have to get a masters [in the process of getting a PhD], but you can get one if you want to.

Q: Is there cooperation between the EE and CS Departments at Princeton?

Wolf: We do get Computer Science students over here, and frequently the EE students go over there. I, myself, have a courtesy appointment in Computer Science.

Q: Where do you think Princeton is ranked among the various EE programs in the U.S.?

Wolf: Well, you talk to different schools and you get different rankings. I take those rankings [with a grain of salt]. At the graduate level, it's a lot more about the individual student and the individual researcher/faculty member [they're working under].

Q: What classes are you teaching currently?

Wolf: I have such a nice schedule. I'm teaching one class this semester, and I'll be teaching two next semester. A lot of my time is spent on research and writing proposals for my graduate and post-doc students.

Q: Where does your research money come from?

Wolf: The majority of the money at the moment comes from NSF, and some comes from the state of New Jersey as well.

Q; How has the enrollment of foreign students changed over the last several years?

Wolf: At the graduate level, we have more domestic students these days because of the economy. For a while, we were mainly getting students from the PRC, India and Taiwan, but those numbers had decreased. Now, they are starting to come back again. We also have students here from Turkey and Greece, and various other places in Europe.

Some of our foreign students are continuing to have visa issues, so we're very careful about sending them to international conferences. We always want to be sure they can return to the U.S. if they go [out of the country]. There was a while there, when we had some of our admitted students who were not able to get the visas they needed to come here to study. But, I hear rumblings that it's starting to get better.

Q: Have you seen a decline in overall enrollment in Electrical Engineering, as has been noted nationally?

Wolf: Yes, there has been a small decline in EE, but that [has stabilized]. A couple of years ago, financial engineering was au courant - trading algorithms and operations engineering. But, I think that has changed again.

Electrical Engineering departments face some very serious issues today. Most are going through some kind of identity crisis - whether they admit it or not - about what EE is and where it should go. I don't have the answer yet, but I think departments should talk among themselves, and the funding agencies, about where this field is going. Electrical engineering isn't in any danger of going away, however. I think that even after Moore's law, there will be [progress that can be made]. I feel strongly that we can exploit the transistors we've got today, for quite some time to come.

To that extent, I'm a bit contrarian. And, I certainly believe we don't have to abandon the existing fields in EE. For instance, you would think there are a lot of interesting problems in power. Certainly you have to ask, would Thomas Edison recognize all of the parts of the modern power grid? He probably would, but nonetheless, there are still good schools that [are actively engaged] in research into power systems. The power grid is one of those existing technologies that people, in general, don't really care about it. They don't want to know what's behind their power [distribution system]. They just know they want it to work. However, there are still many problems that need to be addressed in that area.

Q: What are the principle areas of research in EE at Princeton?

Wolf: There are people here who specialize in signal processing and in computer engineering. The real cutting edge today is biological machines, and there is some very interesting work going on here as well in that area. Also, there is important work being done here in nanotechnology. For the students, however, we offer a fairly traditional degree in EE.

Q: What are your own areas of technical interest?

Wolf: I'm interested in the physical nature of computing - low-power, real-time performance, cost, etc. My PhD was on layout compaction, but I'm not doing physical design anymore. Generally, I work in embedded systems, which includes a lot of work related in some way to a 'smart' camera. The work requires looking at the entire system, from the application down to the chips.

A 'smart' camera is basically a camera with a processor and algorithms that analyze the image or video. One possible application might be that you would have a bunch of cameras to cover the different parts of a room. If you stand in front of one of the cameras, it will tell you where you are in the room. The camera can follow you, and the computation of your location will move with you.

Our original motivation was to create a 'smart' room, a meeting room that's covered with cameras that have full knowledge of everyone in the room. That's clearly one application, but it's not the only application for our systems.

The [larger question is] is - if you want to understand a space, for whatever reason, one camera would never be enough. You would need multiple cameras, which require a way to handle all of that data. You don't want to be dragging that data back to the server, so we put the processing near to the camera. That way, you can actually install and operate these systems in the field. We're trying to make a decision with this system. It's a form of distributed processing, and I think the most interesting question then is what do you do with the information you gather [using the system].

Maybe in certain systems, for instance, you don't actually want certain people in the room, however people might get into that room by 'tailgating' somebody else as they swipe their [legitimate] security badge and enter the room. Eventually, I would like to have some kind of system that says who are the bad guys, who are the terrorists - but as far as I can tell, it's not yet possible to relate general activity or body gestures to a psychological state. So, if you want to just watch somebody, and say they're suspicious - I don't know of any way today to do that as yet. Certainly we know that watching for certain things, certain behaviors, can be useful - but not from a psychological basis.

Smart cameras, in general, have a lot of different uses - medicine, emergency response, etc. Any amount of information on the upper floors of the World Trade Center would have made it safer for the responders on September 11th, for instance. Cameras are getting cheaper thanks to advances in VLSI, so [we're beginning to be able to] afford putting multiple cameras on a subject. [Going forward], when you build buildings, you could install this stuff during construction [and the capability would be there when you needed it].

In general, however, I always try to be agnostic about the applications of the research we do here.

Q: Do you know how Princeton handles intellectual property developed by their graduate students?

Wolf: As far as I understand the law, the students here at Princeton own their course work, but any sponsored work - funded research - is a different matter. John Ritter is the head of our licensing program and I believe he does a good job. There are a fair number of departments here at Princeton who don't generate any IP at all, so it's really a department by department thing.

Q: Did you ever consider staying in industry rather than pursuing a career in academia?

Wolf: I was actually in industry for 5 years (if you call Bell Labs the real world) before I decided to teach. It was a big decision to [transition to academia], but I think it has allowed me to have more of an audience for my ideas. If you want to show your impact inside of a company, there are actually only a limited number of people you can talk to about your technology.

I've always been interested in designing big systems. We used to worry about 10,000 rectangles, whereas now it's 100 million transistors. From that perspective, I'd probably be [looking at the same problems] if I was still in industry. Either way, I would have been interested in climbing the abstraction level. At a university, you have the opportunity to bang your head on the wall and learn some new stuff.

Q: Do you think there's less politics in academia than there is in industry?

Wolf: The main difference is that, if you lose in politics in a company, you get fired. Of course, there are politics in academia, but university politics are kind of like the battle for Stalingrad, whereas industry politics are more like guerilla warfare - the sort of thing where you're solving the problem of the day.

Q: What do you do with your spare time?

Wolf: I spend time with my 2-year-old, who's really interested in understanding things. I also spend time cooking - I do several different types of cuisines. Besides that, I'm working on the 2nd edition of my Embedded Systems Book. My textbook on FPGAs just came out this June. That one took me about one and a half years to write, but it wasn't entirely from scratch because it was derived somewhat from my VLSI book.

Q: You seem like a pretty serious guy, so I'm wondering if you ever tell jokes when you're lecturing?

Wolf: Telling jokes requires delivery, and I'm not sure I've got what it takes. Although, other people always seem to keep laughing when I'm speaking, so maybe I'm funnier than I think.

[Editor's Note: To learn more about Wayne Wolf, and to determine if he has a sense of humor, check out his website: www.princeton.edu/~wolf/bio.html]

"ESL & All That Jazz"

What follows here is my take on Jeff Jussel’s narration of the Celoxica slides on ESL. He walked through the presentation for me in early January, and I thoroughly enjoyed the presentation. Jussel’s a pretty serious guy, and I give him high marks for avoiding the let-me-insert-some-market-speak-into-this-explanation explanation. And, although you may not agree with everything Jeff has to say here, it’s clear that Jussel’s is one voice that will be part of the conversation on ESL that’s inevitably unfolding in the industry even as we speak.

**************************************

Celoxica’s Jeff Jussel on ESL …

“The focus in these slides is to give an overview of ESL - where does ESL fit into EDA? Presently, the EDA companies are in two camps. Either they’re moving into the physical side - the big guys w/ design suites for 90 nanometer and below - driven by Gary Smith or customer demands, or both. Or they’re companies like Celoxica - trying to attack the system-level space by developing tools for algorithm implementation.”

“Algorithms are the key to ESL design. It used to be, when I started designing, that a company was competitive because they were made up of polygon pushers who had developed their own, better, faster technique for doing a design.”

“These days, however, it’s more about - can I get my algorithm into place faster than my competition. An algorithm is the key to a product these days; it’s what’s driving the value. It’s no longer so much, can I make a design that’s faster and smaller - after all, at 90 and 65 nanometers, the pressure is off there - now it’s about - getting my algorithm implemented faster. And the algorithm is what determines if my HDTV, for instance, has a sharper picture and is out on the market faster than my competition. Or, can I get my robot up fast enough to save the Hubbell Telescope before it runs out of power. It’s these types of algorithm-focused problems that we’re trying to solve today.”

“So, what ESL really involves is something that’s very verification centric. Is the algorithm correct? The next question then, is the architecture correct, the implementation of the hardware? All of that revolves around the transaction-level model. That is what’s driving ESL; it’s taking the algorithm to implementation based on the functionality of that algorithm.”

“Standardization is helping out there, working in standard languages like SystemC. Also, taking a transaction-level model (TLM) and synthesizing it - doing it in a hardware implementation so you don’t have to break the verification flow with RTL translations - is helping out there.”

“Until recently, those sorts of things weren’t available. If you weren’t able to take your model and create hardware from that model, what you had to do was to take your best guess and implement by hand. That was a slow and painful process, but you gave the best guess of the architecture you needed to implement the thing. Of course, it took 6 to 8 months for the engineering to implement it in hardware and, of course, by the end of that time if something wasn’t right, you were just out of luck. No product and no market. You’d end up with an algorithm that wasn’t exactly correct and a design that wasn’t necessarily the best architecture.”

“All of this leads to the fact that the benefits for system-level design are that it allows you to get the best architecture in place, and to make sure that the implementation is optimal, without having to break the verification flow in doing it. With system-level design, you get accurate implementation of your algorithm and you can do it quickly.”

“So the crucial process in ESL is to develop the model, refine the model, decide what to implement in software and what to implement in hardware. You make architectural decisions that you’d like to be able to do on the fly, doing trade-offs through virtual prototypes using performance models. Then, from there, you determine what’s going to be in hardware and what’s going to be in software.”

“Of course, the ideal says you could take your algorithm implementation directly from the C model untouched, without having to write the thing in RTL - perhaps using FPGA prototypes and synthesizing directly from the C-based models. This kind of quick implementation of the algorithm leads to rapid prototypes that can verify the algorithms in the hardware even faster than simulations can run the C code. This algorithmic or “behavioral” synthesis is the enabler for ESL. This is the problem statement, the overall philosophy and the general direction that ESL is headed in. Understanding this problem provides a way to define ESL.”

“So, at this point we need to be able to define behavioral synthesis. A lot of the reason that ESL didn’t work the first time around in the industry is that people promised too much from behavioral synthesis. It was nothing more, at that point, than EDA alchemy. People were saying, ‘Our tool will translate C code into perfect hardware.’”

“But, that wasn’t realistic then, and it’s still not realistic. It’s just too difficult even today, and people are still smarter than machines. In the end, you can give the machines that do design a lot of help, and they certainly save a lot of time, but human intervention makes the difference between output that is trash and output that’s good.”

“C-based code can model algorithms at higher levels of abstraction, and there are now tools for implementing directly from that, but that’s not the same as taking C code and never touching it before getting a design out. Behavioral synthesis has to do with defining the process for getting from algorithm to implementation. To get to hardware, we have to add things like concurrency, timing, and data types. Both the tools and the users have to deal with these things.”

“Looking first at concurrency, behavioral synthesis allows you to take advantage of the parallel nature of hardware. In hardware, some algorithms can be made to run faster than on a processor by spreading out things to save time. But, how to tell what should be parallel and what should be sequential?”

“One explicit technique is for the user to specify in the code that we want this part of the design to be sequential, and we want this part to be parallel. Or, in some cases the tools can figure out the partitioning automatically. In general, the user will have to define the broad strokes in the code, and then give the compiler a chance to concentrate on the smaller things. In that strategy, user interaction defines the parallel portions of the design to achieve better results.”

“In SystemC, we’re using constructs like SC_METHOD - or SC_THREAD - to allow the user to explicitly define those parallel portions of the design. In SpecC or Handel-C - and, remember that our tools at Celoxica originated with Handel-C - there are “par” statements. The C code is by default sequential unless you insert a “par” statement to define what to implement in parallel.”

“Another challenge in system-level design is timing, because C code has no concept of timing in a hardware sense. So, behavioral synthesis has to be able to implement clocked processes. You can explicitly define the clock cycles, or you can do this through rules in the language, different constructs in the language. Or you can have the compiler try to achieve timing based on user-defined constraints.”

“Some tools try to achieve timing by adding proprietary statements or labels within the code, which tell the tool, for instance, “I need 5 clock cycles between labels A and B.” The compiler then tries to go out and meet those constraints automatically and responds with the results.”

“Our concept here at Celoxica is to give the user direct control using standard language constructs to get real designs out with deterministic results. For example, you can insert explicit timing within SystemC. Every time you want a clock edge, you put in a ‘wait’ statement. In that way, everything that happens between ‘wait’ statements happens on a particular clock cycle. In Handel-C, it’s a little different, however. It’s a rule-based language where an equal sign denotes a clock cycle. Every assignment with an equal sign advances the clock one cycle in sequential sections of the code. Assignments within “par” statements happen in one clock cycle. All of this thinking clears up the confusion, or in any case takes the focus off of the smoke and mirrors of empty ESL marketing promises - that promise that you can run your design from untouched C code and you’ll get a perfect hardware implementation out.”

“That promise is smoke and mirrors because you’re always going to have to deal with:

Concurrency
Timing/Clock domains
Interfaces
Data Types
Communications
Resource Sharing

and those are problems that every tool has to attack. It’s how to do that, which is being debated today so hotly within the ESL community.”

“At this point in my presentation, I describe how our SystemC and Handel-C tools compare with those from our competition at Forte Design and Mentor Graphics.”

“What we do at Celoxica is to provide direct user control from C-based code for really good results and productivity. Just as you can write good VHDL or good Verilog code - just as you can write bad VHDL or bad Verilog code - you can write good or bad SystemC code for synthesis.”

“In our tools, versus those from our competition, we have the philosophy that the user knows best here. The user will have complete control over everything. For concurrency and timing, we have the user explicitly define those things in their code. That makes the process standard, not proprietary, and means they can take their code and use it in the competition’s tools or use it in standard simulation tools. But, we have the user explicitly define the concurrency. We adhere to all the standard reference manuals here, but again - the user must explicitly define things so that we can get explicit control.”

“Based on this strategy, our tools can handle multiple clock domains, and can handle the interface between clock domains. Synthesis re-timing can help to optimize things, as well, so the user’s explicit definitions can stay at a high level.”

“In the tools from Mentor Graphics, they say you can use any old C code and their tool will synthesize. But the reality is, the user must add data for concurrency and timing, etc. in a GUI, and the GUI stores constraints provided by the users. Then the edited GUI output is synthesized. The downside to that approach is that you can only do a block-based design because the tool can only take in so much complexity before it’s too difficult to use. And, it won’t support multiple clock domains.”

“Forte Design’s tool, Cynthesizer, is a little different. It doesn’t use a GUI, but it uses command-based functions. Forte is trying to solve things heuristically, using trial and error to get the results out. The problem there is that approach also limits you to a fairly simple problem set, which again is block-based only. The other problem is that trial and error is random, so that one little change in the code produces a completely different result. That generates inconsistencies plus limits the user to a single clock domain.”

“So, we believe that what we’re offering is not EDA alchemy. It’s not smoke and mirrors, it’s a functional development and implementation scheme, and tools that allow you to split out the design into the hardware and the software. To do this in ESL, there are two tracks from algorithm to implementation. The first track is language based - system-level designers come up with the algorithm in C-based code and move through functional design, to architecture definition and analysis, to implementation. Celoxica provides some good solutions for going from specification to implementation, but of course by no means provides all of the possible ESL tool sets for this track.”

“The other track used by a different type of designer is the block-based approach. You’ve got IP that already fits into your design, so the system-level tools try to make use of that existing IP. The slides in this portion of my presentation indicate where we have tools in each part of the possible ESL tool set for each track, and where we don’t.”

“Celoxica at this point has also introduced some block-based design tools, but we know we have some holes there. There are holes today in the flows from every company that describes itself as an ESL design tools company. Customers today must partner with a number of different companies to get the full flow - to get all the way from specification to implementation for all possible types of design. That fact is another part of the reality and the debate on ESL that’s very important to point out.”

“In ESL today, no one company has everything. Of course, there’s marketing motivation to say, ‘Use us. We’ve got everything.’”

“But, people get confused when they hear a company say that and then find the reality is something different - which only adds to the problems and the misunderstanding. At this point, everybody has got to see themselves as only providing a piece of the overall ESL solution. I understand that Gary Smith is going to be conducting an industry wide conversation this year to try and establish a complete ESL flow. I would very much like to be part of that conversation.”

“At this point, as Gary Smith and Daya Nadamuni both acknowledge, Dataquest has missed some stuff in their ESL forecast. It’s as if they’re looking at the traditional CAD groups doing traditional RTL-to-GDSII design and seeing a slow-down there. From our perspective, however, that’s not where things are happening in ESL. From our perspective, progress in ESL is happening in other sectors where system designers have algorithms to quickly implement into embedded systems using processors, fixed and programmable hardware and board peripherals. And, from our perspective, ESL is definitely accelerating. That’s what our business and technology motivation is based on.”

"DVCon - Wally, Gary & Gabe"

Industry stalwarts orchestrate roadmaps to an unclear future

Chapter 1 - Mentor Graphics CEO Walden C. Rhines on Verification

Wally Rhines' keynote at DVCon - “Verification Discontinuities in the Nanometer Age” - was well received according to a lot of people in attendance. Rhines started by telling us that half of the design effort is in the verification, and not surprisingly there were 76 companies last year at DAC selling verification tools. There was also $47 million invested in 7 new verification companies in 2004. There are 12 sub-categories of verification tools within the EDA tool paradigm, and $1.18 billion is spent annually on verification, which is more than synthesis and place & route combined.

Despite all this effort, however, there's more bugs at each process node. At the current rate, Rhines estimated the hypothetical Pentium 10 will show up with 6,000,000,000 bugs in need of resolution. Ron Collete, per Rhines, says that 66 percent of every ASIC/IC design requires 2 or more respins. Bugs, Rhines said, want to track Moore's Law, but fortunately they don't. And why is that? Rhines said it's because the tools for verification get better enough fast enough that the trajectory of Moore's Law is not quite the trajectory of bug count. Nonetheless, the problems are enormous and growing.

Rhines posed the question asked by many, and then answered his own query: “How did the bugs get there? Engineers put them there.” Then he pleaded the case of the engineer. The methodology for design is wholly changing every 15 years and at this point, we're on the verge of yet another one of those changes. Rhines reviewed the history: source and drain design in the 1960's and 70's led to schematic capture and logic simulation from the 70's to the early 90's, HDL synthesis and simulation from the late ‘80s though to the early 2000's, and static timing analysis and equivalence checking from the 1990's to today. Given this history, can we know what's next? Rhines said, “Yes.”

He believes the verification of complex embedded blocks will constitute the biggest methodology shift since the move to HDLs, and the methodology shift will require change. However, even though technology changes quickly, people don't. Add that to that, the fact that EDA companies invest in tools, but designers invest in methodology - and you've got some serious speed bumps out on the straightaway in front of you. And we're bearing down on them pretty darn fast.

Rhines said that as we get to the point where the methodology is completely broken - although people rarely change, change will happen nonetheless. Assertion-based verification and functional coverage will be augmented by language exploration and increased availability of standards - and the next phase of the story will get underway.

With that background, Rhines moved into a detailed discussion of present and future realities in verification. He said assertions need to be everywhere and they'll require a lot of work up front. Expect to have 1 assertion for every 10 lines of code, he said. Why aren't people using assertions today? Well, they are, Rhines said, but the process is not standardized.

He credited PSL 1.1 and SystemVerilog 3.1a with going in the right direction there, and said those efforts mean the tool evolution is being enhanced as a result. He said that formal checking has a future and that model checking's just a year away. Assertions will be constrained for model checking, which will help with redundant verification cycles. Rhines said we need metrics and when everything's in place, “Model checking will take over the world.”

He moved to IP and showed a traditional S-shaped graph. He said things move slowly at the outset of a design project, and then at a more satisfying, linear clip mid-project. But progress slows to a crawl again at the end of a development project. He said experienced managers know that the last 5 percent of the gates that are designed today gobble up 31 percent of the project time. He said the situation's not improving and so, with respect to the verification portion of the process, you've got to adhere to the mantra:

“If it isn't verified - it's broken.”

Rhines endorsed a verification flow that includes simulation, formal verification, emulation, and testbenches - and then repeated that we've got to have coverage metrics to know how we're doing. Having laid out the plan, he then asked, “How do we get there?”

Again he answered his own question: “It's easy. Use coverage constraints built into PSL and SystemVerilog, simulation integrated with functional coverage to improve performance, and then develop new test strategies that require functional coverage, as well as random and constrained random testing - and coverage to determine what they've tested.”

Rhines said abstraction happens, so C synthesis tools are coming. ESL initiatives will produce tools that will eliminate RTL coding. And, if you can get design to start at the system level, you'll be able to make decisions based on an optimized partitioning of the problem - partitioning between the hardware and the software. Rhines also touched on platform-based design. Snapping together blocks of IP is intuitively pleasing he said, and commended the SPIRIT Consortium as a type of effort that was helping to move the industry towards that reality.

Rhines ended by declaring the roadmap going forward. In the near term, he said that the EDA tools vendors will support SystemVerilog and PSL. Farther out, designers will automatically determine the sequence of algorithms to apply based on the design, and based on the requisite testbench and coverage required. Farther out, simulation will run until complete coverage is achieved.

Rhines fielded one telling question from the floor after wrapping up his talk. How many additional designers can the world support, given predictions of higher levels of abstraction and more sophisticated tools and methodologies? He said with 50,000 ASIC designers and 500,000 FPGA designers - one could envision 5,000,000 system designers working with a palette of reconfigurable platforms and tile-based structures. That level of involvement, worldwide, Rhines said will be great news.

“Anytime you grow your user base, you grow the opportunities for creativity as well.”

Overall, the keynote offered a tidy, positive, and logical kick-off to DVCon 2005.

Chapter 2 - EDA Editor Gabe Moretti on Quality

Gabe moderated a panel - “Designing Quality In: The Better Design Paradigm” - and entertained discussion from Dataquest's Gary Smith, Jasper Design Automation's Harry Foster, Azul Systems' Kevin Normoyle, Intel's LimorFix, and Verisity Design's Andrew Piziali. The conversation was substantive.

Gabe started by suggesting that it was cheaper to avoid bugs than to find them and fix them. He called it crisis avoidance economics and asked what's so inhumane about asking people to build quality into their products. His panelists were ready to respond.

Andy Piziali said quality is a soft metric and instead, we should look at whether chips are produced on time. He said the timeliness goal requires an efficient design team structure, and that the structure requires separate design and verification groups. He also said that moving to higher levels of abstraction would enhance the overall design process, and commended Brian Bailey's concept of the Abstraction Bridge.

Andy said that EDA and IP vendors must work together to demonstrate IP quality and to annotate that quality within the verification plan. He asked why so much time is spent on functional verification, and said it's because it's hard. An automated verification environment would help but all proposals to that end, hinge on changing the culture that surrounds the verification process. He concluded that design for verification rules should be codified to prevent unverifiable, or difficult to verify logic design from being put forth in the first place.

Next, Kevin Normoyle stood up and spoke to the reality of design. He said that he'd yet to see any article in any magazine that describes how the design process really goes - that everything in print is misleading and glib, suggesting that design is an easy and straightforward process. Kevin said that post mortums on design projects are never published. He also said that if hardware designers start to think like the software guys, we'd all be going down the slippery slop demonstrated by Microsoft - the road that leads to buggy designs and an acceptance of all that represents.

Kevin said we need to get the tool vendors in sync, and in agreement, that quality is indeed important in designs and that if we could do that - the future would be big, indeed. That we could honestly look at 500,000,000 gate designs and celebrate the process of getting there. Then he pulled the rug out from under the vendors: “The tools don't matter. Individual people don't matter. It's the team that matters. Period.”

Kevin said you've got to have one carefully choreographed, well managed, well integrated, honest and organized team that includes everybody from the designer through to the verification guys and beyond. And, he said if you build a verification scaffolding into the design flow, you'll maximize on the skills set that everybody on the team brings to the effort. He was quite adamant about all of it and didn't seem to want to compromise on his vision. He said the end result would be intentional complexity in the products, not unintentional complexity in the product design.

Harry Foster said that 15 years ago, we had separate design and verification teams. But over the years, the verification testbenches have become even more complex than the designs. Despite that, few managers ever realize that you've got to schedule in more time for the verification phase of the project. So, clearly we need to explore the complexity of the specification much earlier in the flow. Harry's conclusion:

“We should optimize the process of design, not the outcome of the problem.”

We've got several ways to approach that end, Harry said. We need to look at the subsystems in the design versus verifying the integrated whole, and we need to look at the system (as in the software) versus the components of the system (as in the hardware). Harry said, unequivocally, the verification team must be part of the design team. And contrary to the popular contemporary urban legend, Harry said we're not doing design, we're doing implementation. And moving to ESL is not going to solve that problem.

If you're keeping score - at this point it's 1 to 2, Separate Teams (Andy) to Integrated Teams (Kevin & Harry).

So, now for the comments from Limor Fix. Limor presented an appealing spreadsheet with Abstraction level, Reuse, Incremental design, and Coverage down the left side of the matrix and How it's done today, How it'll be done tomorrow, Who's doing it today, and Who'll be doing it tomorrow across the top of the matrix.

The 16 resultant squares included: Row 1 with Design 1st, assertion later, Unified assertions (first) + design (later as needed), RTLers + Validators, Designers; Row 2 with Reuse as a starting point, Reuse without altering (accept NIH), Designers, and Designers; Row 3 with Validation begins late - when large enough blocks have been coded, Blocks of any size, Validators, and Designers; Row 4 with Design verification coverage + limited functional verification, More functional verification + unified functional verification/design verification coverage, Validators (mainly manual), and Designers (mainly automated).

If you're serious about following the reasoning here, please get out pen and paper. Draw the 4x4 matrix. Label the columns and rows per Limor's instructions, and fill in the 16 squares again per the instructions. Look at it for a long time and then compare the conclusions to Wally Rhines' keynote. More than settling the argument over Separate Teams versus Integrated Teams, the sensibilities in Limor's spreadsheet dovetail with the sensibilities in the Wally's keynote. And, if Intel and Mentor can be in that much agreement - there might be hope for the world.

That is - if we can first decide how to structure the development/verification teams.

Chapter 3 - Dataquest's Gary Smith on ESL

Gary's panel - “ESL Leadership: Can the U.S. Catch-up to Europe and Japan? - included Summit Design's Emil Girczyc, Forte Design's Brett Cline, HDLabs' Tony Chin, and Philips's Maurizio Vitale. Emil and Brett were speaking on behalf of the smaller North American ESL vendors, and Tony and Maurizio were chartered with presenting the view on the ground in Japan and Europe, respectively.

All told, it was a pretty depressing hour and a half, if you paid close attention to what people were saying.

Maurizio Vitale said that 5 years ago, Europe thought it was behind in the race to ESL, so they did something about it. Now they're in a leadership role in the technology, and as far as he's concerned - in a respectable race with Japan. Maurizio said the U.S. might as well give up now. It's too late, they've missed the boat, and in the end - the U.S. should just accept the fact that they've got just one fate awaiting them as a result of their delay:

To be the eventual home for global manufacturing.

Tony Chin said that in Japan, everybody's learning SystemC. Everybody. Nobody's holding back. It's a hot, hot, consumer-product driven market there and nothing can be done at the development speed required to compete in that market unless it starts, robustly, at the system level. He said that almost all semiconductor companies in Japan have products and plans in place that revolve around SystemC.

It's too late for the U.S., so give up now.

Brett Cline then had a turn. He said that RTL's clearly too difficult, so let's speed up the design process by going to SystemC and behavioral synthesis. He said that big chips and big systems require new thinking, and hinted that it's not too late for the U.S. to expand their horizons and confront the competition for global markets being presented by Europe and Japan.

Brett added that with 600,000 engineers graduating each year in China with degrees in engineering, that those of us in North America need to do something to address that threat. He said that something has got to be the move to ESL -

Now.

Finally, Emil Girczyc said the U.S. is not behind in ESL. Countering the viewpoint of his fellow panelists, he said the U.S. is working in ESL, it's just not doing it by way of SystemC. He said we needed to move past the narrow perception that the only definition of working in ESL, is to be working in SystemC.

Emil said you can't get from SystemC to gates, and that it's no faster to work in SystemC than it is to model in Verilog for higher levels of abstraction. And, besides - consider the fact that there's very little IP written in SystemC. So how is obsessing about SystemC going to help?

Emil said the over-arching problem in the U.S. is that the EDA vendors have a vested interest in the status quo. They're not pushing SystemC or ESL - instead, they're just protecting their existing products and the known flows that support those products. It's not clear that Emil's picture was any rosier, but he did establish a beachhead for the concept that:

ESL is not just about designing in SystemC.

It was indeed a pretty depressing hour and a half, if you sensed the implication that innovation, at least in the area of chip design, is moving off-shore (from a North American point of view) - possibly for good.

Gary Smith closed out the discussion, which included a lot of give and take from the panelists, by answering a multiple-choice question from the floor.

“Is the problem here that a) there's a bunch of obstinate old men in leadership roles in EDA that are inhibiting the move to ESL, or b) the U.S. doesn't actually need to be playing catch-up with Europe and Japan because ESL and/or SystemC aren't the only game in town.”

Gary answered matter-of-factly, “The answer is A - a bunch of obstinate old men.”

"An ESL State of Mind"

The questions posed in this article arise from a consecutive set of circumstances. First I had lunch with Simon Napper and Vindod Kathail of Synfora, and that conversation was quite compelling. Then I shared a cup of coffee with Shiv Tasker and George Harper of Bluespec. That was also a compelling conversation, in particular because Shiv and George were interested – although they disagreed – with the article published here in EDA Nation in January. That article was about ESL Design and featured comments from Celoxica's Jeff Jussel.

Finally, I moderated a panel about ESL at DATE in Munich that included spokesmen for Verisity, Cadence, MIPS, Synplicity, ChipX, and Xilinx. Again, it was a compelling conversation, but I think it would have been a more robust discussion had it included companies that actually position themselves as providers of ESL technology. Therefore, herein you'll find what I would consider a Dream Team Panel on ESL.

The 'panelists' represent companies that I believe do position themselves as players in the ESL market. The panel also includes one analyst and one IP company that uses ESL tools. The participants received the questions via e-mail and provided their responses via e-mail, as well. They were only allotted 600 words for their responses (although admittedly some ran long), so they were asked to skip the questions that were of lesser relevance to their particular message.

When next you have the chance, I would invite you to engage any of these people in person on the topic of system-level design. I think you'll see that these folks are definitely focused on the ESL State of Mind.

The Panelists:
Dataquest – Gary Smith, Chief EDA Analyst
Bluespec – Shiv Tasker, CEO
Celoxica – Jeff Jussel, Vice President of Marketing
CoWare – Mark Milligan, Vice President of Marketing
CriticalBlue – David Stewart, CEO
Forte – Brett Cline, Vice President, Customer Operations & Services
Ignios – Mark Lippett, CTO
SpiraTech – Simon Calder, CEO
Summit Design Automation – Emil Girczyc, President and Chief Executive Officer
Synfora – Simon Napper, CEO
The MathWorks – Ken Karnofsky, Marketing Director

The Questions:

Q.1 – Define ESL. Or perhaps it can't be defined?

Gary Smith, Dataquest – Electronic-system level (ESL) is the concurrent design of both hardware and software. This is the official Dataquest definition.

Shiv Tasker, Bluespec – The best definition I’ve heard for ESL is the design level above RTL. This embodies system modeling and high-level implementation activities. Whatever the definition, ESL solutions and flows should improve entire designs and a broad application space, not just sub-blocks in small niches.

Jeff Jussel, Celoxica – ESL is the methodology and tools that support the design of electronic products beginning from algorithmic software-based functional models, usually written in C. The flow begins with functional TLM modeling, then partitioning of the functionality across an embedded architecture, and finally connecting the C-models to an implementation flow in embedded software (compilers) or hardware (behavioral synthesis).

Mark Milligan, CoWare – ESL is an industry emerging between – and often before [in the design cycle] – embedded software and EDA. The difficulty in defining “ESL” is that we’ve been trying to define it in terms of a tool or set of capabilities, instead of realizing it is a new industry. Misnomers are typical with new industries. We use the analogy of the horseless carriage. The $500 billion automotive industry was originally defined in terms of older, familiar technology, rather than in the context of a major new industry. ESL shouldn’t be defined in terms of EDA; it is becoming a new industry with unique attributes.

Companies in electronic design are facing enormous cost pressures. Two ways out of that: create and maintain more differentiated designs, or cut costs (or both). ESL helps customers create and maintain differentiated designs – often through software. ESL is about software-dominated design. Underlying hardware features are driven by software, but both can be optimized simultaneously early in the architecture phase. It’s not just automating. It’s creating better designs with more value and lasting differentiation. ESL also better connects the design chain by connecting system architects to customers, RTL designers, verification engineers, and critically, to embedded software developers. This enables geographically separated teams to work better together.

David Stewart, CriticalBlue – ESL is all the stuff you need to do to design a product before you start writing RTL or stitching together RTL. The key thing about ESL is that it is implementation independent – major decisions about architecture and hardware/software partitioning have not yet been made and are still to be investigated. To emphasize the point, ESL must include software development. Most definitions of ESL are self-serving and cover a hideously constrained subset of the space, for example, SystemC to RTL.

Brett Cline, Forte – ESL by definition is “Electronic System Level.” However, in practical terms, ESL represents the next abstraction level above register transfer level (RTL). There are two main components to ESL which are hardware design and software design. Hardware design is typically done behaviorally.

Mark Lippett, Ignios – ESL is a technology which: enables the abstract architectural exploration of a system before making firm decisions about the software/hardware partitioning; enables efficient software/hardware co-design; offers a virtual platform for software development on a fast-executing model of a new hardware architecture. Although the first of these represents an exciting long-term opportunity for system design and realization, this does not seem widely available (or at least, used) at the moment.

Today, as system designers move away from the traditional "single processor + peripherals" architectures, ESL fulfills a vital role in providing a software development environment which is both fast and reflective of the complexities of the target platform.

Ken Karnofsky, The MathWorks – ESL is a collection of EDA technologies that aim to provide a more efficient way to model complex hardware. It aims to provide a higher level of abstraction for faster simulation and verification of those systems, and to enable pre-silicon software development.

The EDA Consortium uses the terms System-Level Design and System-Level Verification to describe similar concepts. They encompass software tools that capture, simulate, partition, validate, and verify systems that comprise both hardware and software, including interfaces to code compilation, logic synthesis, and logic simulation.

Simon Calder, SpiraTech – ESL is not a level of abstraction, as its acronym would suggest. I would argue that ESL is the evolutionary 'process' of raising the level abstraction in IC design, verification and test to somewhere above RTL. Any tool involved in that process can be called an ESL tool, or any company involved can be called an ESL company. (Therefore, pretty much every front-end company.)

Emil Girczyc, Summit Design – ESL is not just design above RTL, and it is not necessarily design in SystemC. ESL addresses and supports the design decisions made at the system level – system architecture tradeoffs, hardware/software partitioning, IP component selection and sizing, and system level verification of performance, power, and functionality. Historically, these issues were solved by simple static analysis using pencil and paper or Excel, but as system complexity, competition, and time to market pressures have increased, more accurate dynamic analysis is required.

Simon Napper, Synfora – In the broadest sense, ESL (electronic system level) design is about designing entire electronic systems (printers, cell phones, cameras, etc.) and meeting price, performance, and power requirements. ESL is not about designing only specific components such as processors, memories, and interconnects. In my view, ESL design consists of these steps:

* 1) System Definition – This is where an engineer defines the architecture of the system, including what goes into hardware and what goes into software; which CPUs, buses, and memories to use; what could be implemented using off-the-shelf IP and what requires development of new IP, etc. System definition requires an emphasis on modeling and analyzing performance to make the right choices.

* 2) Custom IP Design – Many (or most) systems need custom IP to meet price, performance, and power requirements. Designing custom IP is a significant component of the overall design in terms of design time and design cost. T he missing ingredient in ESL design is automatic implementation, or synthesis. RTL was an accepted level of design because RTL synthesis eliminated the need to create gate-level descriptions manually. Until there is a similar capability—creating RTL automatically from an ESL description—the adoption of ESL will not be successful.

* 3) System Integration and Verification – In this step, the entire system, including custom and off-the-shelf IP, is put together and verified for accuracy and performance.

* 4) RTL to GDSII – This is the traditional back-end flow.

Q.2 – Explain why you agree/disagree with Gary Smith's evaluation of the situation?

[Editor's Note: Gary Smith will be publishing an article in an upcoming issue of Chip Design Magazine that will layout his evaluation of the situation.]

Shiv Tasker, Bluespec – We were pleased Gary named Bluespec one of only three “must see at DAC” ESL synthesis companies last year. I’m not familiar with his evaluation, but will be interested in his assessment when he completes his current ESL flow work and would be happy to comment then.

Jeff Jussel, Celoxica – The definitions to date have been hardware oriented and have defined ESL as an extension of the existing RTL hardware design flow. ESL is a revolution, not an evolution and goes much further than simply bringing co-design elements to SoC designers. ESL brings the possibility of using custom hardware to applications that never could have used hardware before. In this way, it is opening EDA to markets that haven't historically included hardware designers.

David Stewart, CriticalBlue – I don’t agree that more ESL design is happening; I think it has been happening for as long as hardware and software have co-existed in electronic products. What I see is more automation being introduced into the processes, driven primarily by complexity and time-to-market pressures.

Brett Cline, Forte – Gary has shown clear insight in predicting that the market is moving away from RTL and that the next abstraction level is necessary for timely creation of complex systems. Gary is correct when he says that it is important for methodologies to exist for a design style to take off. Often design teams build on the RTL flow that they have by augmenting it with higher-level tools. This provides the advantage of the new tools while preserving the investment in the old tools.

Mark Lippett, Ignios – I cannot comment on the quantitative analysis in the SoC sector of Gary's evaluation. However, we have qualitative feedback from the engineering management in our target customer base of companies designing complex SoCs. There is a growing recognition that ESL is a mandatory part of the development of all new software programmable platform chips. Software development *has* to start before silicon is available. We have also seen cases where existing chips, which are shipping in volume today, are being retrospectively modeled in ESL environments to facilitate end-user software development and support.

Ken Karnofsky, The MathWorks – Gary has accurately identified the segments currently being addressed by EDA companies (both established and startups). He is also correct in acknowledging the increasingly important role of the system architects that The MathWorks serves, as well as The MathWorks market-leading share. He also acknowledges that ESL is a subset of “system-level design” (SLD), which encompasses both electronic and mechanical elements. In other words, ESL does not cover the whole system.

Many system engineers that The MathWorks serves are doing “full” system-level design – encompassing hardware, software, and mechanical systems, as well as the real-world environments that they operate in (e.g., communications channels, noise models, human perception) – not just the electronics. Others are developing signal processing and control algorithms, converting them to fixed-point, and evaluating their performance and impact on overall system behavior. These elements are necessary to make sure that the team is “building the right thing” (meeting requirements) and getting it right the first time (i.e., eliminating design flaws), as well as simply testing to find flaws later in the development process.

Simon Calder, SpiraTech – If I understand Gary, correctly, Gary's position is that ESL is about hardware/software co-design. This is hard to disagree with, but somewhat out-of-character, because I think Gary is understating ESL.

EDA has always been about reducing the time to revenue for semiconductor IC's. That is what ESL is about. Absolutely, making the software and hardware elements parallel tasks and not serial is a massive gain, but using higher levels of abstraction to hasten SoC and ASIC design, debugging, validation and verification has just as much impact if re-spins can be irradiated.

What has happened recently is that levels of abstraction that had been useful for only hardware/software co-design have been brought into the verification flow. This has been done by bridging the gap between those pure un-clocked transaction level domains with the perfectly cycle accurate world of registers, gates and transistors.

Simon Napper, Synfora – Gary Smith is stirring the pot. He’s encouraging thought and determining whether there is a consensus. I think that there are some pieces missing from a comprehensive and effective ESL methodology. And I’d argue that synthesis is the big piece that is missing. It’s high-level synthesis that will define and drive the deployment of ESL much more broadly than where it stands today.

Q.3 – Does working in SystemC = Working at the ESL level?

Gary Smith, Dataquest – No. You can do RTL design with SystemC. It's a dumb idea, but you can. Also, you can work at the ES level with other languages. For instance, C and e have been used for years. The first ESL designs were actually done with VHDL.

Shiv Tasker, Bluespec – Working in SystemC is, well, working in SystemC. As with many languages, you can work with SystemC at different levels, from ESL to RTL. TX modeling and testbench development with SystemC may be ESL, but synthesizable SystemC is almost always RTL.

Jeff Jussel, Celoxica – SystemC as a modeling language is part of the ESL flow, and coupled with behavioral synthesis serves as an implementation language for the 'back-end' of ESL where the algorithms are connected to existing hardware RTL flows. However, simply adding a SystemC interface does not make a hardware design tool suddenly part of the ESL flow.

Mark Milligan, CoWare – Working in SystemC does equal ESL. But ESL doesn’t necessarily always equal SystemC. Algorithm and embedded processor development aren’t necessarily done in SystemC, and they are definitely part of ESL. Embedded software isn’t written in SystemC, yet modeling for ESW development is a main driver for SystemC.

David Stewart, CriticalBlue – No. SystemC is a hardware modeling language. Assuming you want to use SystemC, there’s a lot of ESL activities before you get to the point of wanting to model your hardware (see definition of ESL above).

Brett Cline, Forte – Technically, working at the ES level (or at ESL) is not the same as SystemC. However, SystemC is the glue that links the methodology together. SystemC provides the starting point for design modeling as a superset of C/C++, easily supports verification with a defined simulation standard, supports implementation with SystemC synthesis tools such as Forte’s Cynthesizer, works with the latest in debug and analysis technology, etc. Because of SystemC, leading edge products from several vendors easily work together. ANSI-C and other C dialects are locked to proprietary vendor products.

Mark Lippett, Ignios – No, SystemC is not necessarily equivalent to ESL. In theory SystemC can be used to reflect an RTL abstraction, so it is vital to remain cognizant of the target abstraction level when writing SystemC.

In many ways SystemC is not the ideal choice for ESL. If we agree that ESL should enable us to establish a software/hardware partition, then in an ideal world the ESL programming model would be seamlessly compatible with the hardware or software development flow. This should mean that at least some of the results at the ESL level would be directly reusable in the final product. However, at present, SystemC is neither of these – it is not a pragmatic route to gates, nor is it a recognized kernel for runtime software.

Notwithstanding the programming model differences, SystemC is not a new language. The principal advantage of SystemC is its empowering effect on the comparatively huge amount of expertise in the software engineering community who, with the advent of ESL tools, are now capable of defining functionality which may ultimately be embodied in hardware.

Ken Karnofsky, The MathWorks – Certainly not. SystemC addresses a subset of the ESL challenges facing electronics manufacturers, and a smaller subset of the problems facing embedded software developers. In fact, it has been proven that Model-Based Design with Simulink, including automatic generation of C code, produces more efficient, reliable software with dramatic reductions in development time and effort. FPGA engineers are finding similar benefits using Simulink and third party automatic RTL generation tools. In addition, SystemC does nothing to address the needs of analog and mixed-signal engineers who need to work at a higher level of abstraction and collaborate ever more closely with digital designers.

Finally, choosing SystemC as a system design language is based on a false premise: that system architects choose C because it is somehow a more productive approach. In fact, most choosing that approach do so because it is freely available, not because it is productive. Adding classes and a scheduler masks the issues. C, C++, and SystemC are too low level to do system-level design productively. This has been demonstrated by the order-of-magnitude productivity gains engineers achieve when they move to Simulink and Model-Based Design to specify, implement, and verify systems.

The answer is to specify and verify designs with executable models, and then generate the code automatically. The previous leap in productivity wasn’t achieved by incrementally improving logic design (or assembly code for software) – it came from a leap in abstraction to higher level languages, accompanied by synthesis and compiler technology. SystemC does not provide the requisite leap for the next generation.

Simon Calder, SpiraTech – Yes and No. It is difficult to imagine anyone using SystemC who has not embraced a methodology that uses levels of abstraction higher than RTL. But please remember SystemC can be and is being used to make RTL style models. They run faster than Verilog or VHDL, but not much. By my definition this is not ESL as the level of abstraction remains unchanged, this can only be considered accelerated RTL. SystemC does appear to have become the modeling language of the transaction levels.

Emil Girczyc, Summit Design – NO! Please see my answer to Question #1.

Simon Napper, Synfora – ESL refers to how to design complex systems (or SoCs) in a limited amount of time with limited resources. SystemC, on the other hand, is a specific language, and possibly a specific methodology, that is good for system-level modeling and verification (used in Step 1 and parts of Step 3). There are multiple languages available for this. Some people use MATLAB for system modeling, and there’s nothing wrong with that. In fact, Gary Smith has just added MATLAB and related tools as one of the groups he tracks to measure ESL revenues.

SystemC is a subset of ESL. People are grasping for a sound bite to encapsulate ESL, and for a lot of people that’s what ESL means. I think that two years from now, it will be understood to be a component of ESL.

Q.4 – Should the conversation about ESL be language neutral? Is that possible?

Gary Smith, Dataquest – Yes and no. We had a lot of RTL languages at one time (for instance, iHDL, nHDL, etc.) However, Verilog put the methodology on the map. SystemC has done the same for the ESL Methodology.

Shiv Tasker, Bluespec – The conversation about ESL should not be restricted to one language, just as RTL isn’t just Verilog. Certainly syntax is not directly relevant, but semantics is crucial (e.g., elaboration, static checking, computation models, composability). While the ESL conversation should be language-neutral, it won't be to the extent that certain semantic ideas are only expressed (easily) in some languages.

Jeff Jussel, Celoxica – Languages are part of the 'religion' of EDA and as such are always hot topics. The ESL languages define important modeling and implementation capabilities, and as standards provide much needed portability and reuse. However, the discussion of ESL goes beyond languages (and tools for that matter). We deliver ESL flows with multiple language support.

David Stewart, CriticalBlue – ESL has nothing to do with languages. Any language which relates to some part of system design prior to implementation is relevant to be included in an ESL discussion; such a discussion need not be language neutral, it should just be language inclusive. The idea that there will be a unified language of ESL (as per my definition in #1) is ridiculous.

Mark Lippett, Ignios – From an idealistic perspective: Yes. From a practical perspective: No. A common language is needed for both software and hardware in order for functionality to be migrated from one domain to the other in the ESL space. There are far too many barriers to the adoption of an HDL in the software engineering community. Therefore I believe that the hardware community will have to rise to the challenge of C/C++ based modeling. This does not necessarily mandate the use of SystemC in particular, but this would be the most pragmatic choice today.

Ken Karnofsky, The MathWorks – The discussion should be about capabilities and methodologies that are needed to solve customers’ problems. A debate about which language is best suited to specific tasks is a productive exercise.

Simon Calder, SpiraTech – Yes and Yes. Raising the level of abstraction suggests a simplification, but as everyone knows simplifying things is a complex process. ESL is no different. There are so many things to be done in raising the level of abstraction that no one language can do it all well. Any language that saves time and money will justify itself, as long as it is not maintained as a monopoly by a single vendor.

Emil Girczyc, Summit Design – Ultimately, customers decide what will work best for their projects and within their particular flows. If a customer is already working in a C environment, then the move to SystemC would likely be natural and preferred for ease of use and functionality. DSP designers would likely use Matlab for their algorithmic development, but today's system design and verification is not just about signal processing.

Simon Napper, Synfora – ESL is a solution to a problem. The conversation should be about defining the problem and how ESL could solve it. To us, the problem is productivity and the cost to complete a complex SoC. We focus on which flow a designer is trying to operate, and how is it helping to increase productivity and reduce the cost of a design.

Q.5 – Are the current standards efforts with regards to SystemVerilog warranted if we're all just going to move to SystemC?

Gary Smith, Dataquest – Yes, Verilog badly needs upgrading and SystemVerilog is that upgrade. SystemVerilog is an RTL language, not an ESL language, so the two will co-exist.

Shiv Tasker, Bluespec – While SystemC is gaining use for functional modeling and testbenches, the path to RTL is murky at best. I suspect hardware designers would be quite surprised to hear that we're all just going to move to SystemC. From their viewpoint, it offers nothing compared to SystemVerilog (and some would argue SystemC’s a big step backward).

Mark Milligan, CoWare – Improvements to Verilog such as SystemVerilog shouldn’t stop. This development is warranted for incremental improvements to the implementation and verification process. More automation for EDA is good; getting dramatic design differentiation using ESL is great.

David Stewart, CriticalBlue – It’s not about languages. If some people want to use SystemVerilog versus SystemC, let them get on with it. In the end, if the language works for them and the tools exist that get them to market on time, it’s a solution. It’s just important to remember that getting from SystemVerilog or SystemC to RTL is typically a small piece in a big puzzle.

Brett Cline, Forte – Yes, but for RTL implementation and verification. SystemVerilog is the next generation of Verilog and provides a good starting point for RTL-based design. Even though the leading edge customers are moving to SystemC, RTL design will still have a place for some customers for the near future.

Mark Lippett, Ignios – I see SystemVerilog as a useful extension to existing RTL design languages, not as a candidate for ESL design (at least, as defined above). As a semiconductor IP company with a synthesizable deliverable, we have to be conservative in our expectations of our customers' integration and synthesis flow. So, in the short and medium term, Verilog and derivatives are the only pragmatic choice for synthesis. Whilst that is the case, SystemVerilog will provide value in lower level hardware embodiment and testing.

Simon Calder, SpiraTech – Many customers believe that SystemVerilog is best for designing test benches and if nothing else it has the potential to make the whole RT Level run better, which in itself is important. SystemVerilog has an important role to play even though SystemC appears to have won the TLM battle.

Emil Girczyc, Summit Design – The two languages serve different needs, though some confusion about SystemC for use at the RT-level did take up much press at one time.

Simon Napper, Synfora – They have taken on a life of their own. The focus of ESL should be on significantly boosting designer productivity.

Q.6 – Aren't there always going to be problems using C-based languages to describe parallelism?

Gary Smith, Dataquest – Coming up with a Concurrent Software (C ?) Compiler is the most important breakthrough technology needed for ESL Design.

Shiv Tasker, Bluespec – 'C-based' encompasses two orthogonal approaches, with different characteristics and issues:

* 1) Automatic parallelization of sequential C: Yes, there will always be problems deriving good, parallel hardware implementations from sequential C code, as demonstrated by 50 years of research on this topic. Researchers in the general computing field of parallel programming have largely abandoned this superficially seductive goal. EDA just hasn’t fully caught on yet.

* 2) Explicit parallelism (e.g., constructs like SystemC's SC_THREAD etc.): Synthesizable, but code is at no higher level than RTL (and often messier).

With # 1, expressing a function is easy; producing good hardware is hard/impossible. The only exception is a small class of vectorizable/VLIW-mappable algorithms, those using tightly nested FOR-loops with simple, linear indices (e.g. FIR filters). But, what % of design is addressed by these code fragments?

With # 2, expressing a function is hard; producing good hardware is no harder than current RTL synthesis. Transaction-level SystemC models require fundamental rewrites for effective hardware synthesis – the concept of smooth refinement to RTL is ridiculous, as sequential algorithms are completely different from parallel ones.

Jeff Jussel, Celoxica – We use C languages because they are good at describing algorithm behavior at a high level, and because they are the language in common for programming embedded processors. C-based implementation languages such as SystemC and Handel-C add the constructs needed to deal with concurrency, timing, interfaces, and other hardware-oriented requirements without losing the high-level advantages of the software-based language.

David Stewart, CriticalBlue – That’s a hardware-centric statement typical of many EDA companies. If you are trying to force fit a general purpose, feature rich but sequential language like C into the parallel world of hardware modeling and implementation then yes, you will have to impose language subsets and coding styles. Note how many vendors support “ANSI C”, i.e. the subset of C and coding styles they support is ANSI compliant!

One of the EDA industry’s biggest opportunities is to capitalize on the explosive growth of embedded software content in today’s electronic products. To do this, they have to recognize, as we have, that the embedded software developer will not tolerate being constrained by modeling guidelines or solutions which don’t allow them to express themselves in unconstrained C/C++. Hardware centric solutions will appeal to RTL designers trying to gain productivity by moving up in abstraction level, but will not grow the EDA market into the embedded software sector.

Brett Cline, Forte – This problem definitely exists for ANSI-C, but not with SystemC. SystemC is a C++ class library. That means that SystemC inherits all of the power of C++ (and essentially C) while also implementing additional abstract concepts such as parallelism, clock accuracy, and bit accuracy necessary to accurately represent hardware.

Designs written in SystemC can have explicit parallelism without hokey proprietary pragmas used to describe things that should happen in parallel.

Mark Lippett, Ignios – It depends whether you wish to explicitly build a "structural" model of a parallel system and then execute code on top of that, or whether you wish to take "algorithmic" C code and infer parallelism from that. I don't doubt that considerable progress will be made in developing "parallel compilers" that extract instruction-level (perhaps even thread-level) parallelism from algorithmic code; however, this is some way off. In the meantime, ESL-based methodologies that use C-based languages to explicitly define a parallel architecture are being used extensively and with considerable success.

Ken Karnofsky, The MathWorks – In order to do so, you force the C code to look like HDLs. This satisfies neither the software developers nor the hardware designers. Simulink, in contrast, has built-in semantics for modeling and simulating real-time, concurrent, multi-rate systems. Simulink models map naturally to hardware and embedded software implementations.

Simon Calder, SpiraTech – We at SpiraTech like to think we have solved some of them.

Emil Girczyc, Summit Design – A variant of C is the most successful HDL because Verilog is a C-based language in the most general definition, and SystemVerilog is adding more C/C++ concepts to Verilog. The HDL dataflow programming style tends to be used at a fairly low level for logic description. The most common HDL coding style is a sequential, procedural programming language with a few parallel (e.g. process) and hardware (e.g. generate) statements. Getting similar constructs right in a more vanilla C context can have similar success.

Simon Napper, Synfora – Your question addresses the core issue of moving to a higher level of abstraction. ESL is trying to increase designer productivity, and increasing productivity means that the tools have to do more of the work. If the tools cannot automatically infer and exploit parallelism, ESL is not going to be an effective solution. There will always be benefits to an experienced designer guiding a tool, but the bulk of the work has to be done automatically.

It also depends on if one is describing a system in terms of functionality or as a collection of hardware components. A system as a collection of hardware components requires a method for describing parallelism, whereas functional descriptions can stay with C for a large part of a system. There are places in system description, especially at the highest level, where you do need an explicit way to describe parallelism, since the description at these levels is more as a collection of components.

Q.7 – How close are we to getting from SystemC to RTL, or is this perhaps the wrong question?

Gary Smith, Dataquest – If you mean automatically, we still have a ways to go. Hopefully, it will be here in two years. Until then, we'll rely on mapping.

Shiv Tasker, Bluespec – More accurately: how close are we to synthesizing good hardware from “high-level” SystemC? Synthesizing good hardware from RTL-level SystemC is easy, but there's no benefit.

It is questionable whether SystemC offers anything in its semantics that makes it easier to synthesize good hardware from high-level descriptions. High-level models must be manually re-written at an RTL level for synthesis. C-based synthesis enhances niche applications: Vectorizable/VLIW-mappable applications can be synthesized, but are a narrow application space. For the rest, SystemC synthesis is an RTL level tool.

Jeff Jussel, Celoxica – With the Agility SystemC synthesis tool, Celoxica has an existing path from SystemC to RTL. But maybe the question implies will SystemC replace RTL? The answer to that is "No." SystemC is used at higher levels of abstraction, but will not replace RTL any more than RTL replaced gate-level design.

Mark Milligan, CoWare – It’s the wrong question. We are talking about a fundamental difference in designs with SoCs versus ASICs with RTL where synthesis was the critical enabler. Now, designs can have hundreds of IP blocks and the challenge is connecting them and designing-in that key differentiation. This must be done with SystemC.

If the question is, “is behavioral synthesis going from SystemC to RTL and are we there yet?” that will be useful, and we’re getting there, but the real key for success is SystemC modeling for IP reuse in SoC designs.

David Stewart, CriticalBlue – It’s the wrong question, unless you happen to be an RTL designer looking to gain productivity. The right question is when will software tool solutions be available, which automate key parts of the manual system design processes that have been used for many years.

Brett Cline, Forte – Perhaps it is the wrong question, because we’re already there. Our customers use SystemC to model their designs and use our Cynthesizer SystemC behavioral synthesis to create hardware in a fraction of the time with better results. They are seeing greater than 50% reductions in time-to-RTL with 33-50% of the resources necessary – with better results.

Maybe the right question is – if this technology already exists and my competitors are using it, how much of a lead do I want to give them while I wait for it to become ‘mainstream’? Of course, I realize that this sounds pretty cynical.

Mark Lippett, Ignios – Focusing on SystemC as a route to RTL is not the wrong question - it's just not the whole question. Referring back to the classification of "structural" and "algorithmic" views of C-based languages in the answer to question 6, there are certainly companies claiming to offer SystemC to RTL *automatic* translation for "algorithmic" descriptions. How efficient these are, and how large the class of applications to which they can be applied, remains to be seem.

Nonetheless, if we look at the structural view of SystemC, this allows the *manual* migration from a fast-simulating SystemC model, which can be rapidly refined, to an accurate RTL implementation, through the use of a common verification suite. This latter approach might be manual, but it is potentially very productive; this is the approach that we use internally for developing our IP cores.

Ken Karnofsky, The MathWorks – The question is whether C or SystemC is the right entry point for design. We contend that it is not, because it is too low a level of abstraction for effective design space exploration, analysis, and optimization. Untimed C has additional problems, because there is no way to simulate the design to validate timing or functional behavior.

Simon Calder, SpiraTech – We are there today. But I suspect your question is; 'How long is it before the RTL to TLM relationship is the same as the Gate Level to RTL relationship of today' If so, my answer is 5-10 years.

Emil Girczyc, Summit Design – There are several viewpoints, but two relevant ones are "We continue to get closer." and "It doesn't matter." "We continue to get closer" with advances in high-level synthesis tools, but more importantly in methodology for IP reuse. If an IP developer (internal group or commercial vendor) delivers a SystemC model for their IP, there is a direct, and effective, path from SystemC to implementation.

This is consistent with traditional system design at the PCB-level based on existing chips. As design teams adopt greater design / IP reuse, the path from SystemC to RTL is implicitly available for an increasing amount of the design. "It doesn't matter" if the value derived from ESL modeling of the system provides enough value in and of itself. This is becoming true for architectural analysis of large systems, and for embedded SW developers who depend on high level models of the HW to get enough simulation cycles to debug their software.

Simon Napper, Synfora – How to design custom IP most productively at the lowest cost is the right question. There is debate about which is the correct language for synthesis, and the real questions are: What does a practical ESL synthesis capability look like? And, How does it fit into the flow?

We argue that, in consumer electronics, the starting point is complex reference algorithms such as H.264, imaging pipelines, etc. written in C. The synthesis tools should take sequential C, infer parallelism automatically, and then automatically generate SystemC models to validate multi-threaded or parallel behavior.

Q.8 – Are Asia and Europe ahead of the U.S. in ESL? If so, why should the U.S. care?

Gary Smith, Dataquest – Yes, but only in the algorithmic ESL methodology. There are other methodologies needed to complete ESL Design.

Mark Milligan, CoWare – Europe and Asia have definitely been ahead of the U.S. in adopting ESL methodologies. But within the last twelve months, U.S. companies have made great strides with pilot programs. The U.S. should care because ESL offers huge opportunities in creating software-differentiated designs and improving the design chain.

David Stewart, CriticalBlue – It’s slightly amusing to me that a successful and powerful nation such as the USA spends so much time pondering about whether they are getting left behind in design methodologies such as ESL. This is usually the behavior of a small, less developed country! My advice: design cool products, and use whatever flows, tools and methodologies you need to get the job done. If that includes ESL then great. However as long as you are designing cool products at good prices on the market at the right time, you’ll be just fine.

Brett Cline, Forte – Yes, the U.S. is behind Asia and Europe. We should care in the U.S. because we are struggling to find ways to make our products more efficiently to try to keep a competitive edge, both in functional concepts and price. Our goal has to be to design better products in less time by making our engineers more productive and the relative costs the same. We need to be the innovators – but at the right cost. In Japan, there are multiple methodologies that exist today and hopefully over time these will flow to the U.S.

Mark Lippett, Ignios – Well, that certainly seems to bear out our own experience. We use ESL tools with our customers to explore the capabilities of new chip architectures that include our IP core. We've spoken with design groups around the world. We see far more extensive and advanced use of ESL outside the U.S., but I cannot claim that this has anything other than anecdotal relevance. The U.S. will have to decide for itself if ESL is relevant.

Simon Calder, SpiraTech – I think superficially the answer is yes. The Asians and Europeans appear to have embraced a more 'Drains Up' approach. But if you analyze it further, what has really happened is that they have just been more willing to use the early ESL offerings from the EDA industry. In reality, many U.S. end-users have been using highly sophisticated internally developed tools and methodologies for years. My belief is that the U.S. customers will move rapidly when they see that there are tools available that really will save them time and money, like they did with Verisity.

Emil Girczyc, Summit Design – Europe and Asia have adopted SystemC to a greater extent than U.S. companies, largely because they moved to ESL after SystemC existed and have a stronger belief in standards. However, U.S. companies are accomplishing many of the same tasks using C and C++. In many cases, the lack of adoption of SystemC in the U.S. is because U.S. companies became adept at performing ESL tasks in C/C++ and, having a working methodology, see no reason to change. Once more commercial tools based on SystemC demonstrate their value, design teams in the U.S. will be quick to adopt them, as quick, or quicker than their counterparts in Europe and Asia.

Simon Napper, Synfora – It’s not clear that the U.S. should care, unless a lack of ESL capability hurts productivity and makes it less competitive. We are still in the early days of deployment, and despite all the talk about ESL, there will continue to be reluctance by design groups to adopt ESL until an effective and automatic way of generating custom IP is established. Once that is established, companies will be driven by competitive issues to get on board with ESL.

Q.9 – Are European companies forced to guarantee employment for their employees, and therefore forced to move to new technology paradigms in order to find something for everybody to do?

Gary Smith, Dataquest – Come on Peggy, you can do better than that!

Mark Lippett, Ignios – No, although it is tempting to think that labour laws are the same for every country in the European Community, this is not the case. In the U.K. we are certainly not required to guarantee employment, which is one reason why the UK has a comparatively vibrant startup community.

Simon Calder, SpiraTech – In the last downturn, there were certainly European companies that had more engineers than their surviving projects nominally required. This talent was focused on projects with longer term productivity gains in mind. I believe the U.S. companies cut back deeper and did less longer term methodology planning. That is changing rapidly and we see U.S. companies putting more energy into their design methodologies.

Simon Napper, Synfora – No. We are all competing worldwide and there are no places to hide. Europeans are well aware of this and they are looking to boost productivity to remain competitive. That’s why they also are focused on the promise of ESL.

Q.10 – In other words, is productivity in Europe & the U.S. versus that in Asia the real question here?

Gary Smith, Dataquest – That has a place, but the top priority is increasing functionality.

Brett Cline, Forte – Productivity directly relates to cost and our costs are generally higher than the costs in Asia.

Emil Girczyc, Summit Design – The real issue to ESL adoption is not productivity, but rather one of risk versus perceived value and need. The large companies in Europe and Asia still have central CAD organizations chartered to investigate and adopt new tools and methodologies (often before they are fully mature). To convince U.S. companies with no or a small central CAD group to adopt new tools and methodologies, the value of tools must be quickly demonstrated and the risk for use on a real project must be low.

We see our customers adopting ESL on the basis of the needs of their project. In Japan, the high integration of IP within the consumer electronics space is clearly being served by ESL. In Europe, wireless device development calls for ESL. In the U.S., the networking companies are modeling entire networks with ESL. Again, it's a difference in project focus and needs for modeling, design and verification.

Simon Napper, Synfora – Productivity anywhere to compete everywhere is the real question.

Q.11 – Shall we let Asia have the consumer electronics market and find other markets for the U.S. and perhaps even Europe to pursue?

Gary Smith, Dataquest – Not out of the question. "Consumer market" and "profits" don't always fit into the same sentence.

Brett Cline, Forte – That is an option, but I don’t believe that Intel, Motorola, HP, Broadcom, Qualcomm, TI, Apple, Cisco (Linksys), PalmOne, Creative Labs, NVidia, ATI, Microsoft, and others would concede that.

Simon Calder, SpiraTech – The U.S. still dominates, processors, DSPs, communications, graphics, digital music and embedded operating systems. Try and make a consumer product without any or all of those! I believe that in 5 years time at least 75% of ASSPs will have a mass-market consumer use. The big brand names may become exclusively Asian and European, but I will not bet against the U.S. semiconductor companies maintaining if not increasing their market share.

Simon Napper, Synfora – Good luck. I don’t think U.S. and Europe can afford to cede that market unless they are willing to tank their economies in the short term. For the next few years, the consumer market is going to drive semiconductor volumes, tools, and methodologies. The U.S. has been in this position before – behind the eight ball – and has always managed to compete.

Q.12a – Where is the ESL market? U.S.? Asia? Europe?

Gary Smith, Dataquest – All of the above, but it's somewhat methodology dependent.

Q.12b – How does your company play in the ESL market? Which market is that? U.S.? Asia? Europe?

Shiv Tasker, Bluespec – Bluespec is re-inventing hardware design. Bluespec's tools deliver substantial productivity improvements in the design process for all applications whether control or datapath dominated. Its strong semantics (elaboration, static checking, state and concurrency model, interfaces and composability) permit smooth, correct refinement from abstract, "transaction-level" models down to a level that, while still substantially higher than RTL, can be synthesized into high quality hardware.

While other approaches may offer benefits to some sub-blocks within a design, Bluespec accelerates the entire chip design process. Bluespec is engaged with customers in the U.S., Asia and Europe.

Jeff Jussel, Celoxica – Celoxica sells ESL tools to system designers where the value in the system is the algorithm and where time to market is a priority. Our customers are in diverse fields including military/aerospace systems implemented on FPGAs, consumer applications using structured ASICs, and embedded systems used to accelerate software for security or medical imaging or genome processing to list a few.

Some of these customers are software designers, some are hardware designers, and some are algorithm experts with no implementation knowledge. The one thing they all have in common is the need to quickly implement a software algorithm across both an embedded processor and custom hardware. This holds true across geographies with about 40% of our business coming in Japan/Asia, 35% in the U.S. and 25% in Europe.

Mark Milligan, CoWare – CoWare enables customers worldwide—in the U.S., Asia, Japan, and Europe—to rapidly create differentiated algorithmic-, processor- and software-centric SoC designs. In 2004, we believe CoWare was the seventh largest EDA company. The larger companies are public with predicted growth rates of 20% or less. CoWare’s predicted growth rate is much higher, making us one of the fastest growing companies.

We believe this growth results from a focus on ESL versus the “automating the automated” focus of traditional EDA companies. The software effort overtakes hardware at 130nm, and the architecture effort overtakes physical design at 90nm. ESL will only continue to grow in importance.

David Stewart, CriticalBlue – At CriticalBlue, we have focused on the U.S. and European markets for now. We also believe that Asia (especially Japan) will also be a very good market for us. Our Cascade product is generating significant interest because it works within existing software and hardware development environments but also delivers dramatic improvements in development time while retaining a degree of software programmability. The architecture, implementation and management of programmable systems is the way forward because it ensures a route from generic embedded software. Some day, all products will be designed this way…

Brett Cline, Forte – Forte is leading the charge in ESL by allowing designers to move up in abstraction level. People have been using higher-level languages for verification for some time now, but actual design is only now enabled by viable high-level synthesis like Cynthesizer. We’re leading the market in this area with more than 75 designs completed, more than 10 currently in production now, and several tapeouts already done. This is how to drive change and that is what Forte is doing. Forte’s initial customers are primarily in Japan, but we are now seeing serious activity in Europe and more interest in the U.S.

Mark Lippett, Ignios – Ignios is a semiconductor IP provider providing an efficient runtime system management solution for heterogeneous multicore SoCs. Commercially, we use ESL tools to demonstrate the value of our solution, internally we use them for system level validation. We engage with design teams around the world.

Ken Karnofsky, The MathWorks – The MathWorks is the leader in Model-Based Design, which encompasses embedded system and electronic system design and verification, and integrates with downstream tools for implementation. Model-Based Design with Simulink and MATLAB solves the real problem facing electronics companies – that design flaws introduced at the specification stage are not detected until late in the process, causing delays and missed market opportunities.

While ESL companies are talking about an upcoming age of embedded software, MathWorks customers are using Simulink today to design their embedded systems and automatically generate production implementations on processors and FPGAs. And while ESL companies are talking about modeling hardware at higher levels of abstraction, MathWorks customers are using MATLAB and Simulink to eliminate design flaws and achieve multi-million dollar cost reductions and time-to-market advantages because the chip works the first time.

Simon Calder, SpiraTech – We believe that for the next 10 years the EDA front-end will be of heterogeneous abstraction. More and more people are agreeing. This means that for everything to work together, verification components called 'Transactors' will be required by everyone, everywhere. Transactors are the EDA devices that mix and match the multiple levels of abstraction that exist at and above RTL. SpiraTech makes transactors, but most importantly we are the only company making tools which automate their creation. We will supply a large library of transactors for common protocols to all comers, make transactors for large companies with proprietary interfaces to support and last but not least sell our Transactor Compiler to those few companies who still design major industry standard interconnects.

Transactors are used in simulation, test, debugging, protocol checking, protocol coverage analysis and performance profiling. Gary Smith reckons those 'ESL' markets should be worth $600M by 2008.

Emil Girczyc, Summit Design – Summit delivers System Architect to assist design teams with architectural design and tradeoffs, and to analyze / characterize system-level performance. System Architect was first adopted in the U.S., and is now gaining momentum in the other regions. Summit also recently announced Vista – the first debug environment specifically designed for SystemC. It is gaining traction first in Asia and Europe because this is where the use of SystemC is more prevalent.

Simon Napper, Synfora – Synfora is focusing on delivering a practical ESL synthesis that is a practical capability for designing complete application engines from C algorithms. We are focusing on the consumer applications that are driven from C reference algorithms and need custom application engines integrated into a platform SoC.

We are focused on state-of-the-art algorithms such as the H.264 video standard. Synfora’s focused on these projects because designers are facing such a daunting design task. And ESL synthesis becomes a lifeline to help them achieve design project goals. These complex designs put significant demands on the synthesis capability to produce complex hardware structures, to automatically deal with unit-level and system-level verification issues, and RTL-GDS issues such as timing closure.

Q.13 – Do you agree with Wally Rhines' keynote statement at DVCon that with the move to ESL, we can anticipate 5 million people worldwide empowered to design?

Gary Smith, Dataquest – Why not. We are closing in on a million right now.

Jeff Jussel, Celoxica – Yes, and this is the exciting thing about ESL. More than any other field, ESL is opening doors for a wide variety of applications to use semiconductors and in particular FPGA. They look at FPGA as a way to accelerate their systems using a custom 'co-processor'. The ESL tools are an enabling technology that will let EDA sell into markets that up until now could not take advantage of custom hardware. There are many more of these types of applications than there are hardware design groups, or even embedded software design groups.

David Stewart, CriticalBlue – I’m not sure about the specific numbers but if you agree with my definition of ESL above, then you can immediately include the majority of the embedded software developers in our world; they all become prospects for buying design automation solutions. If we, as an industry, can harness that opportunity then the future is very bright.

Brett Cline, Forte – There is no doubt that moving up in abstraction allows additional people into the mix more easily.

Mark Lippett, Ignios – It is our view that the trend towards proportionately fewer silicon platforms that have greater flexibility (i.e. programmability), will continue unless design and fabrication costs become substantially cheaper. For non-field reprogrammable hardware architectures, this will restrict mainstream ESL usage to software architectural exploration on a given hardware platform. On the flip side, increasingly complex software programmable platforms will mandate more representative environments for software programmers; these environments can be created using ESL tools.

Simon Calder, SpiraTech – Yes and no. I think Wally was referring to the Embedded software developers market.

An analogy that comes to mind is Gillette looking at China and seeing 600 million new customers for Mach4. They know that the percentage that can spend $25 on 4 razor blades today is very small. Over the next 25 years that percentage will grow. But Gillette already sells $6 Billion of razor blades at margins we have not seen since the 1990's! We in EDA need a quicker fix than that.

The worldwide semiconductor market as grown to $240 Billion, we in the EDA business should be at least 3% of that. 1.5% for time-to-revenue, 1.5% for yield enhancement, power savings and die size. Getting our fair share from our existing user base of lets say 100,000 is a much easier task than turning 4.9 million people who currently pay nothing for anything into profitable customers.

Q.14 – Is it fair to accuse any of the big EDA players of standing in the way of the move to ESL?

Shiv Tasker, Bluespec – No. The market will drive the move to ESL, but only when solutions materially impact overall chip projects, not just sub-blocks.

Jeff Jussel, Celoxica – The big EDA players tend to be more conservative and let the innovation and associated market risk play out among the start-ups. It's not fair to say that they stand in the way of that innovation, though at times their marketing machines create some confusion that might slow things down a bit. In the end, they will join in as the winning ESL methodologies and technologies become apparent.

Mark Milligan, CoWare – It’s not fair to accuse the big companies of standing in the way; they haven’t. All are members and significant contributors to efforts like OSCI. Some of them dabble in ESL in areas close to what they do today. But it’s unfair to expect them to come up with dramatic new breakthroughs—these typically come from new companies. Partnerships are probably the best strategy in ESL. Cadence, for example, partnered with CoWare to help accelerate connectivity from ESL into EDA verification flows.

David Stewart, CriticalBlue – I’m not sure that they are standing in the way of ESL. Rather, I think they do not have the vision to first of all see the opportunity that expanding into these new communities will bring. Second, and perhaps more importantly, they don’t seem to realize that the status quo – constraining EDA to the part between RTL and GDSII – is barely sustainable and certainly isn’t a growth opportunity. It’s in the name EDA – design automation – and we need to spread that automation into other areas of the electronic product chain. This is not optional, it must happen, and if the big guys don’t do that us little guys will.

Brett Cline, Forte – The big EDA players have big revenue streams to protect. If a company has an RTL product line that brings in $300-500M a year, they're going to be very sensitive to maintaining that. It is very difficult for the big companies to spend a lot of money on an R&D group for a new product that will lose money for a bunch of years before breaking out. This is one of the reasons that EDA innovation traditionally comes from startups. But, make no mistake – the budget money has to come from somewhere. With the average customer budget increasing very modestly each year (5% +/-), the ESL tools are getting money from the budget traditionally allocated to RTL tools. This is why the big companies eventually acquire the small companies – to get new technology and grow.

Simon Calder, SpiraTech – No, I would argue that I have seen more Start-ups mis-defining ESL and distracting some of the investment that could be better deployed in accelerating the natural evolution that is occurring naturally. I would say that I have seen some of the bigger guy's over estimate their influence on the customers and make forlorn attempts to orchestrate the migration.

Emil Girczyc, Summit Design – I don't know that it's fair to say that the big EDA players are standing in the way of the move to ESL, but more appropriate to say that they are trapped in the classic "innovators dilemma" as described by Christensen – they don't see the solution because it is not a natural extension of their business and their existing customers are asking them for more and better of the same tools for the same tasks.

The business of the EDA companies is based on hardware groups designing larger and more complex chips that are then programmed to build systems. With ESL, software applications are designed, and then the hardware that best implements the application is selected, often using large amounts of existing IP blocks. ESL addresses new problems, and creates new opportunities for companies that deliver solutions to those problems.

Simon Napper, Synfora – They are not standing in the way; they just don’t appear to be driving the move. This is common behavior, as most significant advancements in EDA technology have come from start-ups. They (the big players) will start getting interested when they see significant design wins by start-ups.

Gary Smith, Dataquest – Not really. They are suffering from the same problem Calma, Applicon & Computer Vision – Daisy, Mentor & Valid did when their methodology changed. Let's see if Cadence, Synopsys and Mentor can do better than those earlier industry leaders did.

[Editor's Note – Thanks to all of the panelists for their contributions to this conversation. I'm sure we'll be hearing more from all of you in various venues over the coming months.]

Accelerated Technology, the Embedded Systems Division of Mentor Graphics Corp., announced that its Nucleus RTOS and development environment now supports the ColdFire MCF547x/548x processors from Freescale Semiconductor, Inc.

Aldec, Inc. announced the release of its Riviera-IPT Desktop for RTL debugging and verification. The company says that the new release is based on Aldec's Riviera-IPT Platform and is designed to allow engineers to run and debug their RTL code from a local PC or workstation prior to system-level verification.

Altium Ltd. announced version 1.1 of its TASKING R8C software development toolset, which supports the R8C/Tiny devices and provides a new interface to the Renesas E7 emulator. The R8C/Tiny is a series of 16-bit microcontrollers from Renesas Technology Corp. for applications needing small pin counts and affordable flash memory.

Applied Wave Research, Inc. (AWR) announced an agreement with TSMC to jointly develop and deliver a design platform for TSMC's 0.35-micron SiGe process. The platform will include AWR's Analog Office RFIC design software, a TSMC 0.35-micron SiGe process design kit based on open software standards, and an end-user support package. TSMC and AWR will develop a set of device models for the TSMC 0.35-micron SiGe process. The model set will include HICUM bipolar transistor models, as well as a set of spiral inductor models. XMOD Technologies will provide the HICUM model libraries.

ARC International and On2 Technologies, Inc. announced a collaboration to provide customers with video codecs optimized for the ARC processor cores. On2 will port their VP6 codec video compression software to the ARC processor core.

Cadence Design Systems, Inc. announced it has added new technology and capabilities to its Virtuoso custom design platform, with the aim to increase speed and productivity in analog, custom, and RF design.

Cadence Design Systems, Inc. also announced that Atmel's RF design group is using the Virtuoso UltraSim Full-chip simulator to verify mixed-signal designs. Tim Hersh, RF Design Engineer at Atmel, is quoted: "The Virtuoso UltraSim simulator reads in the same Spectre netlists and models and uses the same equations, guaranteeing close correlation in results. We were able to increase our productivity by five times."

Cadence Design Systems also introduced its Cadence Allegro system interconnect design platform version 15.2. New constraints in the Allegro platform products include the ability to account for signal delays inherent in IC packages and vias, and the elimination of the need to link to the package database or manually account for critical signal delays.

Cadence Design Systems also announced an "advanced" verification environment for the Incisive Palladium acceleration/emulation system that is designed for verifying multi-million-gate SoCs. New capabilities include enhanced transaction-based acceleration (TBA), verification IP SpeedBridge "solutions," additional integration with embedded software debuggers, and added support for multiple languages and standards.

Cadence Design Systems also announced that ATI Technologies Inc. used Cadence's Encounter digital IC design platform to implement its nanometer-scale, 520 MHz, 160-million-plus transistor hierarchical Visual Processing Unit in the company's Radeon X800 graphics chips family.

Finally, Cadence Design Systems and Rambus Inc. announced agreements to offer "comprehensive solutions" for the serial link interface market. Under agreements between the companies, Rambus is acquiring serial link IP from Cadence to incorporate into its existing RaSer product line of serial link cells. At the same time, Cadence Engineering Services will "gain access to Rambus's portfolio of serial link cells to deliver customized design solutions as needed." Cadence will be the exclusive EDA industry reseller of Rambus's foundry serial link cells, and will exclusively sell only Rambus foundry serial link cells off-the-shelf (OTS).

CoWare and MIPS Technologies, Inc. announced that SystemC-based processor support packages (PSPs) for the MIPS32-24K core family have been added to CoWare's ConvergenSC Model Library. The PSPs are additions in a series of models developed through an ongoing partnership between the two companies.

eInfochips Inc. announced the availability of a DSP-based keyboard, video, mouse interface product, which provides real-time KVM/IP response over TCP/IP to control servers remotely. A frame-compare and image-compression algorithm with special techniques for noise filtering and video compression is implemented on the DSP. Product features include highly secured remote access and server control, browser-based control, field upgradeable design, and compatibility with standard KVM switches.

Giga Scale Integration Corp. (Giga Scale IC) announced shipments of the latest version of its InCyte product family, which includes a link to IP access and management technology from VCX Software Ltd., and allows users to browse the VCX IP Portal Catalog. The VCX Software's library has 2500+ components and InCyte's database has 1,300+ soft IP components and several hundred foundation IP libraries. Users can view the combined IP catalog from VCX and Giga Scale IC from the Incyte Macro browser, search by class of IP, view datasheets and get information on area, power, and number of gates.

Kilopass Technology, Inc. announced that Global UniChip Corp. (UniChip) has signed an agreement with Kilopass to add Kilopass' embedded non-volatile memory technology, XPM, to UniChip's IP portfolio. In addition, UniChip has joined Kilopass Technology's Design Services partner program. Jim Lai, COO and President of Global UniChip Corp., is quoted: "Kilopass XPM technology offers an affordable solution for our CMOS customers who need post-manufacturing, late-stage programming flexibility."

Magma Design Automation announced that its SiliconSmart characterization and modeling products now support Legend Design Technology's MSIM circuit simulator.

Mentor Graphics Corp. and Semiconductor Manufacturing International Corporation (SMIC) announced a Technology Design Kit (TDK) for SMIC's 0.18-micron mixed-signal process technology. The open-source design kit is built for use with Mentor's Analog/Mixed-Signal (AMS) IC Design Flow and allows IC design companies to set up the design environment using the SMIC 0.18-micron process technology.

Mentor Graphics also announced the availability of Calibre and ModelSim for AMD64 processor-based systems running 64-bit Linux.

Additionally, Mentor Graphics Corp. announced I/O Designer for concurrent chip-to-board design of FPGAs and the PCB. The tool allows bi-directional communication and data management throughout the process of implementing FPGAs onto the PCB. Per the Press Release: " Starting with early HDL descriptions of the FPGA, I/O Designer's automated schematic symbol generation function provides PCB designers the schematic symbols used to represent FPGAs in the PCB design. Then, I/O Designer incrementally and bi-directionally manages pin assignments on the FPGA by: a) graphically assigning signals to designated pins in a guided FPGA library environment; b) constraining pin mapping pre-synthesis to achieve optimal FPGA and PCB interconnect; c) communicating allowable FPGA pin-swaps to the PCB solution; d) synchronizing pin-out assignments between the FPGA and PCB solutions for rapid timing closure and routing completion; e) communicating constraints between the PCB and FPGA solutions; and f) allowing designers to optimize their I/O design for PCB layout."

Finally, Mentor Graphics announced its DMS2004 release, a scalable library and data management product. The tool integrates library data with the component data required for business-oriented design and part selection, and includes the management of bill-of-materials during the design phase to allow early visibility for the product lifecycle management system.

Nassda Corp. announced austriamicrosystems AG has adopted Nassda's HSIM. The companies report that HSIM has been used to verify 10+ designs in CMOS, BiCMOS, and SiGe process technologies for the Full Service Foundry group of austriamicrosystems. Thomas Moerth, Design Support Manager at austriamicrosystems, is quoted: "It is austriamicrosystems' policy to focus very much on the accuracy of analog models in order to enable our customers' first-time-right designs. To effectively simulate and analyze GHz high-speed and low-power designs in our latest high-performance processes, we need a high capacity and accuracy circuit simulator. By providing our foundry customers with qualified HSIM models in our design environment HIT-Kit, we are confident that their simulation results will accurately reflect their final silicon."

QuickLogic Corp. announced four new additions to its PCI 2.3-compliant QuickPCI family, all of which are optimized for portable applications. The company says users of these products can expect 132 MBps PCI-bus performance with zero-wait states, while also meeting the power requirements of portable PCI applications such as mini PCI modules or CardBus cards. The QL58x0 devices support PCI Target functions for 32-bit PCI designs.

Soft Mixed Signal Corp. said that it has standardized its interface verification process with software from Denali Software Inc.. and is using Denali's PureSpec PCI Express verification IP to verify its PCI Express PHY Interface for its PCI Express (PIPE) compliant PHY IP. Soft Mixed Signal is also partnering with Denali to distribute and market an integrated PIPE PHY IP with PureSpec. Muzaffer Kal, CTO of Soft Mixed Signal Corp., is quoted in the Press Release: "Denali's PureSpec has allowed us to deliver a fully compliant, verified and highly reliable PHY IP. We are impressed with the sophisticated system environment generated by PureSpec. It covers the complete PCI Express topology and tests boundary conditions and various operating modes required for complete interoperability verification."

Sonics, Inc. announced that it is joining Cadence Design Systems and CoWare in supporting the Cadence/CoWare flow for ESL design through verification. The companies say the flow is based on integration between CoWare's SystemC-based ConvergenSC SoC design tools, the ConvergenSC Model Library and the Cadence Incisive functional verification platform. Sonics is adding its SMART Interconnect IP into the flow, as well as its SonicsStudio interconnect IP configuration tool.

Synopsys, Inc. announced that Semiconductor Manufacturing International Corp. (SMIC) has adopted its Proteus optical proximity correction (OPC) software for production at 130 nanometers. Simon Yang, Vice President of Logic Technology Development Center of SMIC, is quoted: "SMIC is committed to providing our customers with the best service, including high yields and quick turn-around-time. Proteus OPC software helps us better serve our customers."

Synopsys also announced that Renesas Technology Corp., a joint venture between Hitachi, Ltd. and Mitsubishi Electric Corp., has standardized on Synopsys' Star-RCXT for resistive-capacitive (RC) parasitic extraction in its design flow. Hisaharu Miwa, Department Manager for the EDA Technology Development Department in the Design Technology Division of the LSI Product Technology Unit at Renesas Technology Corp., is quoted: "Using Synopsys' Star-RCXT for accurate RC parasitic extraction with PrimeTime for static timing analysis, we successfully taped out several multimillion-gate chips. Based on these results, we have standardized on Star-RCXT for parasitic extraction in our sign-off flow for 90-nanometer designs."

Finally, Synopsys announced the availability of its DesignWare PCI Express Physical (PHY) layer IP, which is based on Synopsys' 6.25 Gbps backplane and high-speed SERDES (serializer-deserializer) technology. The DesignWare PCI Express PHY has been designed to provide higher yield, better interoperability, lower field returns and better ease-of-use in end applications.

Tensilica, Inc. announced the automated design of optimized configurable processors from standard C code using the company's XPRES (Xtensa PRocessor Extension Synthesis) compiler. The company says the tool allows for the development of optimized SOC devices without requiring designers to hand code their hardware. With the Tensilica process, designers input the original algorithm that they're trying to optimize, written in standard ANSI C/C++, and the XPRES compiler automatically generates an RTL hardware description and associated software tool chain.

Tower Semiconductor and Virage Logic Corp. have signed a licensing agreement under which Virage Logic's Technology-Optimized Platforms will be made available on Tower's 0.13-micron CMOS processes. Under the terms of the agreement, Tower customers can access Virage Logic's Technology-Optimized Platforms - comprised of embedded memories, standard cell logic libraries, and I/O libraries - on Tower's 0.13-micron TS13SL (standard logic) process, followed by support for its 0.13-micron TS13LP (low-power) process. Tower customers will also have access to Virage Logic's IP portfolio including the Self-Test and Repair (STAR) Memory System and the Area, Speed and Power (ASAP) Logic Metal Programmable Cell Libraries.

TransEDA announced that AMD is using TransEDA's imPROVE-TLL functional abstraction tool to abstract full-custom macro designs. Per the Press Release: "AMD's Macro Functional Verification team deployed TransEDA's imPROVE-TLL to abstract full-custom macro designs, enabling the use of equivalence checking to speed up the verification process."

VeriSilicon Holdings Co., Ltd. and Magma Design Automation Inc. announced that VeriSilicon's semiconductor IP products in logic, I/O cells and memories now support Magma IC design products Blast Create, Blast Fusion, Blast Rail, Blast Noise, and Blast Power. Magma users can now access library scripts directly from VeriSilicon. Wayne Dai, President and CEO of VeriSilicon Holdings, is quoted: "Magma is the acknowledged technology leader in EDA. We are excited to work with Magma to support their design solution with our libraries for all major China-based wafer foundries, such as SMIC, GSMC, HHNEC and ASMC."

Virtual Silicon Technology, Inc. has introduced the Mobilize power management IP, which aims to reduce dynamic and static (leakage) power on SoCs. The technology is a result of collaboration between Virtual Silicon and National Semiconductor Corp. working on the PowerWise technology. Per the Press Release: "Mobilize is targeted to help SoC designers working in the battery-powered, mobile application space manage power, extending Moore's Law beyond the power barriers at 130nm process technology and below."

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3Plus1 Technology Inc. announced details of the company and a multiprocessor architecture for next-generation hand-held systems, which has been used as the basis for a series of CoolProcessor devices for low-power mobile-system manufacturers. The architecture is in a sub-100mw processor implemented in a standard 130-nanometer low-power CMOS process. Jan Rabaey, professor at U.C. Berkeley and director of the Berkeley Wireless Research Center and the MARCO Gigascale System Research Center, is serving as a technical advisor to 3Plus1. The company also announced it has joined the ARM Connected Community, is working with CoWare Inc. to demonstrate the CoolProcessor in the CoWare simulation environment, is working with Hellosoft Inc. towards its first silicon, and is working with Sonics Inc. towards the implementation of complex IP.

Actel Corp. and Mentor Graphics Corp. announced that the new version of Mentor Graphics’ Precision RTL Synthesis tool is producing “significantly higher performance” on designs that use Actel’s ProASIC Plus FPGA family, including designs with up to 30,000 logic tiles. The companies are reporting that customers using Precision should expect, on average, an 18-percent improvement in clock frequency over previous versions of the software. The Precision RTL Synthesis tool is integrated into Actel’s Libero 6.0 IDE.

Agilent Technologies Inc. announced new wireless testbenches, sources, and measurement capabilities for its Advanced Design System (ADS) 2004A EDA software. Per the Press Release: “Traditionally, nonlinear and distortion analysis and measurements rely only on discrete-tone figures of merit. Discrete-tone stimuli and measurements may prove inadequate since real-world sources have different signal characteristics such as power statistics. For accurate verification, designers must validate the performance of their circuit under real-world stimuli and with the system measurements that current standards require. The new ADS 2004A capabilities include configurable DSP-based modulated sources with RF and baseband outputs, a set of measurement expressions and a range of wireless testbenches for 3GPP, WLAN and TD-SCDMA technologies.”

Airgo Networks announced a tapeout using Sequence Design’s PowerTheater to automate the power analysis for Airgo’s new 802.11g chips. Derrick Lin, Senior Director of ASIC Engineering at Airgo Networks, is quoted: “PowerTheater predicted power usage within 10% of silicon for our AGN100BB chip. We achieved this level of accuracy by leveraging PowerTheater’s innovative RTL and gate-level analysis capabilities. Since switching to PowerTheater’s accurate and automated RTL power estimation, Airgo designers have minimized power early in the design cycle and verified that power budgets are met.”

Aldec, Inc. announced the release of Riviera 2004.08 with a direct simulation kernel connection with SystemC, which the company says creates an efficient system-level co-simulation environment for next generation design and verification methods. Eric Seabrook, Product Marketing Manager at Aldec, is quoted in the Press Release: “Traditionally, only early adopters have had the advantage of designing with the latest methodologies offered to the market. Aldec aims to change that with its release of Riviera 2004.08 by offering a completely integrated, mixed-HDL and SystemC solution at an affordable price.”

Ansoft Corp. announced availability of SIwave v2. The product is a full-wave electromagnetic field simulator, which analyzes signal-integrity and power-integrity effects in PCBs and IC packages. The new release includes: power plane impedance, signal net analysis, resonant mode analysis, Spice export, robust meshing, automated geometry cleanup, unlimited undo and redo, a decoupling capacitor model library, and a frequency-dependent model for dielectric. Per the Press Release: “SIwave’s proprietary full-wave, finite-element technique allows designers to characterize simultaneous switching noise (SSN), inter-symbol interference, power and ground bounce, resonances, reflections and coupling between traces and power/ground planes.”

Apache Design Solutions announced that ATI Technologies Inc. has adopted Apache’s full-chip dynamic physical power integrity flow. ATI says it is using Apache’s RedHawk-SDL for cell-based dynamic voltage drop analysis and NSPICE-PI for global I/O simultaneous switching output (SSO) verification. Per the Press Release: “ATI found traditional methods of static-only IR-drop analysis to be inadequate for their high-performance graphics processor designs. They saw that Apache’s ability to perform full-chip dynamic power analysis, including the effectiveness of decoupling capacitance, and the verification of global I/O SSO, was important for their current and future designs.”

ARC International announced that SanDisk Corp. has licensed the ARC 600 RISC processor core and MetaWare development tools for use in their next-generation flash storage products. Yoram Cedar, Senior Vice President of Engineering at SanDisk, is quoted in the Press Release: “In planning for our next-generation product lines, we had very strict size and performance requirements. After seeing that the ARC 600 core could be configured to optimally meet our size, area and performance needs, the choice was easy.”

Applied Wave Research, Inc. announced the integration of Analog Devices’ analog-to-digital converter models (ADIsimADC) with AWR’s Visual System Simulator 2004 (VSS) design system. The companies say the combination of capabilities will allow RF and baseband design engineers using VSS software to develop wireless communications systems by modeling the actual performance of Analog Devices’ ADCs in a system block diagram. Brad Brannon, Staff Applications Engineer in the High-speed Converter Group at Analog Devices, is quoted in the Press Release: “Every converter genre exhibits unique ‘real world’ behavior patterns, and this tool helps minimize the design surprises that tend to result from basing performance assumptions strictly on data sheet specs.”

Applied Wave Research also announced the Microwave Office 2004 design suite for next-generation RF and microwave circuit designs. The design suite integrates 3D planar EM simulation with circuit simulation and layout tools, permitting arbitrary physical structures to be embedded within linear and nonlinear circuit simulations. James Spoto, AWR President and CEO, is quoted: “The layout process for RF and microwave design drives overall circuit performance and must be closely connected to electromagnetic simulation tools. The Microwave Office solution … provides everything designers need to take an idea from concept through simulation and directly into physical implementation.”

Cadence Design Systems, Inc. announced new PSpice-based simulation technology for the company’s OrCAD product line. The technology integrates Cadence PSpice with MATLAB and Simulink products from The MathWorks. The company says the new PSpice SLPS interface, co-developed by Cadence and Cybernet Systems in Japan, allows co-simulation of electrical and mechanical systems.

Meanwhile, Cadence Design Systems and the Shanghai Research Center for Integrated Circuit Design (ICC), founded by China’s Ministry of Science and Technology, announced the availability of the ICC-Cadence CPU/DSP SoC reference methodology. The methodology includes the Cadence Encounter digital implementation platform, Incisive functional verification platform, and CoWare software tools for ESL design and verification.

Cadence Design Systems also announced that ATI Technologies Inc. selected the Cadence Incisive Palladium acceleration and emulation system to verify some of its highly complex designs. Dave DiOrio, Vice President of Engineering at ATI, is quoted in the Press Release: “ The Palladium system provided the features we needed to meet stringent product delivery schedules and increased our ability to test our ASICs and application-level software.”

As well, Cadence Design Systems announced that NVIDIA used Cadence’s Incisive Palladium system to “significantly reduce” its verification time for NVIDIA’s new GeForce 6800 graphics processor. Brian Kelleher, Vice President of Hardware Engineering at NVIDIA, is quoted in the Press Release: “Previously, our verification process would take about two to three days per turn - the cycle for bug detection, identification and the repair process. With Palladium, we average two to three turns per day.”

And, Cadence announced that TelASIC Communications, Inc. got a 10x simulation performance increase in the course of developing the “world’s fastest analog/digital converter.” Cadence said that TelASIC used its Virtuoso UltraSim FastSPICE simulator to verify TelASIC’s TC1410 ADC. Don Devendorf, CTO at TelASIC, is quoted in the Press Release: “Using Virtuoso UltraSim, our designers were able to run multiple simulations on the entire ADC circuit in a few hours, producing accurate results and reducing our verification cycle from weeks to days.”

Finally, Cadence Design Systems announced it has helped enable Stretch Inc. to meet an “aggressive time-to-market goal for a high-performance software-configurable processor design.” Stretch says it benefited from the Cadence Digital IC design flow and libraries from TSMC.

Carbon Design Systems announced it has joined 0-In Design Automation’s Check-In Partner Program. The companies say that the assertion synthesis capability of 0-In’s Archer Verification System, when coupled with Carbon’s DesignPlayer engine, will provide “design bug identification without sacrificing runtime performance.”

Carbon Design Systems also announced it has integrated its DesignPlayer engine with Virtutech’s Simics Instruction Set Simulator, which the companies say will enable customers with processor-based designs to execute operating systems and application-level software “on a fast and accurate model of a chip or system.” The companies are also announcing that this integration allowed Sun Microsystems to boot its Solaris operating system on a Simics-DesignPlayer model of their design.

Per the Press Release: “DesignPlayer is a soft model that is accurate to the hardware-cycle and register accurate. Unlike behavioral models or C models generated from an ideal specification, DesignPlayer behaves exactly like the hardware with all its errata. Hardware designers now have the cycles they need to run complete regression suites before chip tapeout. Software designers can finally test and debug their code on a high performance, cycle accurate, linkable model. Customers get an executable specification that contains the silicon errata for system integration and test.”

Denali Software Inc. and Mentor Graphics Corp. announced a collaboration whereby Mentor Graphics will use Denali’s PureSpec verification IP product to confirm its PCI Express IP core is compliant with the PCI Express and Advanced Switching Interconnect interface standards, and interoperable with other system designs as well.

Denali Software also announced that Cray Inc. has selected Denali’s Databahn memory controller IP cores and MMAV verification IP software for Cray supercomputer product development. Cray says it plans to use Denali’s Databahn IP in the design of the DDR-SDRAM memory system, and will use Denali’s MMAV product for modeling and simulating the interactions between chips and external memory devices for design verification and performance analysis.

eInfochips Inc. announced the availability of a high-performance DSP-based keyboard, video, mouse (KVM) interface product, which the company says is designed to be scalable and customizable. The KVM product supports all major server platforms, provides remote access to servers using standard IP connections, and enables management of servers from the boot-up process as if the network administrator was sitting next to the managed device. The product also features a frame compare and image compression algorithm with techniques for noise filtering and video compression implemented on the DSP, browser-based control, field upgradeable design, and compatibility with standard KVM.

Forte Design Systems announced that Sanyo Electric Co., LTD has adopted Forte’s Cynthesizer SystemC behavioral synthesis tool for the implementation of Sanyo’s designs for consumer semiconductor devices. Fumiaki Nagao, Senior Staff member at Sanyo Electronic, is quoted in the Press Release: “Forte’s Cynthesizer has demonstrated its ability to quickly synthesize high-quality RTL from complex algorithms without sacrificing quality of results. We expect Cynthesizer to help cut months off our design cycle, while providing us with a complete and automated verification flow.”

HDL Works announced the release of version 5.2 of EASE, the company’s design entry environment for VHDL, Verilog, and mixed-language designs for FPGA and ASIC. Per the Press Release: “Synthesis and simulation tool independency enables the user to select his most favorite tools while setting-up a complete design flow … Many improvements have been made in this new version. These changes include Tcl driven version management with support for ClearCase, RCS and Synchronicity Design Sync, Verilog 2001 support and a new project browser. “

LogicVision, Inc. announced that the company is aligning with UMC to provide UMC customers with access to LogicVision’s wafer yield product. Frank Wen, UMC President, is quoted in the Press Release: “We believe this alliance will establish a new standard for rapid diagnosis of process issues associated with the increased design and process complexities of advanced technologies, allowing a faster ramp to full silicon yield.” From the Press Release, as well: “Because UMC is already shipping 90-nanometer silicon with good yields to customers, it was LogicVision’s leading foundry of choice for implementing this new program.”

Mentor Graphics Corp. announced that its ATPG tool, FastScan, has been selected for UMC’s 130 and 90-nanometer digital reference flow. Ken Liou, Director of the Design Support Division at UMC, is quoted in the Press Release: “We worked closely with Mentor Graphics to develop the ATPG portion of our reference flow. Using FastScan, we are able to achieve excellent test coverage which ensures we are providing our customers with high-test quality for their designs.”

Mentor Graphics also announced availability of the Capital Harness Systems product suite release 2004.1. The company says the new release includes: dynamic electrical simulation, which provides real-time feedback to design engineers; design abstraction, which allows engineers to visualize electrical designs at various levels of detail; design comparison, which provides graphical representation of connectivity or properties differences between related designs; enhanced harness drawing features, such as display of composite wire tables, display of terminal materials and display of nested dimensions for complex bundle configurations; and new integrations with third-party MCAD tools.

Optimal Corp. and Applied Wave Research, Inc. (AWR) announced what the companies are calling “the first commercially-available three-dimensional (3-D) full-wave EM extraction design flow.” The AWR-Optimal methodology is intended to assist with signaling issues characteristic to wireless communications designs operating from 1 to 50+ GHz, and combines Optimal’s O-Wave product with AWR’s Microwave Office and Analog Office design suites through the AWR EM Socket interface.

Len Perham, Chairman and CEO of Optimal, is quoted: “As technology alliance partners, AWR and Optimal demonstrate the ability of two vendors with leading-edge technology to collaborate successfully in order to provide intrinsic value to the customer, in this case, the microwave and RFIC designers who are encountering increasingly challenging circuit problems at the advanced semiconductor technology nodes.”

Silicon Canvas, Inc. announced the release of Laker-AMS version 6.1. Highlights of the release include: the new licensing scheme transition from Rainbow to FlexLM, improved hierarchy navigator usage, added Tcl/Tk scripting language support, a streamlined Spice-out procedure, and a new interface to the Laker full-custom layout tool. Per the Press Release: “Greatly increased interest and a desire to shift from a traditional polygon pushing methodology to the schematic driven layout flow methodology make the new release attractive to a broad range of existing customers and new prospects.”

Synopsys, Inc. announced that IPCore Technologies Corp., described as “China’s pioneer pure design foundry”, has signed an agreement to adopt Synopsys’ Galaxy Design and Discovery Verification platforms, and the company’s DesignWare IP portfolio as IPCore’s primary internal design flow. Under the terms of the agreement, Synopsys Professional Services will expand its delivery capability in China by selectively utilizing IPCore on a subcontracting basis.

Synopsys also announced that Samsung Electronics Co. Ltd. has signed a multi-year license agreement for Synopsys’ DesignWare IP. Under the terms of the agreement, Samsung is licensing the DesignWare Cores IP portfolio, which includes the PCI Express and USB families of digital cores and analog PHYs. K.H. Kim, Vice President of ASIC Business at the System LSI Division of Samsung Electronics, is quoted in the Press Release: “Outsourcing select IP lets our engineers focus on the value-added portions of the design such as quality, features and performance. This agreement with Synopsys will add industry-leading PCI Express and USB technology to the variety of proven IP cores provided by Samsung’s ASIC business.”

Finally, Synopsys announced the availability of the DesignWare USB 2.0 On-The-Go (OTG) PHY (Physical Layer) Core targeted to TSMC’s 90-nanometer, 130-nanometer, and 180-nanometer processes as well as an extension of the Hi-Speed USB 2.0 PHY Core product line to the 90-nanometer process node. The new OTG PHY handles HNP (host negotiation protocol) and SRP (session request protocol), which are the OTG-specific differences between the Hi-Speed 2.0 and the new OTG standard. Synopsys says DesignWare USB 2.0 OTG PHY is “the industry’s first 90-nanometer USB OTG PHY Core … is interoperability tested and jointly certified with Synopsys industry leading digital USB cores, thus providing a complete drop-in solution with lower cost, form factor and risk.”

Tharas Systems Inc. announced the Tharas Flexible On-demand Rental Collaborative Environment, T-FORCE, which is an on-site subscription verification program.

Per the Press Release: “T-FORCE, with subscription rates starting at $10,000 per month, is the most cost-effective subscription program on the market for accelerated functional verification of complex ASIC and system designs. T-FORCE, developed for customers with flexible verification needs, provides best-in-class accelerated verification at an affordable price. Projects with fluctuating verification capacity needs can increase or decrease hardware-assisted verification as necessary. The entry level of the program gives a customer the ability to verify up to 4-million gates ... Purchasing hardware-assisted verification technology is a huge capital expense that carries the very real possibility of obsolescing that investment every other year. T-FORCE virtually eliminates the fiduciary concern with on-demand access to capacity and performance throughput at an affordable price. The on-site subscription model builds acquisition credits towards future purchases.”

TriCN announced that it has released an area-efficient single lane (x1) PCI Express PHY. Currently the product is available in the TSMC 130-nanometer process. Per the Press Release: “TriCN’s PCI Express PHY x1 is the first to achieve a size of only 0.68 sq. mm for the PIPE core.”

Ron Nikel, Co-founder and CTO at TriCN, is quoted in the Press Release: “While today’s announcement marks another significant ‘industry first’ for TriCN, it represents an even bigger win for semiconductor designers who are constantly seeking to reduce area consumption, especially in consumer applications ... Based on our analysis of the market, we believe our single lane PCI Express PHY is nearly 40 percent smaller than the nearest competitor.”

Technically Speaking announced the PracticalHDL desktop multimedia HDL training course for interactive, self-paced learning with design tools from various companies including Synplicity and Xilinx. PracticalHDL includes parallel Verilog and VHDL instruction, with varying levels of complexity, and comes with learning modules for the coding of memory, finite state machines and RTL verification. Verilog and VHDL practitioners can download a free trial of the course by visiting the website.

Demos on Demand announced a broadband "video resource" for the IC design industry that features product demos from 70+ EDA, PLD and IP vendors. The site allows engineers 24-hour access to product demos from a spectrum of vendors. The programming features recorded sessions with product managers and AEs and is comprised primarily of in-depth product demos for IC design, from ESL design entry through layout. Engineers can visit the site and search by vendor or by product category.

AccelChip Inc. announced increased functionality for the AccelChip DSP Synthesis product, plus new support for third-party partners' RTL synthesis and simulation tools. Version 2004.5 includes support for new FPGA devices, and enhanced flows for ASICs, an enhanced floating- to fixed-point conversion, an enhanced scheduler, and a new implicit loop unrolling (ILU) functionality to the common explicit loop unrolling to array operations, where the user can specify all or down to the specific type of array to be unrolled. AccelChip DSP Synthesis is designed to fit into current design flows, to bridge the gap between MATLAB and RTL, and integrates verification and implementation flow with products from Aldec, Altera, Mentor Graphics, Synopsys, Synplicity, The MathWorks, and Xilinx.

AccelChip announced, as well, that it has extended its AccelWare IP libraries to include building blocks for signal processing and communication applications. The company says the new AccelWare blocks extend the range of the existing AccelChip DSP Synthesis toolset into various real-time, continuous communications and array signal-processing systems.

Finally, AccelChip says it has joined the OpenDoor program from Mentor Graphics. Juergen Jaeger, Marketing Director for the Design Creation and Synthesis Division at Mentor Graphics, is quoted in the Press Release: "When EDA vendors work together, the users reap the benefits. Strong partner solutions maximize productivity, expand choices and shorten time to market, all of which become increasingly critical factors for success in complex FPGA design."

Accelerated Technology (AT), the Embedded Systems Division of Mentor Graphics, announced the Nucleus EDGE software development environment based on the Eclipse open platform standard for the embedded systems industry. The new environment includes a project manager with an editor and builder, various debugging environments, run-mode debug capability, kernel awareness when using an RTOS, and basic execution and memory control. The Nucleus EDGE software will initially support the ARM GNU, RedHat GNU and ARM RealView C and C++ compilers.

Altium Ltd. released Version 8.5 of the TASKING C166/ST10 toolset, which includes enhancements to the compiler and debugger and introduces several key improvements. "Programming large applications is now easier - with support for 'the huge memory model' and additional memory allocation functions offering an optimal match of the application's program setup to the hardware organization. [Also], increased configurability of MISRA C compliance checking enables developers more flexibility to decide whether the code is required or just advised to comply with particular rules in keeping with the standards of their company and the requirements of the project. The C166/ST10 CrossView Pro debugger has also been enhanced in the new version of the toolset."

Altium also announced the release of its LiveDesign evaluation kits that include an evaluation board with the choice of either an Altera Cyclone or Xilinx Spartan-3 FPGA device. The kits are designed so engineers and designers can evaluate Altium's DXP 2004 product range and use the LiveDesign design methodology in Altium's Nexar and Protel design systems. LiveDesign uses FPGAs as reconfigurable implementation platforms for digital circuitry during system development, permitting "live and interactive development and testing of electronics systems inside a programmable hardware design space."

AMI Semiconductor (AMIS) and ARM announced that AMIS has selected the ARM architecture for some new programmable automotive electronics. AMIS has licensed two ARM7 family processors, the ARM7TDMI and ARM7TDMI-S microprocessors, to use in developing products that the company says will help improve driver information, in-car entertainment, body electronics and passenger safety. The first ARM technology-based automotive solutions from AMIS are expected to be available in 2006.

Apache Design Solutions announced that Toshiba has adopted Apache's full-chip dynamic power integrity tools into the Toshiba SoC power closure flow.

Applied Wave Research, Inc. announced their Microwave Office 2004 design suite for RF and microwave circuit designs. The new software integrates 3D planar electromagnetic (EM) simulation with circuit simulation and layout tools, so that arbitrary physical structures can be embedded within linear and nonlinear circuit simulations. The simulator uses a full-wave spectral-domain approach based on the method-of-moments, and is multi-threaded to take advantage of multiprocessor computers. AWR says various third-party EM solvers are integrated with the company's unified data model, including: Sonnet Software's EM product, Zealand Software's IE3D, MEM Research's EM3DS, Simulation Technology and Applied Research's Analyst, and Optimal Corp.'s O-Wave.

In addition, Applied Wave Research and Euan Information Technology announced that BOE HYDIS Technology Co., Ltd.'s Advance Technology Development Group Development division plans to utilize AWR's Analog Office software for the design and simulation of thin film transistor (TFT) liquid crystal display (LCD) panels.

ARM and Sun Microsystems has announced a long-term collaboration to integrate and distribute "optimized" Java solutions for mobile devices. The companies say they'll streamline access to the integrated products by establishing one single distribution source through Sun. The integrated product will be distributed by Sun; commercial deployment of the integrated product will be subject to the separate licensing terms of Sun and ARM respectively.

ARM also launched its new NEON media and signal processing technology targeted for mobile and consumer products that implement multiple combinations of video encode/decode, 3-D graphics, speech processing, audio decoding, image processing, and baseband functionality. The NEON technology will be implemented in future ARM processors, and will be supported by ARM and third-party tool chains. NEON technology is a 64/128-bit SIMD (single instruction multiple data) instruction set that "can execute an MP3 audio decoder in less than 10 CPU MHz, and can run the GSM AMR (Adaptive Multi-Rate) speech codec using only 13 CPU MHz."

Artisan Components and Cadence Design Systems announced a collaboration to provide library views for designers to optimize low-power chip designs. Per the Press Release: "Artisan and Cadence performed qualifications using Artisan's SAGE-X standard cell library and measured delays against SPICE while varying voltage, slew and load. The average difference in measured delays between SPICE and ECSM was 0.5%."

BAE Systems, Celoxica Ltd., and Medius Inc. announced what the companies are calling a "novel software approach to sensor integration that allows for optimized performance and dramatic cost reduction for cruise control, collision avoidance and other automotive safety systems." The new technology comes in release 2.0 of the companies' sensor-fusion technology demonstrator series, and has a self-aligning intelligent sensor that can automatically line up with the frame of reference of the vehicle it is attached to, therefore minimizing factory alignment issues.

Cadence Design Systems and the Shanghai Research Center for Integrated Circuit Design (ICC) announced the ICC-Cadence CPU/DSP SoC reference methodology, which includes the Cadence Encounter platform and Incisive platform, and CoWare's ESL design and verification tools. ICC was established in March 2000 by the Science and Technology Commission of Shanghai Municipality, and is said to focus on "promoting Shanghai and all China IC Design industry to realize rapid development."

Cadence Design Systems also announced the availability of an RTL-to-GDSII reference flow for SoC designs at 130 nanometers and below. The flow uses IP libraries and memories from Faraday Technology Corp. and technology from UMC to allow both high-speed and low-leakage transistors to be combined onto a single chip.

Cadence then announced that Fujitsu Ltd. has standardized worldwide on the Cadence Incisive Conforma equivalence checking tool for verifying ASIC requirements of Fujitsu's SoC designs.

As well, Cadence announced that Stretch Inc. met "an aggressive time-to-market goal for a high-performance software-configurable processor design - and benefited from the strength of a comprehensive Cadence Digital IC design flow and libraries from TSMC to mitigate its design risks and ensure high quality of silicon (QoS) through improved area and performance." Wow.

Cadence Design Systems also announced that Renesas Technology Corp. has standardized on MaskCompose for automated reticle design synthesis in its 90-nanometer design flow.

Finally, Cadence Design Systems announced two new product suites, OrCAD PCB Designer and OrCAD PCB Designer with Pspice, both of which are included in the OrCAD 10.3 release. The suites include the OrCAD PCB Editor constraint-driven PCB layout editing tool. OrCAD PCB Designer includes the SPECCTRA autorouter and the OrCAD Capture design entry tool, while PCB Designer with PSpice includes PSpice A/D for analog/mixed-signal simulation. OrCAD 10.3 also has features for OrCAD Capture, OrCAD Layout, and PSpice. The OrCAD 10.3 release with OrCAD PCB Designer will be available in November 2004.

Carbon Design Systems announced the addition of VHDL and mixed language (VHDL and Verilog) support to its product line. Carbon's SPEEDCompiler software reads synthesizable Verilog and/or VHDL and generates a DesignPlayer engine, which can represent one or more chips. The company says multiple engines can represent a system that encompasses hundreds of millions of gates.

Catalytic Inc. announced the first of what the company says will be a series of DSP design automation software products. Per the Press Release: "Catalytic's Fixed-Point DSP Studio software speeds floating-point to fixed-point conversion for users implementing systems using C or RTL. It shortens implementation time for fixed-point DSP algorithms by providing fixed-point variables in MATLAB from The MathWorks, accelerating MATLAB verification simulations up to 20X."

Celoxica announced it will support the Xilinx's new Virtex-4 FPGAs through the latest release of Celoxica's suite of system design and synthesis tools. Note that Celoxica's tools synthesize complex algorithms described in C or SystemC direct to the FPGA fabric. Alternatively the designer can use the same algorithmic description and output RT-level VHDL and Verilog.

Chartered Semiconductor Manufacturing announced functional 0.13-micron 300-millimeter wafers from its Fab 7. The company says the results exceed internal targets within five months of the first equipment installation. Chartered also announced it has launched the engineering for 300-mm wafers at Fab 7 for its 0.11-micron process, and for the 90-nanometer platform being jointly developing with IBM. The 90-nanometer cross-foundry platform that will be available at both Chartered's Singapore-based Fab 7 and IBM's East Fishkill fab in New York.

ChipX announced that it has selected SynTest's VirtualScan, Scan/ATPG tool, to "ensure the quality of its new generation of large ASIC designs and cut the cost of ASIC testing, by reducing the scan-test pin-count on load boards." Elie Massabki, Vice President of Marketing at ChipX, is quoted: "We pride ourselves on offering our customers the lowest cost ASIC solutions and getting them to market faster than any other ASIC alternative. Upgrading our DFT tools with VirtualScan from SynTest is an important step towards our on-going effort to consistently upgrade our development and test capabilities with the most effective tools to service our customers." Great.

CoWare Inc. announced a new version of the company's SPW DSP application product, SPW 5-XP for Windows. CoWare says the new release includes new features and functionality to make DSP application design faster and easier. These features include integration with MATLAB from The MathWorks that the companies say accelerates implementation starting from MATLAB algorithms. New features also include Windows "look & feel,' an open, extendible, standard XML database, and SPW's simulation engine and library of 4,000+ DSP application models."

Meanwhile, CoWare and AccelChip Inc. announced a joint effort to provide an advanced design and verification flow for DSP designs that originate in MATLAB. The companies have integrated CoWare's DSP application design tool, SPW, with AccelChip's algorithmic synthesis tools to offer DSP design teams the ability to verify generated RTL levels in Verilog or VHDL within the SPW environment.

Denali Software Inc. and Mentor Graphics Corp. announced a collaborative effort whereby Mentor Graphics will use Denali's PureSpec verification IP product to confirm that Mentor's PCI Express IP core is compliant with the PCI Express and Advanced Switching Interconnect (ASI) interface standards, and interoperable with other system designs.

eInfochips Inc. announced the availability of DSP-Karma, a suite of DSP software, hardware and systems integration services. The company says DSP-Karma offers is a suite of services with emphasis in the areas of video conferencing, wireless multi-media devices and remote server management solutions. Services includes algorithm design and development, DSP processor selection, board support packages for RTOS on DSP, porting and migration across diverse platforms, board-level systems and firmware solutions on DSP.

Emulation and Verification Engineering (EVE) announced that Amos Technologies will be its exclusive distributor to electronics companies in Israel. Under terms of the distribution agreement, Amos Technologies will market and support ZeBu, EVE's verification platform used by IP, FPGA, ASIC, SoCs, and embedded software. EVE also announced that D'Gipro Design Automation and Marketing, Ltd. to be EVE's distributor in India.

FishTail Design Automation, Inc., announced exclusive distribution agreements with both Saros Technology Ltd. in Europe and Advinno Technologies in Southeast Asia. The company already works with SC HighTech in Japan. The company says the distributors will provide customers with front-line sales and support in their regions.

Fujitsu Ltd., Fujitsu Microelectronics America, Inc., and Synplicity, Inc. have announced an agreement to develop a custom physical synthesis product for Fujitsu AccelArray structured/platform ASIC devices. Fujitsu and Synplicity say they will work closely to produce an optimized version of Synplicity's Amplify physical synthesis software, specifically targeting the AccelArray architecture and enabling performance and faster overall timing closure for Fujitsu's devices. Under the terms of this agreement Fujitsu and Synplicity will jointly define and Synplicity will develop the customized Amplify software for the AccelArray physical synthesis product.

HDL Works announced Version 5.2 of the EASE design entry environment for VHDL, Verilog, and mixed-language designs for FPGA and ASIC projects. EASE 5.2 includes Tcl-driven version management with support for ClearCase, RCS, and Synchronicity Design Sync, as well as Verilog 2001 support and a new project browser.

HDL Works also announced Version 1.1 of HDL Companion, an environment for insight into IP, integrating IP with new code and keeping an overview of HDL designs. New features include Signal Tracing through the design hierarchy, support for Verilog 2001, and version management with support for CVS and RCS.

IMEC announced the IMEC Industrial Affiliation Program (IIAP), which will "seek alternatives to the current use of scaling to reduce device dimensions using nanotechnologies. The program will also investigate disruptive technologies or new paradigms for semiconductor manufacturing processes. Although single devices have been demonstrated, there has been little effort in using nanotechnology building blocks to create an innovative technology with higher density and new functionality. IMEC program participants will investigate the use of semiconducting wires, carbon nanotubes and spintronics and, at the same time, develop the metrology and theoretical approach required as a backbone for implementation of the new methodologies."

"In the first phase of research, the potential of semiconducting wires will be studied. IMEC's fabrication process for making these vertical-pillar structures is now sufficiently mature to start evaluating their use in back-end-of-line (BEOL) processing, more precisely in the vias between the BEOL metal layers. The typical dimensions of the pillars (20nm to 100nm) match perfectly with state-of-the-art optical lithography, demonstrating an ideal link between evolutionary and revolutionary technologies. Applications may be possible in both optical and switching components."

Swept up in the excitement, Freescale Semiconductor, Inc. and IMEC say they are currently in the process of "helping you realize the vision of seamless mobility. IMEC and Freescale are working together on reconfigurable multiprocessor systems." Freescale says it has joined IMEC's Industrial Affiliation Program (IIAP), and thereby plans "to deliver leading edge mobile multimedia solutions by utilizing IMEC's existing and future reconfigurable technology, capitalizing on IMEC's total system approach and its focus on low power, as well as leveraging IMEC's system design tools and methodologies."

iRoC Technologies Corp. introduced the Soft Error Analysis Web Tool, a web-based tool that assesses the Soft Error Risk (SER) of IC designs-transient faults caused by external radiation that affect the logic states of ICs and memories in SoCs, ASICs, FPGAs, or memories. The tool also gives recommendations on steps that can be taken to quantify and also reduce the soft error failure-in-time (FIT) rate if the target application or industry requires it.

iRoC Technologies also introduced its SERPRO services for transistor-level SER prediction and optimization. The company says the services will "help semiconductor companies perform faster and more accurate soft error modeling before design tape out-making their ICs more reliable in the field."

Eric Dupont, iRoC's President and CEO, is quoted: "Up to 90 nanometers, both standalone and embedded memories have been the primary design element impacted by cosmic rays, so memory providers and designers of SoCs with large memory elements will benefit greatly from our new services. As more devices are designed for 90- and 65-nanometer nodes, potential damage from cosmic rays will not only affect memory elements, but also logic gates. Designers of memory and logic devices need to be able to analyze, simulate, predict and optimize their SER numbers during the design cycle to achieve their target SER rate and ensure product reliability."

Lattice Semiconductor Corp. and Mentor Graphics announced a multi-year extension and expansion of their OEM agreement for Mentor Graphics synthesis and simulation tools. The new agreement adds the Mentor's Precision RTL synthesis tool to the Lattice OEM portfolio,

LSI Logic Corp. announced three new RapidChip IntegratorQSslices. Per the Press Release: "The new slices leverage LSI Logic's proven-in-silicon and standards-compliant GigaBlaze serializer/deserializer (SerDes) technology by including four independent lanes of 4.25 gigabits per second (Gbps) SerDes. Another key architectural advantage of the RapidChip IntegratorQS slices is that they support PCI Express datapaths of 250 MHz. These datapaths are implemented in the metal configurable R-cell logic transistor fabric. The combination of SerDes and logic performance ensures that developers can implement ASIC-class low latency, high system performance solutions, with the benefits of risk mitigation and affordable NRE costs associated with Platform ASIC technology."

Magma Design Automation Inc. and ChipX announced availability of an RTL-to-GDSII design flow based on Magma's Blast Create and Blast Fusion. The companies say they have worked together to test and customize the Magma flow to support the ChipX CX5000 family and future structured ASIC product families.

Also, Magma Design and MIPS Technologies, Inc. announced the availability of a validated reference methodology for the high-performance MIPS32(R) 24K microprocessor core family. The methodology includes flow documentation, floorplanning information, tool scripts and make files. In addition to validating the reference flow, MIPS says it has completed the Magma IP verification process for the 24K family and the company has been added to the growing list of "Magma-Ready" IP providers.

MatrixOne, Inc., and Technia AB signed a software and service agreement with Ericsson to use MatrixOne's PLM software as Ericsson's global platform for managing development projects. MatrixOne and Technia will work together on the global deployment and implementation of the system within Ericsson's R&D units.

Mentor Graphics announced the availability of the Altera Stratix GX design kit for ICX. The companies say the new design kit allows engineers using the Mentor Graphics ICX signal integrity (SI) analysis tool to perform full-board analysis on designs featuring the high-speed serial I/O technology of the Altera Stratix GX devices "hundred of times faster than previously possible with SPICE-based simulation techniques."

Mentor Graphics also announced that its suite of advanced synthesis products will support the newly introduced Virtex-4 FPGAs from Xilinx. Customers who use the Precision RTL or LeonardoSpectrum tools can now request software that supports the full range of Virtex-4 devices, while the Precision Physical tool is offering beta-level support

Then, Mentor Graphics announced that it has "enabled the industry's most accurate simulation of nanometer technology with the introduction of new resistance and capacitance engines for its full-chip, transistor-level parasitic extraction solution, Calibre xRC. Based on the new resistance engine, Mentor Graphics has also developed hierarchical netlisting and optimized back annotation capabilities between Calibre xRC and Nassda's high-performance simulation platform HSIMplus."

Mentor Graphics also announced that the Calibre product line is now accepting OASIS files and supporting OASIS output in the upcoming 2004.3 production. It includes the GDS-to-OASIS translator, which was previously made publicly available for validation and verification of the new format. The OASIS translator will be an included feature in the Calibre releases, and available to all Calibre customers.

Mentor Graphics also announced new enhancements to its MBISTArchitect BIST tool for on-chip testing of embedded memories generated by Artisan Components. Additionally, Artisan says it has recognized the MBISTArchitect tool as a "qualified BIST solution" for testing its embedded memories and facilitating its Flex-Repair(TM) Redundancy solution for yield improvement. Per the Press Release: "As the use of embedded memory continues to increase, thorough testing and defect diagnosis has become paramount to product quality and yield enhancement. Memory BIST has emerged as the most efficient method to test and diagnose problems with embedded memories."

Mentor Graphics also announced a technical collaboration with StarCore to offer Seamless hardware/software co-verification processor models for StarCore's licensable processor cores, SC1200 and SC1400. The support packages will implement SC1200 and SC1400 cores and subsystems, as well as providing performance profiling for cache activities, memory accesses and software codes.

Mentor Graphics also announced new automated functionality in its ATPG, FastScan, and TestKompress embedded deterministic test tool. The ATPG Expert feature works as an internal "expert" within the FastScan or TestKompress tools to automatically analyze the design, manages test generation complexities, and determines the sequential depth or abort limits to set, the types of compression to exploit, and how to handle clock interactions and bus contention.

Mentor Graphics also announced a new version of its popular ModelSim simulator and new verification technology from the recently completed acquisition of 0-In Design Automation. With the ModelSim 6.0 simulator and the 0-In product line, Mentor Graphics says it now offers "standards-based support for the most advanced verification methodologies. Offering support for assertion-based verification and coverage-driven verification flows, as well as verification IP, Mentor's scalable verification platform offers engineers a faster way to reach verification closure than current methods."

Finally, Mentor Graphics announced it has established business agreements with Optimum Design Associates (Optimum) and PCB Libraries to make their libraries available for use with the Mentor Graphics PADS PCB design flow. These agreements will allow PADS customers to choose from various suppliers of component libraries in selecting components for their electronic products." Clearly, it's been a busy month for Mentor!

PolarFab has published its 2005 PolarShuttle schedule. The company says that designers can "test prototypes and minimize a new product's time to market by incorporating PolarShuttle into their development schedule. New for 2005 are two additional manufacturing runs of PolarFab's PBC4 0.5-micron BiCMOS-DMOS (BCD) process."

Pulsic Ltd. has announced that Hynix Semiconductors has adopted Pulsic's shape based place-and-route flow "to reduce the turnaround time for leading-edge designs."

QuickLogic Corp. announced a Reference Design Kit (RDK) for low-power designs that uses the company's Eclipse II FPGAs. The Low Power RDK includes hardware and software tools, and allows designers directly measure the power consumption of Eclipse II designs, and calculate, analyze, and simulate power dissipation for Eclipse II designs under development. The Low Power RDK comes with two PCBs - a prototyping board housing the Eclipse II FPGA and a daughter board for power measurement.

QuickLogic also announced the QL92xxx family of programmable SoC devices, products based on the QL902M member of the QuickMIPS product family. The new products incorporate additional pre-programmed modules that will target the device for embedded digital-media applications. The first member of the family, the QL92010, incorporates an IDE controller. Subsequent devices, to be announced later this year, will embed functionality "consistent with the company's focus on providing silicon solutions for equipment that distributes and processes digital media across wired and wireless IP networks."

Silicon Canvas, Inc. announced the release of Laker-AMS version 6.1. The new release includes a new licensing scheme transition from Rainbow to FlexLM, enhanced hierarchy navigator usage, added Tcl/Tk scripting language support, a streamlined Spice-out procedure, and a new interface to the Laker full-custom layout tool. The company says the new release assists in the shift from a traditional polygon pushing methodology to the schematic driven layout flow methodology.

Silicon Dimensions, Inc. announced an agreement with eSilicon Corp. to distribute Chip2Nite to the eSilicon customer base. In addition, eSilicon says it will adopt Chip2Nite into its silicon implementation flow and collaborate with Silicon Dimensions to develop new tools to meet future IC design challenges.

SMSC announced what the company describes as "one of the industry's most comprehensive lines of USB2.0, mobile super I/O and embedded Ethernet controllers for a wide range of consumer and commercial connectivity solutions. With this announcement, SMSC delivers the USB2503 and USB2507, the industry's first USB2.0 3-port and 7-port hub controllers with SMSC's innovative MultiTRAKTM multiple Transaction Translator (Multi-TT) technology, as well as the USB2504, a second generation 4-port hub controller; the USB2228, a controller for 12-in-1 flash card readers; the USB3250, a second generation USB2.0 physical layer transceiver (PHY) device; the SIO1000, a second generation consumer InfraRed (IR) I/O controller; plus the Company's LAN9118,a second generation 10/100 Non-PCI Ethernet controller." Again, wow.

Stone Pillar Technologies Inc. announced TestPlanManager, which the company describes as the newest addition to its Silicon Insight family of products for developing semiconductor process technologies. TestPlanManager automates the creation of test routines for device characterization and provides capabilities for test library management, which the company says improves test plan readability, reduces errors, guarantees consistency between test plan documentation and executable, and reduces engineering effort by as much as 75 percent.

Synopsys, Inc. announced that Samsung Electronics Co. Ltd. has signed a multi-year license agreement for Synopsys' DesignWare IP, under the terms of which Samsung is licensing Synopsys' PCI Express and USB families of digital cores and analog PHYs. The first core Samsung will use under the license agreement is the USB 2.0 PHY core.

Synopsys also announced that Synopsys' Design Compiler FPGA (DC FPGA) now supports the Xilinx Virtex-4 family of domain optimized FPGAs and ISE 6.3i place and route software. Synopsys says that DC FPGA is targeted for designers who prototype ASICs using high-end FPGAs. [Bets are on that there will be more and more of this type of news in the coming era coming from a range of different EDA vendors.]

Synopsys also announced that IPCore Technologies Corp. (described as "China's pioneer pure design foundry") has signed a multi-million dollar agreement to adopt Synopsys' Galaxy Design and Discovery Verification Platforms, and Synopsys' DesignWare IP portfolio as IPCore's primary internal design flow. The company says that under the terms of the agreement, Synopsys Professional Services will expand its delivery capability in China by selectively utilizing IPCore on a subcontracting basis.

Synopsys also announced that Microchip Technology Inc. has standardized on Synopsys' Circuit Explorer optimization and analysis solution for its complex analog designs. The Microchip team says they selected Circuit Explorer because "it enabled them to take weeks off of their design cycle and eliminate the tedious manual tasks usually associated with complex analog designs." Something to celebrate.

Synopsys announced, as well, the availability of the DesignWare USB 2.0 On-The-Go (OTG) PHY (Physical Layer) Core targeted to TSMC's 90-nanometer, 130-nanometer, and 180-nanometer processes, as well as an extension of the Hi-Speed USB 2.0 PHY Core product line to the 90-nm process node. The new OTG PHY will handle HNP (host negotiation protocol) and SRP (session request protocol), which are the OTG-specific differences between the Hi-Speed 2.0 and the new OTG standard. The OTG solution is based on the Synopsys USB 2.0 PHY that is already certified and shipping in volume.

Then, Synopsys announced that Atheros Communications, Inc. has adopted Synopsys' NanoSim for the RF front-end circuit verification of Atheros' AR5005G single-chip wireless product. The company says the chip is a multi-million-gate IC that supports the IEEE 802.11b and 802.11g protocols, and that using NanoSim 2004.06, Atheros engineers can now perform RF front-end circuits verification of their complex mixed-signal devices.

Also, Synopsys announced that its Proteus optical proximity correction (OPC) software has been adopted by NEC Electronics Corp. for use in NEC's 90-nanometer production.

Synopsys also announced that BAE Systems used Synopsys' Galaxy Design Platform to achieve success on 24 radiation-hardened space-qualified ASICs. Per the Press Release: "Galaxy's predictive timing closure, as well as its tightly integrated flow, was instrumental in the design success of the complex chips."

Finally, Synopsys and Photronics, Inc. have announced a joint program for improving the manufacturability and quality of photomasks and reducing the cycle times for design-to-photomask flows. The companies says that they'll explore and develop solutions in the area of DFM and mask synthesis targeting faster time to yield for semiconductor manufacturers.

Synplicity Inc. announced that the company's newest version of the Synplify Pro synthesis software provides full support for Xilinx's Virtex-4 FPGAs. The company also announced the latest version of its FPGA synthesis and physical synthesis software solutions. The Synplify Pro 7.7 synthesis tool includes enhancements, as well as support for new FPGA devices from Xilinx and Lattice Semiconductor. Synplify Pro software now include timing-driven synthesis support for Xilinx's Virtex-4 FPGAs and support for Lattice Semiconductor's LatticeECP and LatticeEC FPGA device families. Synplicity says enhancements have also been added to the Amplify FPGA 3.7 physical synthesis software.

TransEDA announced the availability of its PCI All-in-One verification IP and its latest VN-Control bus-based system-level test generator release 3.0. The new verification IP provides a single, compatible programming interface which allows verification teams to reuse their tests on systems containing any combination of PCI Express, PCI-X and PCI buses. This IP accommodates testing of various system-level configurations such as systems containing PCI Express buses only, a combination of PCI-SIG standard buses, or a single PCI-SIG standard bus selectively enabled.

Wolfson Microelectronics plc announced that the company has purchased software from Verific Design Automation and is using it as part of its internal design environment. Wolfson said they had to because the increasing digital complexity of Wolfson's advanced mixed-signal products has motivated a transition of its digital design flow from a partly schematic, partly Verilog hardware description language (HDL), flow to a fully Verilog HDL based flow. Verific's HDL Component Software provides a Verilog parser and analyzer.

X-FAB Semiconductor Foundries AG announced an extension to its modular 0.35-micron process family to include a high-voltage option, as well as 0.35 µm-BiCMOS technology. With this product extension, X-FAB says the XH035 0.35 µm CMOS technology can be "flexibly expanded with virtually a free range of combinable add-on modules."

Xilinx announced shipments of the 6.3i release of its Integrated Software Environment (ISE), which the company says is optimized for the Xilinx Virtex-4 family of Platform FPGAs. The company says the new ISE 6.3i uses the Virtex-4 architecture to support up to 200,000 logic cells and 500 MHz performance for twice the density and up to 10 times better performance-price ratio than previous generation FPGAs.

Xilinx also announced the version 6.3i of the Platform Studio for system-level embedded processing design on Xilinx Platform FPGAs. The company says that the tool suite automates various architecture-level design steps and offers a new software environment based on the Eclipse IDE. The Platform Studio 6.3i release supports the Xilinx processor products, including the MicroBlaze and the immersed PowerPC cores, and allows for system-level design for the Virtex-4 LX, SX, and FX device families, while also supporting the Xilinx Virtex and Spartan-3 Series Platform FPGAs.

ARM, Artisan Components, National Semiconductor, Synopsys, and UMC announced that the five companies are collaborating to deliver a comprehensive low-power, energy-efficient SoC technology demonstrator for the ARM926EJ-S processor. The "ULTRA" technology demonstrator for the ARM926EJ-S processor is being implemented in UMC's 130e Fusion process, a 130-nanometer process platform designed for the integration of high-speed and low-leakage transistors in a single CMOS process. ULTRA stands for UMC Low-power Technology Reference using the ARM926EJ-S processor.

AccelChip Inc. announced that the Jet Propulsion Laboratory (JPL) has selected AccelChip DSP Synthesis and AccelWare IP libraries to develop a digital filter for space-based radar applications.

Accelerated Technology announced it has combined its UML (xtUML) modeling tool with its prototyping product. The Nucleus BridgePoint for UML modeling suite and the Nucleus SIMdx prototyping environment provides a hardware-independent platform for developing embedded applications.

Agilent Technologies Inc. announced that Innovative Wireless Technologies (IWT) has selected Agilent's Advanced Design System (ADS) software and ultra-wideband (UWB) DesignGuide to help prove UWB design concepts for prototyping. Agilent says the multiyear agreement includes licensing for ADS, its circuit and system simulators, the UWB DesignGuide, and Agilent test equipment.

Agilent Technologies also announced a new budget analysis capability in its ADS 2004A software that the company says enables engineers to design RF systems more accurately, as it predicts RF system performance by considering specification tradeoffs, such as impedance mismatch versus gain, earlier in the design cycle.

Agilent also announced the availability of its ultra-wideband (UWB) Design Exploration Library. The company also announced that Daido Steel Co. Ltd. has selected Agilent's Advanced Design System (ADS) 2004A EDA software and the new UWB Library to help in the development of bandpass filters used for UWB transceivers.

Aldec, Inc. announced Version 4.3 of its Active-HDL 6.3 co-simulation and debugging environment for ESL design and verification. The release includes a direct kernel connection between Active-HDL's mixed-language VHDL and Verilog HDL compilers and the C/C++ compiler, so that the co-simulation environment for SystemC is independent of the entry language. The company says it has also redesigned the waveform viewer.

Aldec and Magma Design Automation announced availability of a design flow interface between Active-HDL 6.3 and PALACE version 2.4. The companies say the integration of the two products automates the data exchange of graphical design capture, mixed VHDL and Verilog verification and physical synthesis, to help provide an efficient solution for Actel, Altera and Xilinx designs.

Altium Ltd. announced a universal JTAG interface to help engineers use the company's LiveDesign tool with any third-party FPGA development board. The JTAG interface attaches to the parallel port of a developer's computer and includes a set of flying leads that connect to the target development board.

Altium also announced support for a range of FPGA daughter boards for its FPGA-based development board, the NanoBoard. The additional daughter boards cover devices from CPLDs to high-performance FPGAs.

Altium separately announced a new plug-in daughter board supporting the Xilinx Virtex-II Pro FPGA as part of a comprehensive FPGA daughter board release for Altium's "LiveDesign-enabled" FPGA-based development platform.

Altium also announced the release of the P-CAD 2004 PCB design system, which the company says includes 50+ new and enhanced features, including upgraded layout and automatic and interactive routing, improved support for CAM file editing and circuit simulation, and other enhancements for greater power and control over the PCB design process: a new interactive Advanced Route tool, and complete control over all interactive routing features, including the level of 'glossing' or trace cleanup the tool attempts during interactive routing.

Finally, Altium said it will expand the HDL capabilities of Nexar with support for Verilog. Also, the upcoming Service Pack 2 for Altium's DXP 2004 design systems, which includes updates for Nexar and the Protel board-level design system, will add syntax-aware code editing, parsing and compilation support for Verilog. Service Pack 2 for its Nexar software will include a 32-bit FPGA-based RISC processor to help to take the risk out of migrating systems to the 32-bit domain.

Anadigm has launched the first of a series of Configurable Analog Starter Kits that include ready-to-use EDA files, source code for dynamic configuration, and step-by-step instructions for implementing the circuit in a field programmable analog array (FPAA).

Applied Wave Research, Inc. (AWR) announced that Silicon Laboratories, Inc. has adopted AWR's Microwave Office and Visual System Simulator (VSS) design suites. Silicon Laboratories teams will use the AWR software to simulate RFIC chips and modules.

ARM announced that it has released its PrimeXsys Platform, based on the ARM1176JZF-S 32-bit processor core, to STMicroelectronics.

ARM also announced the Cortex-M3 processor, designed to for high system performance in cost-sensitive embedded applications. It is the first member of the new Cortex family of CPU cores.

Atmel Corp. and Mentor Graphics Corp. announced an extension of the OEM agreement between the two companies for synthesis, simulation, and verification tools from Mentor. The companies say the new agreement spans the spectrum of tools required for both FPGA and CPLD design.

Bluespec Inc. and Novas Software, Inc. announced that the companies have created a debugging environment for behavioral synthesis that allows hardware design engineers to debug high-level, untimed, behavioral source code. The environment allows interactive cross-probing and communication between Bluespec's Blueview design visualization tool and the Novas Verdi Automated Debug System.

Cadence Design Systems, Inc. announced that Azul Systems implemented a high-density, high-speed design using the Cadence Encounter digital IC platform and RTL Compiler.

Cadence also announced that PalmChip Corp. has qualified Cadence Encounter RTL Compiler for implementation of PalmChip's AcurX SoC platform. The companies say that using the tool, core IP blocks of the AcurX platform achieved up to 3x faster run times than with PalmChip's previous synthesis solution.

Cadence also announced a collaboration with IBM to launch Power.org, an open standards community to help IC designers develop SoCs using the IBM PowerPC Architecture, and dedicated to promoting the IBM PowerPC Architecture as the preferred open-standard hardware-development platform for electronic systems for markets such as consumer electronics, networking, storage, military and automotive.

Cadence also announced an assertion-based verification (ABV) solution as a part of its Incisive functional verification platform. The technology includes broad, native assertion support for Property Specification Language (PSL), SystemVerilog Assertions (SVA) and Open Verification Library (OVL). In addition, Cadence is also introducing an extended open-source library of assertions.

Cadence also announced the Encounter Diagnostics yield diagnostics tool, designed to help identify nanometer IC yield problems and locate root cause defects. The new tool supports all digital design styles and test vectors produced by ATPG tools.

Cadence also announced that Toshiba Corp. and Toshiba Microelectronics Corp. taped out a 24-million-gate chip using Cadence SoC Encounter. The chip is Toshiba's largest to date, and was designed using Toshiba's TC300 process for 90-nanometer technology.

Cadence also announced enhancements to its Encounter Conformal technology, Encounter Conformal 5.0, to provide verification capability to insure that the tapeout accurately reflects design intent. New capabilities in include FPGA support, clock domain checking and advanced datapath verification.

Finally, Cadence and Chartered Semiconductor Manufacturing announced that the companies have jointly qualified the Cadence Fire & Ice QX cell-based extraction tool for Chartered's advanced nanometer processes.

Chronology, a division of Forte Design Systems, announced TimingDesigner version 7.0, an interactive timing analysis and diagram product. Version 7.0's project manager feature helps exchange timing information, and helps users manage the specification and analysis of interfaces for digital IC and board designs. Designers can organize multiple diagram components within one project; components and blocks are arranged and displayed in a single tree, with a summary list of all constraint violations in the project diagrams. Designers can also merge two diagrams from different components, to automatically create an interface to account for component connectivity, as well as to manage signal duplication and propagation delays.

CoWare Inc. and LSI Logic Corp. announced availability of ZSP SystemC-based models for use with the CoWare ConvergenSC design environment. LSI Logic says it developed cycle- and transaction-accurate SystemC-based models for each of the available ZSP cores and, through joint cooperation with CoWare, integrated the ZSP models into CoWare's ConvergenSC Model Library.

CoWare and Forte Design Systems announced an integrated SystemC-based solution for ESL design to implementation. The integration of CoWare's SystemC-based ConvergenSC SoC design tools and Forte's Cynthesizer SystemC behavioral synthesis product aim to unite system architecture, simulation, and synthesis in the flow. Users can explore/validate a design's system architecture in ConvergenSC, then synthesize to RTL Cynthesizer, and verify the RTL in a system context with the same SystemC model.

CoWare also announced a new release of its SystemC-based ConvergenSC SoC design tools. New features allow for faster modeling and debug of IP models, platform subsystems, and SoC designs in SystemC, with an open environment that helps integrate internal tools and IP into the system-level flow. The new development environment includes a SystemC integrated development and debug environment (IDE) based on the open Eclipse C++ development environment for embedded software. In addition, ConvergenSC supports the latest release from OSCI, SystemC version 2.1.

Denali Software, Inc. announced an IP core, and design and verification IP software that use ARM's AMBA AXI interface. The product, PureSpec-AXI, uses technology from the PureSpec product line to provide for pre-silicon verification of functionality, compliance and system-level verification of designs utilizing the AMBA AXI architecture. Denali's new IP core, Databahn-AXI, and uses Denali's Databahn DDR controller IP, and provides developers with a native AMBA AXI interface for its DDR-based memory controller cores.

The Embedded Microprocessor Benchmark Consortium (EEMBC) and Patriot Scientific Corp. announced EEMBC has published the benchmark scores for Patriot Scientific's IGNITE 2FX 32-bit processor. The processor was tested against the EEMBC Consumer benchmark suite in a 600-MHz simulation, and achieved an out-of-the-box score of .01808 Consumermarks per MHz

eSilicon Corp. announced that it collaborated with Aarohi Communications and Synopsys in the tapeout of a complex chip design, and subsequent first-pass functional silicon.

HelloSoft, Inc. and Toshiba America Electronic Components, Inc. (TAEC) announced an enhancement to HelloSoft's VoIP software suite, which has been optimized for the Toshiba T6TC1XB-0001 embedded controller.

Hong Kong Science and Technology Parks Corp. (HKSTP) and Synopsys announced that HKSTP has licensed Synopsys' DesignWare IP cores portfolio.

IMEC says it has developed an integrated low-cost, low-power, pulse-based ultra-wideband pulser designed in 0.18-micron CMOS logic technology. The transmitter is 0.6 x 0.6 mm, operates between 3 and 5 GHz, and is flexible in both center frequency and bandwidth.

Impulse Accelerated Technologies, Inc. announced a new edition of its CoDeveloper C to RTL design tools, which support for Altera's SOPC Builder and the Quartus II, Version 4.1 design software. CoDeveloper is a tool to describe, debug and test mixed hardware/software applications using standard C development tools such as Visual Studio and GCC/GDB - and compile those applications directly to Cyclone or Stratix devices without writing low-level VHDL or Verilog.

Infineon Technologies announced that their 150-MHz TriCore TC1130 microcontroller, which the company says is a 32-bit chip capable of running the Linux OS, has achieved an "exceptional" score of 95.2 Automarks in tests against EEMBC's automotive/industrial benchmark suite.

The Joint Development Project (JDP) between Silterra Malaysia Sdn. Bhd. and IMEC announced functional SRAM chips at Silterra's wafer fabrication facility in Malaysia. The device was an 8-megabit SRAM, and was fabricated in the all-copper, foundry compatible 0.13-micron CMOS process technology jointly developed by both companies.

Kilopass Technology, Inc. announced that its XPM technology is now available for use in ASICs and SoCs using standard logic CMOS 90-nanometer silicon processes, in addition to its current products that are based on 0.18, 0.15, and 0.13-micron processes.

Magma Design Automation Inc. and Cadence Design Systems announced that Magma's IC implementation system now supports the effective current source model (ECSM) from Cadence.

Magma also announced that DongbuAnam Semiconductor has standardized on SiliconSmart CR and SiliconSmart IO characterization and modeling technology. The companies say the tools will be used for timing and low-power characterization of DongbuAnam's next-generation nanometer libraries.

In addition, Magma and Mentor Graphics announced an interoperability agreement to integrate the Mentor's TestKompress embedded deterministic test (EDT) tool into Magma's RTL-to-GDSII design system. Mentor and Magma will "provide mutual customers with an integrated IC implementation flow that includes comprehensive DFT capabilities to ensure design closure and testability of nanometer designs."

Magma also announced that NEC Electronics America, Inc. verified a multimillion-instance nanometer design, using Version 4.2 of the Blast Fusion physical design system, complete with Magma's third-generation routing technology.

Finally, Magma announced that a "fully-validated" RTL-to-GDSII design enablement kit for the IBM-Chartered Semiconductor Manufacturing jointly developed 90-nanometer process platform is now available online.

MatrixOne, Inc. announced the Synchronicity Developer Suite V4.1, which introduces a new DesignSync package and DesignSync CTS (Custom Type System). DesignSync CTS allows customers to create a plug-in to recognize and manage data from other EDA tools that are not supported "out of the box."

MatrixOne also announced that Elettronica, a manufacturer of defense equipment and systems, has completed implementation of MatrixOne's PLM platform.

Mentor Graphics announced that the Platform Express SoC design creation tool now supports the SPIRIT 1.0 specification for IP design reuse (see below).

Mentor Graphics also announced additional functionality for the Calibre platform - Calibre Transition, Measure and Analyze - which the company says will address DFM requirements. Mentor also outlined its roadmap for future Calibre DFM tools, to include optimization for manufacturing at various stages in the design flow: design, verification and analysis, tapeout and test.

Mentor Graphics also announced that ATI Technologies Inc. is using Mentor's VStationTBX verification accelerator.

Mentor Graphics also announced that the Institute of Computing Technology (ICT) of the Chinese Academy of Sciences has selected the VStationPRO emulation system as the verification platform for its Goodson series CPU chip.

Mentor Graphics also announced that NEC Electronics has adopted Mentor's analog mixed-signal simulator, ADVance MS tool for development of large, high-speed I/O interface circuits for NEC's analog and mixed-signal SoC products.

Mentor Graphics also announced the availability of two new iSolve speed adapters from its family of emulation products supporting the USB and PCI Express industry standard protocols.

Mentor Graphics also announced a collaboration with Xilinx to supply Expedition and PADS users with reference data, which allows them to more efficiently implement the multi-gigabit transceiver (MGT) technology available in Xilinx FPGAs.

Finally, Mentor Graphics announced the XtremePCB design tool that allows multiple members of a PCB design team to work simultaneously on a design from a single database on a global network, whether they are in the same office or dispersed geographically.

OASIS Tooling has announced support of the OpenAccess platform version 2.2.

PolarFab says it has improved its 6-inch complementary BiCMOS (c-BiCMOS) RFBC/ABC3 processes to provide reduced die sizes and decreased design times. Three digital cell libraries have also been added to the company's RFBC/ABC3 standard cell library portfolio in order to reduce design times.

Also, PolarFab and Mentor Graphics announced the availability of a design kit (DK) which supports the PolarFab PBC4 BCD process technology. The DK is available for use with Mentor's Analog/Mixed-Signal (AMS) IC Design Flow. Apogee Technology Inc. says the company has taped out a next generation mixed-signal chip using the PBC4 kit.

PowerEscape, Inc. introduced its second generation products, PowerEscape Architect and PowerEscape Analyzer. The tools provide for power optimization strategies for both hardware and software engineers, by indicated the ideal memory architecture to the system architect while also indicating power bottlenecks in embedded code to the software developer.

QualCore Logic said it has added two new IP cores to its product portfolio. The first is a digital Serial ATA Host Controller with OCP Interface. The second is high-speed analog dual serializer/deserializer (SerDes) core for SXGA/SXGA+/UXGA application that utilizes a Low Voltage Differential Signaling (LVDS) I/O.

QuickLogic Corp. announced it now has a "Wireless Application Portal" on the company's website, which the company describes as a "comprehensive resource that discusses the challenges associated with wireless system design and provides users with solutions to these challenges, particularly related to 802.11a/b/g Wi-Fi."

QuickLogic Corp. also announced a partnership with Renesas Technology Corp. that the companies say will enable low-power products for the expanding WiFi market. The technology consists of Renesas' SH processor and a programmable companion bridge from QuickLogic for connectivity to miniPCI and Cardbus based WiFi modules or chipsets.

Sequence Design announced that Q-DOT has selected Sequence's Columbus-AMS RLC parasitic extraction tool for inductance and capacitance extraction.

Sequence Design also announced that S3 Graphics used the company's PhysicalStudio optimization software to reduce timing and noise violations on various S3 Graphics' designs.

Finally, Sequence announced a "major milestone" in recent power optimization efforts with Toshiba, which says it signed off on a wireless design using Sequence's MTCMOS (Multi-Threshold CMOS) technology.

Silicon Dimensions, Inc. announced Chip2Nite 2.0, whose features include a new DRC suite, auto-macro placement and block floor planning capability, improved statistics reporting, and a 5x to 10x improvement in "typical" database load times critical for prototyping and what-if analysis.

SoftJin has released a free suite of IC design layout data exchange libraries and tools for use by IC designers and EDA product companies, including GDSII and OASIS readers, writers and GDSII-to-OASIS translator, in source code form. The suite is named Anuvad, and includes tools to handle the OASIS format.

Sonics Inc. announced its new SonicsMX product for the design of low-power SoC devices for wireless and handheld products. SonicsMX provides physical structures, advanced protocols, and power management capabilities. SonicsMX is the result of a collaboration between Sonics and Texas Instruments, which verified that Sonics' SMART interconnect is suitable for low-power operation such as TI's OMAP platforms.

SMSC and TransDimension announced that TransDimension's high-speed USB controller IP, a ULPI interface block, and SMSC's USB3300 ULPI stand-alone physical layer transceiver (PHY), are the first products to pass the high-speed USB Implementers Forum (USB-IF) compliance testing using the new ULPI interface.

Stelar Tools, Inc. has introduced HDL Explorer, a rapid RTL closure tool. HDL Explorer provides a combination of new design creation, and exploration and editing of new and legacy designs and testbenches using best-known methods (BKMs). HDL Explorer is designed to let designers and verification engineers find and fix errors, and define and manage the design/verification interface in new or existing HDL designs. HDL Explorer is the first in a family of products that Stelar will be bringing to market.

Stelar Tools also announced that it has integrated Verific Design Automation's HDL Component Software with its graphical and textual design environment. Verific's HDL Component Software has C++ source code-based Verilog and VHDL parsers, analyzers and elaborators, and acts as a front end to Stelar's toolset.

Stone Pillar Technologies Inc. announced that Micrel Inc. has adopted the DesignRuleBuilder component of the company's Silicon Insight toolkit for semiconductor technology development.

Synopsys, Inc. and Shanghai Hua Hong NEC Electronics Ltd. (HHNEC) announced that HHNEC has adopted Synopsys' Proteus optical proximity correction (OPC) software. HHNEC is a joint venture between NEC Corporation, Jazz Semiconductor and Shanghai Hua Hong Group.

Synopsys also announced that NVIDIA Corp. has adopted Synopsys' Galaxy 2004 test tool for its designs.

Synopsys also announced that STMicroelectronics used the Galaxy Test flow to "significantly increase its fault coverage and reduce tester time on its latest high-volume printer chipset."

Synopsys announced the DesignWare VIP (verification IP) suite for the AMBA 3 AXI protocol, which resulted from a between Synopsys and ARM.

Synopsys also announced that Sasken used Synopsys' Galaxy Design Platform to develop a reference flow to enhance implementation and signoff for its various complex designs.

Meanwhile, Synopsys and KLA-Tencor announced that they are collaborating to develop a compact yield analysis and modeling system for Toshiba Corp. The new modeling system will enable Toshiba to improve parametric yields on its sub-100-nanometer SoC products.

Synopsys also announced that it now supports the Intel Xeon processor with Intel Extended Memory 64 Technology (Intel EM64T) for 64- and 32-bit computing, with the Red Hat Enterprise Linux version 3 operating system, using its Galaxy design and Discovery verification technology.

Finally, Synopsys said that Micron Technology, Inc. has chosen Synopsys' SiVL silicon-versus-layout software to help implement advanced DRAMs, flash memories, CMOS image sensors, and other semiconductor components.

Synfora, Inc. announced A new release of PICO Express, a tool for application engine synthesis (AES). This version of PICO Express provides for faster IP integration and verification, and includes FPGA synthesis scripts for industry-standard tools to support FPGA prototyping for system verification.

SynTest Technologies announced that its DFT-PRO 100 and 200 Series of ATPG starter packages include the DFT tools for comprehensive ASIC testing. The tools operate on scan-inserted netlists and include tools for testing DFT rules' violations, ATPG, and test pattern formatting.

Tensilica Inc. announced that ATI Technologies Inc. has licensed the Xtensa configurable processor.

Tensilica also announced that Seiko Epson Corp. has licensed the Xtensa configurable processor for next-generation imaging products.

Teseda Corp. and Yokogawa Electric Corp. announced that they will work together to verify transportability of Standard Test Interface Language (STIL) DFT data between the Teseda OpenDFT WorkBench engineering software and production test platforms.

Teseda also announced the OpenDFT initiative "to exploit the full power of design-for-test (DFT), uniting design, test, and manufacturing to cut weeks from time-to-money and improve device yield and profitability." Teseda says it has worked with EDA and ATE vendors to develop the OpenDFT WorkBench software to bring DFT-Intelligent interactive validation, debug, and diagnosis to ATE platforms.

In related news, Teseda, in cooperation with Agilent Technologies, announced the development of the Teseda OpenDFT WorkBench software for the Agilent 93000 SOC Series platform.

Thomson announced that the company has licensed ARM OptimoDE signal processing technology for the development of broadcast video processing ICs.

Toshiba Corp. and Xilinx announced a strategic foundry relationship whereby Toshiba will manufacture Xilinx FPGA products. The companies say they have already achieved functional 90-nanometer first silicon at Toshiba's 300-mm fab at Oita, in Kyushu, Japan. Subsequently, Toshiba will start volume manufacturing in Q1 2005.

Meanwhile, Toshiba Corp. and ARM announced that Toshiba has licensed the ARM1136J-S processor. Toshiba says it will use the processor to develop ASICs for products such as consumer electronics and network systems.

TransEDA announced version 2.5 of its imPROVE-HDL formal property checker. Improvements aim to enhance the use of assertion-based verification (ABV) methodologies for SoC design. In addition to reading PSL assertions from an external file, imPROVE-HDL v2.5 now supports PSL in both VHDL and Verilog embedded in the design.

Verific Design Automation announced that it is shipping "the first commercially available" SystemVerilog parser. The parser supports the entire SystemVerilog 3.1 language definition, with the exception of SystemVerilog Assertions, for which it supports 3.1a.

ViASIC Inc. announced the availability of its new 0.13-micron ViaMask library for TSMC and TSMC-compatible processes. The company says the new library is silicon-proven and produces a 10-percent increase in density, and a higher performance than the previous version.

X-FAB Semiconductor Foundries AG says it has a new, patented PIN-diode module for its 0.6-micron BiCMOS technology (XB06). The company says it's now possible to integrate PIN diodes (PIN = positive intrinsic negative) with CMOS and BiCMOS transistors on a single chip.

Xilinx announced the EasyPath FPGAs, described as "the industry's only customer-specific and flexible solution for volume production priced lower than structured ASICs."

Xilinx also announced two new devices in the CoolRunner-II CPLD product family, the CoolRunner-IIA available in 32 and 64 macrocell densities. The XC2C32A and XC2C64A devices incorporate an additional I/O bank to support voltage level translation and device interfacing. Xilinx is also offering the two devices in smaller footprint, lower cost packages.

ZMD announced a sub-1GHz, IEEE 802.15.4 development kit for ZigBee applications, the ZMD44101DK, which lets developers perform detailed evaluation of ZMD's low-power ZMD44101 RF transceiver using a graphical interface.

AccelChip Inc. announced what the company describes as significant new MATLAB language support that improves the ability to create forward-error correction algorithms written in MATLAB for synthesis and verification in its AccelChip DSP Synthesis product. Enhancements include: a new AccelWare Advanced Math Toolkit with matrix inversion and factorization to generate hardware implementations of complex algorithms used in wireless communications applications; new IP cores including Reed-Solomon decoding; new native Galois field support in the AccelChip DSP Synthesis tool; Improved support for two-dimensional array operations; wider variety of designs using matrix- and array-based operations can be synthesized and verified using AccelChip products; support for Virtex-4 devices; and support for Cadence’s Incisive Simulator

Agilent Technologies Inc. and Synopsys Inc. announced a new diagnostics reference methodology, which has been designed to speed fault localization and failure analysis. The methodology relies on the Agilent 93000 SmarTest Program Generator (PG) 2.2 and the Synopsys TetraMAX ATPG tool, in conjunction with the Agilent 93000 SOC Series test platform. The companies say the combination of tools automates the bi-directional information sharing between EDA and ATE required for scan diagnostics.

Aldec, Inc. announced the release of Active-HDL 6.3, described as the Actel edition. The company says that when Active-HDL is connected with Actel Designer (aside from synthesis), the system becomes a closed environment to the engineer. It has unrestricted VHDL, Verilog, EDIF or mixed simulation, which can execute all Actel implementation tools from the Active-HDL GUI. Active-HDL is compatible with most third-party synthesis tools from various companies including, Synplicity, Magma, Synopsys, and several FPGA-vendor provided tools.

Altium Ltd. announced that its Nexar system design software has been updated to support v4.2 of Altera’s Quartus II development software. James Smith, Director of EDA Vendor Relations at Altera, is quoted: “As the only development tool that supports FPGA, CPLD and structured ASIC designs, the Quartus II software allows Altium customers to easily target their prototyping and production solutions using our programmable logic devices.”

Aprio Technologies Inc. announced the release of its first products, the Halo suite of tools, which include Halo OPC, Halo Sim and Halo-Cal. The company says the products deliver a “fresh and effective answer to the thorny problems that come with chip design re-spins, designs that need OPC (optical proximity correction) modification to solve yield issues, or modified designs that require a quick change to mask data (also called ECOs). Because qualification of an OPC tool can take considerable time and require several test wafers, Aprio has chosen to architect its Halo suite to leverage incumbent OPC tools when applicable. In those instances, the Halo-Cal tool is used to generate models for Halo-OPC and Halo-Sim that mimic the behavior of the already-qualified tool. This calibration tool makes it possible to use Halo-Sim for finding errors in existing OPC results while Halo-OPC is then used to fix those errors in a style consistent with the tool initially used.” Aprio says the Halo suite of tools complements existing OPC generation tools that have already been qualified by the manufacturer.

ARM announced that LG Electronics, Inc. has licensed ARM OptimoDE embedded signal processing technology for use in LG’s video encoding and decoding product lines. LG says the first product that will use from OptimoDE technology is an H.264 based HDTV. The technology will be expected to provide the processing performance required by HDTV frame rates and frame sizes, while still retaining reprogrammablity to accommodate multiple video decoding standards.

BYO Solutions, Inc. announced the Partition-Pro partition tool designed for partitioning "big ASIC design in RTL description across multiple FPGAs automatically."

Cadence Design Systems, Inc. announced that NEC Corp. used Cadence’s Encounter design platform to develop “the complete 90-nanometer chipset for one of the world’s fastest vector supercomputers. With Encounter technology, NEC achieved a 2x improvement in chip performance on its most advanced, highest performance 90-nanometer vector supercomputer chipset to date. The NEC SX-8 chipset is comprised of four 90-nanometer designs, including a hierarchical 9-million instance chip that was routed flat for final engineering change order implementation and rapid design closure.”

Cadence also announced that Toshiba America Electronic Components, Inc. (TAEC) has introduced a design kit for Custom SoC and ASIC customers using Cadence’s Encounter RTL Compiler synthesis. The new kit supports designs for implementing in TC280 (130-nanometer), TC300 (90-nanometer), and newer process technologies.

Cadence also announced that Oki Electric Industry Co., Ltd. has taped out a chip for Oki’s uPLAT SoC design platform with Cadence’s Encounter RTL Compiler synthesis. The companies say that with Encounter RTL Compiler, Oki reduced power by 45 percent and area by 12 percent.

Cadence announced the release of Encounter Conformal Constraint Designer, which the company says automates the generation and validation of design constraints at all stages of the design process from RTL to final netlist. The company says the product performs comprehensive design constraint quality checks that help reduce the number of iterations due to invalid constraints. Design constraints are used to direct synthesis, timing analysis and place and route to meet a chip's timing, area and power requirements. Encounter Conformal Constraint Designer is designed to help pinpoint the root cause of constraint problems.

Cadence announced new capabilities that the company says will enable wireless chip designers and manufacturers to have better insight into the mixed-signal and RF challenges that surround wireless design. The new Cadence product offering combines "new Cadence RF extraction technology, two new design flows tailored for wireless chip design, Engineering Services, silicon-proven IP, and integration with technology from industry-leading Cadence partners Agilent, CoWare, Helic, and Mathworks. The RF IC flow [features] Assura RF, the new Cadence technology that delivers complete extraction for RF design. The two new design flows that are included [are] based on 802.11b wireless LAN design IP. These flows enable simultaneous verification of the RF, analog and digital domains together and verification of the wireless IC design in the context of the system. The flows integrate technology from Cadence partners to help streamline wireless design."

Celoxica announced that important algorithm IP, and a block-based graphical design entry platform, have been added to the company’s portfolio of ESL design tools. Jeff Jussel, Vice President of Marketing at Celoxica, is quoted in the Press Release: “There are two popular methods of design entry in ESL design tools; block-based schematic-style entry and software-style algorithmic coding using text-based descriptions. With PixelStreams, we’ve fused these approaches in a block-based graphical editor manipulating a library of C-based video processing models as well as custom C-language models. When combined with C-language synthesis, PixelStreams provides the absolute fastest way to get from algorithm concepts to hardware implementation for applications using these imaging functions.”

Celoxica also announced version 3.1 of its DK Design Suite, DK3.1, which is designed to provide high-level system co-design, verification and C-based synthesis for complex algorithm implementation to high-density FPGA and Programmable SoC devices. DK3.1 also includes performance upgrades to the Nexus-PDK co-verification environment and new device support in the integrated Platform Developers Kit (PDK) board and processor support packages. DK3.1 enhances the implementation path from prototype to SoC through high-level synthesis characterized by IEEE compliant VHDL and Verilog output, automatically generated from complex C algorithms.

CoWare Inc. announced an expansion to its ConvergenSC Model Library with the addition of ARM PrimeCell peripherals. The library now contains IP platform models for peripheral. The companies say that their cooperative effort has allowed CoWare to use the golden RTL and test benches to create these SystemC PrimeCell models.

CriticalBlue announced it has completed a benchmark project validating its Cascade tool with respect to Synopsys’ RTL implementation flow. The company says it worked with a "leading" semiconductor company who defined the embedded software benchmark example and its target gate count and performance constraints, and Cascade determined the available solution space and to generate synthesizable RTL for suitable co-processor architecture. No modifications were made to the original embedded software. Synopsys DC and VCS were provided to CriticalBlue through a Synopsys marketing program.

Denali Software announced that Ubicom, Inc. has selected Denali’s verification IP products for its chip design and verification projects. The companies say that Ubicom engineers use Denali’s PureSpec verification software to model and simulate interactions between its chips and other devices in the target system.

Forte Design Systems announced that Toshiba Corp. has chosen Forte’s Cynthesizer SystemC behavioral synthesis product for use in their SystemC design flow. The companies say they have entered into a multi-year agreement to use Cynthesizer in Toshiba’s next-generation system-level ICs for the consumer, networking and computer markets. Seiichi Nishio, Senior Manager of Methodology at Toshiba, is quoted: “ After extensive evaluations, we determined that by using Cynthesizer, we can substantially reduce the time to design and implement next generation products so that we meet customer needs while taking advantage of the increasing performance and complexity that our advanced technologies provide.”

HARDI Electronics AB announced availability of a new motherboard in the company’s HAPS family, designed for access to multi-gigabit serial links, embedded PowerPC processors, and 1600+ pairs of LVDS signals. The board is named HAPS-20 and is for designers who need high-speed prototypes of large ASICs. The board can be used as a stand-alone device to prototype ASIC designs up to 4 million gates. Capacity can also be increased by stacking two or more HAPS-20 boards together. The HAPS-20 conforms to the HAPSTrak standard, and therefore is backward and forward compatible with various generations of HAPS motherboards and daughter boards.

IMEC announced that it has achieved what is described as the smallest triple-gate device SRAM cell reported to date. The device is a 6-transistor SRAM cell with an area of 0.314mm2. The SRAM cell has a static-noise margin of 240mV at 1.0V operation and shows good functionality down to 0.4V with a symmetric butterfly curve. The cell also shows great potential for scaling down to the 32nm node.

Knowledge*on Semiconductor announced the availability of new design kit for the Agilent Technologies’ Advanced Design System (ADS). The design kit contains various passive components, as well as the three types of HBT. The companies says that RF engineers will benefit from the design kit because it includes accurate models for 214 inductors, 30 capacitors, resistors, via hole, pad and transmission line, which the foundry provides with. The design kit has a temperature scalable HBT model; the accuracy of the model is confirmed through temperature dependent DC and frequency measurements.

Magma Design Automation Inc. announced QuickCap NX, which the company describes as an enhanced” version of its QuickCap parasitic capacitance extraction tool. Added capabilities include: new process modeling, technology model encryption, a parallel execution mode, reference-level SPICE netlist generation, and a new 3D graphics viewer. Per the Press Release: “QuickCap NX is a highly accurate 3D solver that precisely models advanced process effects such as OPC, CMP and trapezoidal wires … With better process models, QuickCap NX users can do more accurate noise and timing analysis and achieve design closure faster. QuickCap NX also includes technology file encryption capabilities that provide foundries with a secure method of sharing additional process information with their customers, allowing them to further enhance the accuracy of their parasitic extraction. Magma has added a 3D graphics viewer to simplify and accelerate the debug of new complex circuit structures and technology files. QuickCap NX also provides parallel operation to reduce runtime.”

MagnaChip Semiconductor announced a new Process Design Kit (PDK) that supports Agilent’s RF Design Environment (RFDE) EDA software. MagnaChip says the PDK contains the full frequency range for its 0.18-micron mixed-signal/RF CMOS processes, from DC through baseband and into the RF range, thus allowing designers to simulate the entire SoC design and therefore ensuring correct operation at all frequencies. At the 0.18-micron node, these frequencies typically range from the audio and video frequencies in the baseband to 5 GHz in the RF band. In the future, designers are expected to be able to produce frequencies of higher than 10 GHz in the 0.13-micron node.

MatrixOne, Inc. announced that Comau Pico selected MatrixOne as its standard PLM environment. Comau Pico says that its adoption of MatrixOne PLM comes after several successful implementations of MatrixOne in other business units of the Comau Group.

Mentor Graphics Corp. announced that its Platform Express XML-based rapid SoC design creation tool now supports the SPIRIT 1.0 specification for IP design reuse. Ralph von Vignau, Chairman of SPIRIT and Director Technology & Standards of Philips Semiconductors, and CTO for the Reuse Technology Group, is quoted in the Press Release: “The success of SPIRIT depends on EDA vendors supporting the standard with their tools. Mentor is a technology contributor and active participant in creating the SPIRIT standard, so it’s great to see this work being successfully deployed in Platform Express.”

Mentor Graphics announced that TSMC used a comparison of Calibre xRC results, field solver data and silicon measurements as part of the validation for its 90-nanometer process technology. The companies say that TSMC and Mentor Graphics worked collaboratively on the test structures and the measurement technique to accurately quantify and measure 90-nanometer parasitic effects.

MIPS Technologies, Inc. and Virage Logic Corp. announced that using a MIPS32 24Kc core plus Virage Logic's Area, Speed and Power (ASAP) Logic High-Density (HD) libraries and ASAP Memory HD memories in a TSMC 0.13G process, the companies have produced a tape-out ready design for a 333 MHz processor in 3.7 mm2, consuming 166.5 mW and delivering 480 Dhrystone MIPS (DMIPS) performance.

Open Core Protocol International Partnership (OCP-IP) announced the availability of CoreCreator 4.0. OCP-IP says that CoreCreator provides a single graphical or command-line-based environment for validating Open Core Protocol (OCP) implementations. Version 4.0 is fully compliant with, and supports OCP 2.0. CoreCreator 4.0 streamlines generation and packaging of core models, interfaces, timing parameters, synthesis scripts, test vectors, and verification suites necessary for efficient IP core reuse and SoC integration.

The Optical Internetworking Forum (OIF) announced that six of its member companies will demonstrate interoperability functionality using the OIF’s recently approved Common Electrical I/O (CEI) Implementation Agreement (IA). The demonstration will take place at DesignCon 2005, and will include Altera, Interconnect Technologies (A Northrop Grumman company), Molex, Tyco Electronics, Vitesse and Xilinx. Test equipment from member companies Agilent Technologies Inc. and Tektronix, Inc. will provide test equipment for the demonstration.

Prosilog SA announced the release 2.2 of its Magillem platform-based design tool. The company says this release includes the “SPIRIT Editor” module, which allows the packaging of IP blocks according to the SPIRIT 1.0 specification released in December 2004. Ralph von Vignau, SPIRIT Chairman, is also quoted in the Prosilog Press Release: “We are pleased with the traction that SPIRIT has gained in the market with the delivery of the version 1.0 specification. Companies such as Prosilog, are delivering SPIRIT-compliant EDA tools, demonstrating that an ecosystem focused on an open standard for IP reuse is building rapidly.”

Pulsic Ltd. announced that it has licensed its Lyric Physical Design Framework to ON Semiconductor. ON Semiconductor says it has licensed Lyric components for floorplanning, standard cell placement, interactive editing and automatic routing of its next generation of mixed-signal designs.

QualCore Logic announced availability of 15 “silicon-validated” analog IP cores and special inputs/outputs (I/Os) for graphics and memory interface applications. Each of these was successfully validated in 0.13-micron process technology from two leading foundries to reduce risk and accelerate product development of system-on-chip (SoC) designs. The 15 analog IP cores and special I/Os are available in the 0.13-micron 1.0v/3.3v process technology and are delivered as GDS II files. Mahendra Jain, QualCore Logic’s President and CEO is quoted: “QualCore Logic’s strategy is to build the largest and most diverse portfolio of silicon-validated analog and mixed-signal IP and special I/Os. These 15 new IP cores bring that number to more than 400.”

ReShape, Inc. announced it has shipped its enhanced PD Builder, which the company says supports SoC Encounter Global Physical Synthesis (GPS) from Cadence Design Systems. ReShape says it worked in collaboration with multiple customers that use Cadence software and, utilized the PD Builder Open Flow feature to insert "expert tool user practices" into its programmable reference design flow.

SMSC and TransDimension announced completion of USB-IF On-The-Go (OTG) compliance testing of a Hi-Speed USB solution utilizing a stand-alone transceiver. Per the Press Release: “TransDimension’s Hi-Speed USB controller IP with a UTMI+ Low Pin Interface (ULPI) interface block and SMSC’s USB3300 ULPI stand-alone physical layer transceiver (PHY), are the first Hi-Speed USB products to pass OTG compliance testing, which is governed by the USB Implementers Forum (USB-IF). ULPI modifies the well-known UTMI+ link/PHY interface to significantly reduce the pin count necessary for discrete USB transceiver implementations to support host, device or OTG functionality.”

Synopsys, Inc. announced that Winbond Corp. has used Synopsys’ Galaxy Design Platform for Winbond’s latest 130-nanometer MPEG-4 multimedia chips - and had first-pass success. Per the Press Release: “Winbond’s MPEG-4 chip is representative of leading-edge 130-nm designs, where utilization of greater than 80 percent of the silicon area is fast becoming the norm. Congestion and increased risk of SI issues are more prevalent in chips of this density, and can contribute to significant increases in chip failure, declines in yield at target frequencies, and reduced performance.” Edward Wan, Senior Director of Design Services Product Marketing at TSMC, is quoted in the Press Release: “Synopsys and TSMC have partnered to ensure that our mutual customers targeting TSMC’s advanced technologies can take advantage of TSMC Reference Flow 5.0 and TSMC in-house library to achieve the best quality of results, accuracy, and time to volume. Winbond’s silicon success demonstrates that our combined flow and TSMC in-house libraries are proving to be seamlessly integrated and highly effective for the most complex designs.”

Synopsys, Inc. and Grace Semiconductor Manufacturing Corp. announced that Synopsys' Professional Services group and Grace have jointly developed a reference design flow for Grace's 180-nanometer processes. The companies say the RTL-to-GDSII flow is based on Synopsys' Galaxy Design and Discovery Verification platform, and that end-users can download the pre-verified reference flow, which is available immediately from Grace.

Synopsys also announced that UMC is using Synopsys’ alternating aperture phase-shift mask (AA-PSM) technology to improve manufacturability for its 90-nanometer process. The companies say the manufacturability improvements are achieved through increased lithography resolution, a larger process window, and better performance. They also say that UMC and Synopsys engineers worked together to retarget an FPGA chip to the AA-PSM process using Synopsys’ DFM flow.

Synopsys also announced that Artisan Components, Inc. has standardized on Synopsys’ ESP full-custom memory equivalency checker for its new low-power, high-density Metro Platform memories. Dhrumil Gandhi, Senior Vice President of Product Technology at Artisan, is quoted in the Press Release: “ In order to support leading-edge low-power design techniques, Artisan’s Metro memories are significantly more complex. Synopsys’ ESP verification solution plays a major role in helping us meet our customers’ first-pass silicon requirements.”

Synopsys also announced that CEVA, Inc. has taped out its next-generation high-speed serial interface chips and the CEVA-Teak DSP using Synopsys’ Galaxy and Discovery platforms: Physical Compiler and Astro products for increased capacity, PrimeTime SI tool for signal integrity, Power Compiler products for power management, and VCS and NanoSim software for mixed-signal chip sign-off.

Tensilica, Inc. announced that it has based its FPGA prototyping design flow on the Design Compiler FPGA (DC FPGA) tool from Synopsys. The companies say that DC FPGA supports key design elements of the Tensilica processor.

Tensilica also announced that NVIDIA Corp. has licensed the Xtensa LX configurable processor. The companies say this license will allow NVIDIA to add specialized functions to its outstanding graphics capabilities in new SOC designs. Chris Malachowsky, NVIDIA Co-Founder and Vice President of Hardware Engineering, is quoted in the Press Release: "For the application areas we are targeting, the extensibility and performance of Tensilica’s Xtensa LX microprocessor were key factors in our license decision."

Tensilica also announced that LG Electronics has used the Xtensa configurable processor core to deliver what the companies describe as "the world’s first mobile phone capable of receiving digital broadcast signals. Compatible with the Terrestrial digital-multimedia-broadcast (T-DMB) system, a broadcast system currently being rolled out in Korea, the new mobile phone is powered by a sophisticated digital media processor which was designed using the Tensilica Xtensa processor core and design environment."

Tower Semiconductor announced the availability of Virage Logic’s Nonvolatile Electrically Alterable (NOVeA) embedded memories for production on Tower’s 180-nanometer CMOS logic process. Per the Press Release: “NOVeA is the industry’s first embedded reprogrammable nonvolatile memory (NVM) to be manufactured on a standard CMOS logic process without any additional masks or process steps.”

TransEDA announced SystemVerilog support in new versions of its VN-Cover and VN-Check tools. The company says that by delivering these new versions, TransEDA says it is providing support for the emerging SystemVerilog standard, and that VN-Cover can take advantage of new SystemVerilog constructs such as enumerated types, records, user-defined types, etc., and still accurately measure code coverage on their design in the same way they do with VHDL and Verilog.

Virage Logic Corp. announced its third-generation Self-Test and Repair (STAR) Memory System. The company says the STAR Memory Systems provides “cost-effective on-chip testing and repairing of designs embedding megabits of memories, but adds significant enhancements that result in faster time-to-market, lower test costs, smaller area and better yield for complex SoC designs. The enhancements provide increased intelligence and automation. In nanometer SoC design, soft errors, memory leakage and the need for high-speed testing are just a few of the challenges plaguing designers. These challenges are compounded by the ever-increasing numbers of memory blocks. Virage Logic has added intelligence in both the test and repair architecture and algorithms to meet these challenges. The STAR Memory System’s embedded error-correcting-code (ECC) circuitry employs the widely used Single Error Correction, Double Error Detection (SEC-DED) approach to automatically detect and correct soft errors for improved reliability.”

I spoke by phone with Krishna Balachandran, Senior Director of Product Marketing at Virage, about the announcement. Krishna told me, “We’re announcing a new test and repair solution for embedded memories that advance nanometer processes. The processes have gotten so much more complex, and taking that much longer to mature - while the memory content on the chip is going up dramatically at the same time. People, in the past, were using tens of memories. Now they’re using hundreds, or even over a thousand on a chip, such that memory is now the driver for overall yield on a design. Therefore, it’s appropriate that memory repair and test solutions must provide the avenue towards decent yields and product profitability. In this announcement, we’re addressing the challenges by adding intelligence and automation to the STAR Memory System. It’s a brand new architecture for an evolving product.”

Accelerated Technology announced the Nucleus RTOS for Texas Instruments' OMAP1710 processor. Other components for the OMAP1710 processor include the Nucleus POSIX API, the Nucleus SHELL command line interface and the Nucleus file management software.

Actel Corp. announced its ProASIC3 and ProASIC3E families, which the company describes as its “third-generation of flash-based programmable logic solutions and the world's lowest-cost FPGA. With the ProASIC3/E families, the company says it is addressing the strong market demand for full-featured, cost-effective FPGAs for consumer, automotive and other price-sensitive application areas. In addition, the company announced a device programmer and starter kit, which supports its ProASIC3 and ProASIC3E FPGAs.

Actel also announced the availability of 90 IP cores to support its new ProASIC3 and ProASIC3E device families, which the company says demonstrates its commitment to the deployment of its new FPGAs.

Actel also announced that its Libero 6.1 Integrated Design Environment (IDE) provides complete support for the company's ProASIC3 and ProASIC3E devices.

Aldec, Inc. announced the release of Active-HDL 6.3, Altera Edition with direct support and automation for Altera's Quartus II design software version 4.2, Stratix II FPGAs and HardCopy II structured ASICs. The company says it has produced a Tcl-based script that automates the design flow interface between Active-HDL and the Quartus II software, so the engineer has a closed design environment and the ability to compile and simulate FPGA and HardCopy structured ASIC devices from a single design environment.

Altium Ltd. announced the release of Service Pack 1 for P-CAD 2004, which is Altium's PCB design system. The company describes the current release, SP1, as a “minor update initiated in response to feedback from customers via Altium's P-CAD Forum.”

Anadigm announced AnadigmDesigner2 version 2.5, which has a new Visual C++ Prototyping tool for dynamically reconfigurable FPAAs using the AnadigmVortex development system. The new user interface includes improvements to the CAM browser and handler, and other features, which allows users to create custom filters by manually moving pole and zero positions.

Apache Design Solutions announced the RedHawk-EV dynamic power analysis and verification tool. The company says that RedHawk-EV provides increased coverage for design weakness identification and exploration, automatic supply noise repair for power closure sign-off, and higher capacity for transient simulation of SoC designs. RedHawk-EV is designed to allow designers to verify potential power-related functional and timing behavior, and avoid excessive over-design.

ARM announced that Siemens has licensed the ARM Jazelle Technology Enabling Kit (JTEK) software for use in its next-generation “ARM Powered” feature phones.

Applied Wave Research announced that the company will provide its Microwave Office design suite to Eagle Test Systems to simulate performance of RF boards that are part of the Eagle's ATE products.

Arithmatica, Inc. announced an integrated, front-end flow for mutual customers of Arithmatica and Cadence Design Systems, which the companies say will improve quality of silicon for “math-critical” chips. The new flow was developed as part of the Cadence OpenChoice Program and includes Arithmatica's CellMath silicon IP and Cadence's Encounter RTL Compiler synthesis and Conformal formal verification tools.

Blue Pearl Software, Inc. the Indigo RTL Analysis tool designed for “rapid functional closure.” The company says it will be releasing its timing closure product later in 2005. Indigo identifies functional issues in RTL designs prior to synthesis, and resolves things like synchronization of data crossing clock domains and logic races. Indigo runs at the full chip level, without synthesizing to gates, and analyzes multiple clock domain designs to see that data crossing domain boundaries is synchronized. It recognizes double register, memory and custom synchronization schemes and points to data that re-converges from independent synchronizers.

Cadence Design Systems, Inc. announced that ATI Technologies Inc. is now using Cadence's new Palladium II acceleration/emulation system to “significantly accelerate” the functional verification of ATI's high-performance digital television (DTV) chip designs.

Cadence Design Systems also announced that Sanyo Electric Co., Ltd. had achieved an “important” production tapeout using Cadence's Encounter digital IC design platform, which helped “decrease power consumption of an important block of Sanyo's chip by 10 percent, while maintaining critical performance requirements.”

Cadence Design Systems and Rising Microelectronics Co., Ltd. announced that Rising has started sampling a SCDMA/GSM dual mode (1.8GHz SCDMA and 900MHz GSM) RF IC transceiver. The companies say the transceiver was designed using the Cadence Virtuoso and Encounter design platforms, and was implemented on IBM's 0.18um BiCMOS 7WL process and process design kit (PDK) developed and qualified by IBM for Virtuoso technologies.

Cadence also announced that its tools helped Fujitsu to achieve “first-pass silicon” on 66 recent, consecutive designs.

Cadence also announced that its Encounter digital IC design platform helped Silicon & Software Systems design multiple 90-nanometer designs over the past 18 months. The companies say the designs ranged in complexity and size from 1 million to 10 million gates, and exhibited performance metrics of 600+MHz.

Celoxica announced its Agility Compiler for SystemC, which the company says includes system design capabilities for synthesis of SystemC models to hardware. “It produces IEEE-compliant RTL descriptions as input to various, currently available ASIC/SoC synthesis flows, and then generates gate-level EDIF netlists for what the company describes as “high density” PLDs … The direct path from SystemC to hardware closes a critical gap in the ESL design flow for successful SoC design from system-level models. Agility Compiler synthesizes a complete hardware system with no artificial limitations on design hierarchy, structure, timing or interfaces.”

Celoxica also announced that within the Synopsys in-Sync program, it formalized the interoperability between Celoxica's Agility Compiler and DK Design Suite and Synopsys' Design Compiler.

Celoxica announced, as well, an agreement with Toshiba Corp. to provide its DK Design for application design and development using Toshiba's Media Embedded Processor (MeP) digital media SoC. The multi-year agreement covers C-based design entry, simulation, co-simulation and synthesis, as well as development hardware, through the availability of a MeP RapidPlatform developers' kit.

CoWare Inc. announced a new option for its SPW 5-XP DSP application solution for Windows that the company says “enables early verification of complex embedded DSP designs. “Using the option, designers who are developing DSP applications can reuse their SPW 5-XP reference models for verification of embedded software for TI TMS320C6000 and C5000 DSP platforms developed using TI's Code Composer Studio (CCStudio) IDE.”

CoWare also announced its SPW DSP application design tool has been integrated with the new Cadence Virtuoso custom design platform for RF designers.

CriticalBlue says it has validated its Cascade tool with respect to Synopsys RTL implementation flow. The work was completed in conjunction with “a leading semiconductor company who defined the embedded software benchmark example and its target gate count and performance constraints. No modifications were made to the original embedded software.”

EMA Design Automation announced that RadiSys Corp. has adopted the Cadence Allegro system interconnect design platform 600 series at all of its design centers.

IBM and Chartered Semiconductor Manufacturing announced they are expanding their joint development efforts to 45-nanometer bulk CMOS process technology. The companies say that when development is complete, they'll have a common process platform which span three generations of process technology. This 45-nanometer joint effort is a continuation of an agreement signed in November 2002 to jointly develop and align on 90-nanometer and 65-nanometer on 300mm silicon wafers.

Chartered Semiconductor Manufacturing also says it has begun prototyping customer products at its 300mm facility at multiple advanced technology nodes. The company says pilot production activities are currently running on Chartered's 0.13-micron process, the 90-nanometer cross-foundry platform jointly developed by Chartered and IBM, and the 90-nanonmeter SOI process.

IBM, Sony Corp., Sony Computer Entertainment Inc. and Toshiba Corp. (Toshiba) announced a multi-core architectural design, which includes floating point performance with observed clock speeds at 4+ GHz. The new microprocessor is code-named Cell. The prototype chip is 221 mm2, integrates 234 million transistors, and is fabricated with 90-nanometer SOI technology.

IMEC announced it has produced a 5GHz and 15GHz low-power voltage controlled oscillator (VCO) by post-processing high-quality inductors on top of 90-nanometer RF CMOS devices using a thin-film wafer-level packaging (WLP) technology. IMEC's thin-film technology uses alternating layers of BCB (benzo-cyclobutene dielectric) and thick electroplated Cu layers deposited on top of the passivation. The post-processing is compatible with both Cu and Al back-end.

LogicVision, Inc. announced that Open-Silicon is using LogicVision's embedded memory-test and repair-analysis technology as part of its standard tool flow in ASIC designs. Additionally, the companies announced that LogicVision will collaborate with Open-Silicon to add automatic memory repair to Open-Silicon's tool flow.

M2000 announced 90-nanometer FlexEOS embedded FPGA macros, The company says the new macros have 1,000+ reprogrammable look-up tables (LUT's) per mm2 and performance capable of 2.7 GHz. The macros have 98,304 LUTs, are SRAM based, and can be dynamically reconfigured to change the functionality of ASIC and SoC circuits after silicon processing and packaging.

Magma Design Automation Inc. announced that Texas Instruments Inc., and Sun Microsystems will use design software from Magma as part of a collaboration on a next-generation computer system chip set.

Magma Design Automation also announced that Enuclia Semiconductor has selected Magma's front-end tools, Blast Create and Blast Plan Pro, to prototype designs in FPGAs and structured ASICs, and then move them into to Enuclia's ASIC/COT (customer-owned tooling) design flow.

Mentor Graphics Corp. announced that LSI Logic has licensed Mentor's 10/100/1000 Ethernet Media Access Controller (MAC) IP core. The companies say the core has been proven in silicon and has been pre-verified and tested for integration into SoC designs. Mentor Graphics acquired their line of Ethernet IP from Alcatel in July 2003.

Mentor Graphics also announced that its suite of synthesis products supports Altera Corp.'s new HardCopy II structured ASIC family. The companies say that Precision RTL Synthesis and LeonardoSpectrum tools are now available in relationship to HardCopy II devices.

Mentor Graphics similarly announced that its suite of synthesis products has added support for Actel Corp.'s new ProASIC3 and ProASIC3E FPGAs. Users of the Precision RTL Synthesis tool from Mentor Graphics can request software updates for designing with the new devices. Initial support for ProASIC3/E in the Precision Synthesis tool suite has been available to some customers since October 2004.

Nascentric, Inc. announced its Nascim fast-SPICE simulation technology, with current-based transistor models to reflect actual current flow and current density in CMOS circuitry. The company says it's the first in a series of simulation and analysis products being developed by Nascentric. The suite of products intends to focus on transient physical and electrical effects that negatively impact timing, power and signal integrity in nanometer designs, effects such as IR drop, leakage currents, electromigration, and cross-coupling.

ProDesign announced the availability of the CHIPit Gold Edition Pro high speed ASIC design verification platform for multimedia ASIC and SoC design. Uses range from the initial phases of design algorithm creation, through the basic IP development and debugging, to the validation of complex SoC designs and early “quasi prototyping” for firmware and software development.

Pulsic Ltd. announced that Elixent has licensed its Lyric Physical Design Framework. Elixent says it will use Lyric for automatic and interactive routing of its advanced cell designs for its D-Fabrix RAP cores. The D-Fabrix array is automatically compiled from a library of cells designed at the transistor level to optmize possible speed and power performance in the smallest possible area.

QuickLogic Corp. announced a partnership with Renesas Technology Corp. to develop an 802.11b/g IP phone reference platform, which the companies say will target the Wi-Fi market. The reference platform will be designed based on Renesas' SH7720 32-bit RISC processor and QuickLogic's low-power programmable PCI bridge.

QuickLogic also announced the company's Eclipse II family of low power FPGAs are now qualified for operation at the extended industrial temperature range, -40 degrees to +100 degrees Celsius device junction temperature.

ReShape, Inc. announced it has shipped its enhanced PD Builder, which the company says supports SoC Encounter Global Physical Synthesis (GPS) from Cadence Design Systems. ReShape says the company worked in collaboration with various Cadence software users so the PD Builder Open Flow will include best practices in its programmable reference design flow. Designers using PD Builder, can work in conjunction with physical design tools from Cadence, Mentor Graphics, and/or Synopsys.

Sandwork Design, Inc. announced that its analog and mixed-signal circuit debugging tools have been incorporated into the design flow of ON Semiconductor Inc.'s design centers.

Silicon Dimensions, Inc. announced support for AMD's 64-bit Linux platforms in its Chip2Nite suite, so now Chip2Nite users can have access to “64-bit computing with applications involving large data sets and computationally intensive tasks.” The company says that Chip2Nite currently supports Red Hat 7.2, 7.3, and 8.0 and Red Hat Enterprise Edition 2.1 and 3.0.

Sonics, Inc. announced that Toshiba Corp. will design the SonicsMX and Sonics3220 SMART Interconnects into a new family of wireless handheld products. The companies say that Toshiba currently uses Sonics' Silicon Backplane SMART Interconnect and Sonics' MemMax Memory Scheduler in its processor-based digital consumer product.

Synopsys, Inc. announced that Aarohi Communications, Inc. is now using Synopsys' VCS RTL verification tool for the functional verification of Aarohi's “next-generation” FabricStream intelligent storage product.

Synopsys also announced release of its DesignWare Hi-Speed Universal Serial Bus (USB) On-The-Go (OTG) controller core, which the company describes as “the lowest gate count IP available on the market.” The core is a modular version of earlier DesignWare Hi-Speed USB and OTG cores.

Synopsys also announced that NetSilicon, Inc. has had “first-silicon success” using Synopsys' Vera testbench automation tool and the VCS RTL verification tool as part of NetSilicon's NS9750 NET+ARM processor verification environment.

Synplicity announced enhancements to its FPGA synthesis software to improve productivity and integration with formal verification, place & route, and debugging products. Enhancements include: integrated formal verification flow support for Cadence's Conformal and Prover Technology's eCheck equivalence checker software; tighter integration with P&R tools from Actel, Altera and Xilinx, and Synplicity's Identify source code debugging product for FPGAs is now integrated into the Synplify Pro product. Also, this version of Synplify Pro software includes support for Actel's ProASIC3 FPGAs and Altera's HardCopy II structured ASICs.

Synplicity and Prover Technology Inc. announced an integrated verification flow for Synplicity's Synplify Pro FPGA synthesis tool. The companies say the flow combines the Prover eCheck equivalence checker and the Synplify Pro 8.0 software, and that users of the Synplify Pro can use Prover's formal verification product in their verification flow. The combined flow automates equivalence checking of Altera and Xilinx FPGA designs.

Synplicity also announced enhancements to its Synplify DSP software, which include new DSP synthesis optimizations for performance and area, additional blockset functionality, including support for saturation/rounding, and a customizable DSP block library so that designers can add custom DSP IP to their library. The company says Synplify DSP gives users of products from The MathWorks with a DSP synthesis path from Simulink to hardware.

TDA Systems Inc. announced a new S-parameter tool, which allows differential S-parameter measurements based on Time Domain Reflection and Transmission (TDR/T) data. The product is available on a stand-alone basis or bundled with TDA's IConnect software, and is designed for digital design, electrical-compliance testing and signal integrity engineers.

TDA also announced version 3.5 of its IConnect and MeasureXtractor TDR and VNA software, which the company says includes the new S-parameter functionality.

Taiwan Semiconductor Manufacturing Company (TSMC) announced a suite of internally developed libraries that support its Nexsys 90-nanometer technology. The libraries include links to TSMC technology and support for design methodologies represented by major EDA, package and IP vendors. The company says the libraries are already in volume production, and are TSMC Reference Flow 5.0 proven and DFM compliant.

Tensilica, Inc. announced the V6 suite of automation tools, which the company says speed ups block design in SoCs design, and makes it easier to design SoCs with configurable processors. The company says a designer with an existing algorithm coded in C or C++ can develop a customized Xtensa LX processor in a day, as opposed to a RTL design cycle that usually requires six to nine months.

Tharas Systems, Inc. announced support for Verilog 4-state logic simulation in Hammer 100. The company says that Hammer 100 can detect and propagate 4-valued logic similar to a Verilog software simulator.

TransEDA announced Expression Coverability Analysis for automatic analysis of conditional expressions for designs written in Verilog, VHDL and mixed languages. The tool uses an embedded formal engine to identify uncoverable expression terms and coverable terms that have not been exercised. Uncoverable expression terms are reported and eliminated from the overall coverage calculation.

TTP Communications plc. and ARM announced collaboration to design and develop 3G IP platforms, which use ARM processors and TTPCom Cellular Baseband Engine (CBEmacro) technology. TTPCom says it will distribute the combined technologies to semiconductor manufacturers. ARM says it will license the processor core to its silicon partners and TTPCom will license the CBEmacro technology.

Virtual Silicon Technology, Inc. announced an integrated digital frequency synthesizer (DFS), the Delta-Sigma Fractional-N Phase Locked Loop product for synthesizing output frequencies to suit an individual project. No special processing is required for mixed-signal circuits.

Zuken says its CADSTAR 3D desktop design tool has been upgraded and now has Windows XP functions, with drag and drop loading of designs, floating toolbars, and modeless and dockable dialogues for Design Browser.

AccelChip Inc. announced its 2005.1 release of AccelWare IP toolkits and AccelChip DSP Synthesis product. The company says its new AccelWare cores "extend the company’s leadership position in cores that directly implement matrix operations for wireless communications, signal processing, and other forward-error correction applications. Additionally, the 2005.1 version of the AccelChip DSP Synthesis tool integrates the algorithmic synthesis environment based on MATLAB with Xilinx System Generator."

Accelerated Technology, a Mentor Graphics Division, announced its Nucleus Inter-processor Communications (IPC) software, which the company says is an application-level tool that enables high-speed communications between two or more processors running on the same chip, computer or over a network.

Accelerated Technology also announced that a Running System Debug (RSD) enhancement supporting the ARM RealView Developer Suite has been added to the Nucleus PLUS real-time kernel. The company says this enhancement will allow the Nucleus software application developers using the RealView RVD Debugger to halt individual Nucleus software tasks without needing to halt the CPU.

Actel Corp. and Prover Technology, Inc. announced that the Prover eCheck equivalence checker has been "validated for design verification" in Actel’s Libero Integrated Design Environment (IDE). In addition, Prover says it has joined Actel’s Alliance Program.

Actis Design, LLC says it has begun shipping AccurateC Release 2.4. the company's static C++ code analyzer for SystemC that Actis calls "the first software tool used in the SystemC code development flow." The company says previous versions were used post compilation, but AccurateC Release 2.4 can analyzes SystemC code prior to compilation, simulation or synthesis, and therefore designers can analyze either one module or the entire SystemC design.

Agilent Technologies Inc. announced major developments in its EDA frequency-domain simulation technologies for RFIC, MMIC, and RF SiP design. The company says, "Simulation speed improvements of up to 50 times have been achieved for large and complex circuits used in wireless communications products and aerospace and defense applications. Customers have observed excellent results with test circuits containing thousands of transistors, such as transceiver ICs for wireless local area network (LAN) applications."

Aldec, Inc. announced its Riviera-IPT with support for the ARM926 hardcore processor including functionality for SMART Clocking for the ARM processor, which allows the designer to combine emulation speed with simulation functionality, and Memory Mapping, which is extended memory support to permit the designer to emulate various RAM architectures in a single device while at the same time substantially reducing the simulator overhead that would normally be required to handle these memories.

Altium Ltd. announced a product roadmap for its P-CAD technology. The company says the roadmap is "an insight into Altium’s ongoing support and development of P-CAD, and demonstrates Altium’s commitment to meeting the current and future design needs of its customers."

Altium also announced version 2.2 of its TASKING TriCore VX-toolset. The company says new features are "aligned" to Infineon’s 32-bit TriCore microcontrollers, and include: Code performance improvement of up to 25%; Build speed improvements – compiler time reduction of 55% and overall assembler improvements of around 80%, Extensive support for Infineon’s Debug Access Server (DAS) solution, and TCP/IP stack reference design as sample project.

Ansoft Corp. says it has released a new version of AnsoftLinks that includes support for Mentor Graphics PADS Layout (formerly PowerPCB). The company says that AnsoftLinks allows for direct import of third-party PCB/CAD databases into Ansoft's electromagnetics software. Additional enhancements in AnsoftLinks include: simplification of the vias option for solid-model export; via fill option to define thickness in model units; ability to define a number of facets for pads and antipads; exportation of defeatured Ansoft files with plane extents; Integration enhancements for other third-party tools from Cadence, Mentor Graphics, Synopsys and Zuken.

Apache Design Solutions announced that STMicroelectronics has adopted Apache’s SoC power closure sign-off flow for its on ST’s Nomadik low-power application processor designs.

Apache also announced its RedHawk-EV dynamic power analysis and verification tool. The company says that RedHawk-EV provides increased coverage for design weakness identification and exploration, automatic supply noise repair for power closure sign-off, and higher capacity for transient simulation of SoC designs.

Applied Wave Research, Inc. (AWR) announced an agreement with TriQuint Semiconductor that will add AWR’s Microwave Office and Visual System Simulator (VSS) software to TriQuint’s EDA tool set.

Arithmatica, Inc. announced that Xilinx, Inc. used Arithmatica's CellMathT IP in its Virtex-4 SX55 FPGA. The companies say the SX55 device delivers 256 billion multiply-and-accumulate per second (MAC/s) processing performance, and with 512 XtremeDSPT Slices, is the "highest-performance" member of the SX family.

Arteris SA announced its first product offering, which the company describes as "a complete solution for creating Networks-on-Chip (NoC). Arteris NoC Solution is used to connect and manage the communication between the variety of design elements and IP blocks required in today's complex SoCs. The company's proprietary IP library utilizes a packet-based switch fabric in conjunction with Arteris NoC specific design tools to generate unique NoC instances. The result is the first commercial NoC solution that overcomes the limitations of traditional bus-based methods, while maintaining compatibility with existing interface standards and design tool flows."

ASSET InterTech Inc. announced that its ScanWorks JTAG test system has been integrated into Agilent Technologies’ new Medalist i5000 in-circuit test (ICT) system. Agilent says it is including ScanWorks as the JTAG "bundled solution" on its Medalist ICT product line, including the i5000 and 3070 Series systems.

Atmel Corp. and Celoxica Ltd. announced a joint effort that the two companies say will extend ESL design to a family of dynamically reconfigurable processors currently under development at Atmel. The new backend tools are being developed for new processors based on Atmel’s FPSLIC technology that is planned for introduction later in 2005. Tools from Celoxica’s ESL portfolio, the DK Design Suite and Agility Compiler will synthesize hardware accelerators from algorithms described in C or SystemC. Celoxica will also provide its hardware/software co-design technology and board-level integration technology to allow Atmel customers "a seamless implementation flow."

Atsana Corp. announced that Samsung Electronics selected Atsana’s J2211 media processor for its 2 Mpixel SCH-M309 camera phone.

Brion Technologies, Inc. announced its Aerion microlithography aerial image sensing technology platform. Working in the cutting-edge area of lithography, the company is developing products capable of capturing full-field, in-scanner aerial images at resolution and at the wafer plane for 193-nanometer and 248-nanometer wavelengths, under exact production conditions such as illumination scheme, lens settings and stage speed.

Brion Technologies also introduced its Tachyon RDI (RET Design Inspection) "model-based, full-chip verification tool for the production flow of post-RET design verification." The company says the Tachyon RDI 1100 is a hardware accelerated, image-based data and simulation engine for lithography modeling and database handling.

Cadence Design Systems, Inc. announced that its Encounter digital IC design platform helped Silicon & Software Systems design multiple 90-nanometer designs over the past 18 months. The companies say the designs ranged in complexity and size from 1 million to 10 million gates and exhibited performance in excess of 600MHz.

Cadence also announced that its Encounter platform helped GUC tape out seven 130-nanometer designs. The companies say the most sophisticated designs – with 3 million gates and 400 MHz clock speed – were closed with all timing and signal integrity requirements met. That's good news.

Meanwhile, Cadence and Virage Logic Corp. announced results of a collaboration to provide library views that the companies say better address low-power, multi-voltage nanometer designs. Virage says it has generated and qualified timing library views that include the Cadence effective current source model (ECSM) extensions for supply-voltage delay prediction and noise library views (cdB) for signal-integrity analysis. The companies report that when used with Cadence's Encounter digital IC design platform, the new library views will allow design teams to account for crosstalk, IR drop, voltage and frequency scaling, and multiple voltage-island support required for nanometer process technologies.

Cadence also introduced its OrCAD Signal Explorer, which the company describes as a "scalable, personal productivity product line." OrCAD Signal Explorer has new PCB-level topology exploration and signal integrity (SI) analysis technology.

Cadence also announced new design-partitioning technology for the Allegro PCB Editor. The company says the technology helps meet customer demands for "faster time to market and shorter design-cycle times" by assisting with concurrent collaboration for team-based PCB design.

Cadence also announced that Wipro Technologies has renewed an agreement under which Cadence will provide Wipro access to Cadence's technologies. The organizations say that this agreement marks the third renewal of the Cadence-Wipro business relationship over the past eight years Cadence also announced that Wipro taped out its largest design to date using Cadence tools.

Cadence Design Systems also announced Cadence Encounter Test Architect, which the company describes as "the industry's first full-chip test architecture development product. It includes the industry's first unified compiler-based methodology for full-chip test. The result is faster development of a higher-quality test infrastructure than is currently possible with point test tools. Based on a unique test infrastructure compiler, Encounter Test Architect supports a unified methodology for specifying, compiling, and verifying full-chip test. This includes scan, compression, memory BIST, on-product clock generation, boundary scan, and I/O test."

CAST, Inc. announced a new IP core that the company says implements a dual-role host/device controller in conformance with the On-The-Go (OTG) supplement to the USB 2.0 specification.

Celoxica Ltd. announced a new programmable SoC prototyping and development platform, the RC250 package, which the company says gives designers a hardware/software desktop environment for complex system development. The RC250 has an array of peripherals including analog and digital video I/O, two channel gigabit Ethernet and USB2.0. There is a platform support library (PSL) that allows access to the board-level features from the ESL. System level APIs supplied with the RC250 enable hardware/software co-design and architectural exploration of partitions, and helps with IP reuse by abstracting the specific board level detail away from the application code.

Concept Engineering GmbH announced NlviewWX, which the company describes as the sixth engine in its visualization software components that support Tcl/Tk, Java, the Microsoft Foundation Class (MFC) Library, Qt, and Perl. EDA tool developers can use the wxWidget environment to build EDA tools and can use Concept's NlviewWX engine to create GUIs for their EDA tools as well.

First Silicon Solutions (FS2) and Tensilica, Inc. announced that the FS2 System Navigator is available for debug and system integration of SoC designs with Tensilica Xtensa V and Xtensa LX configurable and extensible processors.

IMEC and CoWare say they have signed a "letter of intent to collaborate" towards the development of an integrated design flow for "efficiently mapping advanced multimedia and wireless applications on a flexible and programmable platform." The two organizations intend to close the gap between IMEC's proprietary research tools and CoWare's electronic system-level (ESL) design tools.

iRoC Technologies Corp. introduced its TFIT software, which the company describes as its "Soft Error Design Solution Platform." The software is designed to help analyze the impact of soft error strikes on custom designs in order to help meet reliability targets. Soft errors are defined as "transient faults caused by external radiation – mainly cosmic rays – that affect the logic states of ICs and memories."

Macraigor Systems LLC announced the availability of its J-Scan Version 1.0 boundary-scan debug and programming tool. The company says the new technology "allows circuit designers to facilitate early test development, thereby shortening the development cycle and prototyping process."

Magma also announced that Enuclia Semiconductor has selected Magma’s Blast Create and Blast Plan Pro to prototype designs in FPGAs and structured ASICs. Carl Ruggiero, CTO of Enuclia Semiconductor, is quoted in the Press Release: "Enuclia has been impressed with the ability of Magma’s products to provide for seamless design transitions from FPGA prototyping to structured ASIC, and ultimately to our ASIC/COT design flow.

Mentor Graphics Corp. announced that its TestKompress embedded deterministic test (EDT) tool is being used by UMC in the foundry's 90 and 130-nanometer reference flows. The companies say that TestKompress tool has "proven to reduce manufacturing test time by up to 100x compared to other test alternatives, helping users increase test coverage and test quality on their complex devices without compromising test time or test cost."

Mentor Graphics also announced the release of its latest constraint editor system (CES) into its Expedition Series and Board Station RE PCB design flows. The company says this CES tightly integrates with the entire systems design flow from schematic entry through physical layout, facilitating multi-disciplined communication of high-speed design rules and constraints between engineers, designers and their tools. Constraints can be entered through a common GUI and then automatically accessed by individual tools in their native formats. The CES also supports bi-directional cross probing.

Mentor Graphics also announced a collaboration with VIA Technologies, Inc. to provide reference designs for use with the Expedition Series design flow for VIA’s new P4M800/Pro, PT894/Pro and K8T890/Pro chip sets. The companies say the reference designs are only available through VIA, and will allow Expedition users to reuse design data for

Mentor Graphics also announced that the Fraunhofer Institute for Integrated Circuits (IIS) has selected the Mentor Graphics Catapult C Synthesis tool for use in next-generation digital broadcast applications.

Mentor Graphics also announced "further integration capabilities" between CHS (Capital Harness Systems), the company's electrical design-to-build flow, and Dassault Systemes' CATIA V5 MCAD suite. The companies say that a new data bridge linking CATIA V5 with Mentor's Capital Engineer product is now available.

Mentor Graphics also announced that Renesas Technology Corp. has completed a joint development effort that integrates the Mentor Graphics 0-In Assertion Synthesis technology and assertion-based verification flows with Renesas’ LogicBench rapid prototyping system.

Nassda Corp. – which is in the process of being acquired by Synopsys, Inc. – announced the release of version 6.0 of its HSIMplus, HANEX and CRITIC verification products. The release includes new HSIMplus integrations with hierarchical parasitic extraction and digital simulation software aimed at higher-capacity IC verification for designs that combine analog, mixed-signal, digital and memory IP components. HANEX Version 6.0 enhancements include coverage of a wider range of design types, improved analysis of manufacturing variations on circuit performance and increased speed of analysis. CRITIC version 6.0 supports a streamlined crosstalk analysis flow and utilizes aggressor-only timing window data, or can analyze worst-case path delay if timing windows are not available.

In addition, Nassda and Mentor Graphics say they have collaborated to develop "the industry's first full-chip solution for hierarchical extraction and full-chip simulation of nanometer circuit behavior, signal integrity, power integrity and electromigration effects. The companies say the combination of Mentor Graphic's Calibre xRC extractor and Nassda's HSIMplus simulator provides "improved capacity and efficiency for verifying the impact of nanometer silicon on design performance and can lead to improved chip yield."

ProDesign announced the availability of the CHIPit Gold Edition Pro high-speed ASIC design verification platform for multimedia ASIC and SoC design. The company says the platform can be used for everything from the initial phases of design algorithm creation, through to basic IP development and debugging and the validation of SoC designs, as well as early "quasi prototyping" for firmware and software development.

Prosilog SA announced the integration of Yogitech’s OCP eVC in Magillem, which is Prosilog's platform based design environment. The companies say that eVC is imported, configured and connected to the DUT (Design Under Test). Yogitech’s eVC is registered in the MagillemVerification IP list.

Rambus Inc. and Cadence Design Systems, Inc. announced that Open-Silicon has licensed multiple Rambus RaSer serial link "offerings" through the Cadence-Rambus reseller program. The companies say that under the agreement, "Open-Silicon gains access to a portion of the portfolio of Rambus's silicon-proven, industry-standard RaSer PHY cells for applications such as PCI Express, 10-Gigabit Ethernet/XAUI and Serial RapidIO."

Naveed Sherwani, President & CEO of Open-Silicon, is quoted: "Our customers are looking for the most predictable and reliable ASIC turnkey solution available. Integrating Rambus's serial links into multiple customer designs has been incredibly successful. As an IP aggregator, Open-Silicon can provide this silicon-proven IP to our customers, hence simplifying the transfer of Rambus's IP to ASIC designers."

Opsware Inc. announced that Cadence Design Systems has selected Opsware as its "global IT lifecycle automation solution."

The Silicon Design Chain Initiative announced new design techniques that are said to achieve "total power savings of over 40 percent on a 90-nanometer test design. The low-power design employed an ARM1136JF-S test chip, ARM Artisan standard cell libraries and memories, Cadence Encounter design platform and TSMC's Reference Flow 5.0. Applied Materials, Inc., ARM, Cadence Design Systems, and TSMC form the Silicon Design Chain Initiative.

SoftJin announced plans to provide customized software development and building blocks that address the needs of suppliers in the DFY/DFM and programmable platforms space. The company says its new software building blocks for DFM/DFY products will be announced in Q2 2005. Be on the look out.

Synopsys, Inc. and Oki Electric Co., Ltd. announced that Oki is using Synopsys' new HSPICE high voltage MOS (HVMOS) model for the design of Oki's LCD TV driver SoC. Oki says its design team "achieved unparalleled accuracy using this HVMOS model with HSPICE technology."

Meanwhile, Synopsys and ARM announced a jointly developed low-power reference methodology (RM) for implementing ARM Intelligent Energy Manager (IEM) technology in silicon. The companies say they have proven that the IEM technology, when used with the ARM Artisan low-power library, can reduce the ARM processor energy consumption by up to 60 percent. Please recall that ARM acquired Artisan in 2004.

Synopsys also announced that Virage Logic Corp. has standardized on Synopsys' ESP memory equivalency checker for the embedded memory components of its IPrima Mobile semiconductor IP platform. The companies say the resultant increase in productivity has enabled Virage Logic to reduce the engineering time needed to complete functional verification of the circuits in its Area, Speed and Power (ASAP) Memory compilers from days to hours. Nice.

Synopsys also announced that Synopsys and Hitachi Global Storage Technologies have demonstrated 3Gb/s Serial ATA (SATA) II interoperability between Hitachi's high-performance Deskstar hard drives and the Synopsys DesignWare SATA Host Controller core.

Synopsys also announced DFT Compiler MAX, which the company describes as "its next generation DFT synthesis solution, offering 1-pass test data volume compression capabilities to address design and test challenges occurring in 130-nanometer and smaller process technologies." The company adds that DFT Compiler MAX is an extension of its "1-pass test synthesis solution that delivers push-button test data volume compression of 10-50x, enabling DSM testing for high fault coverage without significant impact on test costs."

Meanwhile, Synopsys and Grace Semiconductor Manufacturing Corp. announced that Grace has adopted Synopsys' DFM tool suite, including the Protease OPC and sill lithography verification tools.

Synopsys also announced that Synopsys' coreAssembler IP integration tool supports the SPIRIT 1.0 IP packaging standard. The company says that coreAssembler is "the only tool that supports a path to implementation in silicon for SPIRIT-compliant IP in addition to system-level integration and verification. Tight integration with the Synopsys Galaxy Design Platform and Discovery Verification Platform helps to achieve superior quality-of-results and speed the time to verification. By providing production support for SPIRIT 1.0, coreAssembler now enables designers to more rapidly integrate the broad portfolio of DesignWare IP, as well as third-party IP compliant with the SPIRIT standard."

Finally, Synopsys announced its Galaxy IC Compiler, which the company describes as "the next-generation physical design solution, endorsed by leading-edge early users including Agere Systems, ARM and STMicroelectronics. It is the first-ever physical design solution which provides concurrent physical synthesis, clock tree synthesis, routing, yield optimization and sign-off correlation, delivering unmatched design performance and productivity."

Tensilica, Inc. announced that it has posted "the highest score ever recorded for a licensable processor core, and the highest absolute score ever published for any processor, on the Office Automation benchmark suite of the Embedded Microprocessor Benchmark Consortium (EEMBC)." The EEMBC benchmark scores are independently certified by the EEMBC Certification Laboratories (ECL). Tensilica says its score confirms that "the Xtensa LX processor is nearly four times faster than the much larger PowerPC 440GX core, and more than 4 times as powerful as the 64-bit MIPS 20Kc processor."

Tensilica also announced that it has "teamed up with leading RTOS and IDE vendors to provide automated customization that match any and all changes designers might make to Tensilica’s new Xtensa LX configurable processor." The company says automated support is now available for Wind River Systems VxWorks and TORNADO II for VxWorks, and the Nucleus RTOS from Accelerated Technology, a division of Mentor Graphics.

Tharas Systems, Inc. announced that ATI Technologies Inc. has its selected Hammer 100 hardware accelerator to help in the verification of ATI's next-generation 3D graphics processor.

TurboTools announced its CablEquity product, first in the company's SystemEquity tool family. TurboTools says it is the first company in the industry that introducing the next generation of engineering automation solutions that "go beyond the capabilities of traditional EDA applications. The SystemEquity is defining the new market segment for EDA tools called System CAD or SCAD. TurboTools views SCAD as an entirely new method of managing system design and manufacturing processes."

VaST Systems Technology Corp. announced the release of CoMET 5.7, with features that include among many enhancements: support for VaST’s models, plus integration and co-simulation with previous generations of VaST models and support for SystemC models, standalone and integrated into full platforms.

VaST Systems also announced the addition of its Peripheral Device Builder (PDB) to the company's line of virtual system prototyping tools. PDB is designed to help VaST users to develop peripheral devices such as interrupt controllers, DMA VaST engines, timers, clocks, and memory controllers. The company says that PDB provides a common code base for VaST-generated peripheral models and enables users to create models from a high level behavioral description.

Verific Design Automation announced an interface between its HDL Component Software and the OpenAccess database. The company says the new interface has a link to Verific’s HDL parser for Verilog, SystemVerilog and VHDL, for fast netlist import, along with RTL support to the OpenAccess 2.2 database.

Verific Design Automation also announced that Silicon Navigator Corp. (SiNavigator) has licensed its HDL Component Software.

Virtio Corp. says it has released a software development model for the Texas Instruments’ TMS320DA295 portable audio playback processor. Virtio also announced support of the TI OMAP family, the VPOM-V1030 Virtual Platform.

X-FAB Semiconductor Foundries AG announced a collaborative agreement with Cadence Design Systems. X-FAB says it will "work closely with Cadence to build and deliver comprehensive design kits for analog and mixed-signal ICs targeting mainstream and advanced process technologies."

Xilinx announced version 7.1i of the Platform Studio tool suite for Platform FPGA embedded processing design. This new is aimed at the company's Virtex-4 FX family.

Xilinx and AccelChip Inc. announced a new interface between AccelChip DSP Synthesis and Xilinx System Generator for DSP tools which "enables rapid development of high performance DSP and communications systems. Jointly developed by Xilinx and AccelChip, this new interface enables designs captured in The MathWorks’ MATLAB language to be rapidly incorporated into System Generator designs for implementation and verification. System Generator for DSP is the framework for developing and debugging high performance DSP systems for Xilinx’s advanced FPGAs. System Generator, together with The MathWorks’ Simulink tool, provides the graphical design environment commonly used by system architects and hardware designers."

ZAiQ Technologies, Inc. and ProDesign Electronics Corp. announced that ZAiQ's SYSTEMware verification software and IP and ProDesign’s CHIPit Systems will be integrated to produce a transaction-based verification platform.

Zuken and LogicSwap have launched a new migration offering that allows users of P-CAD to transfer PCB design data, schematic databases and incorporate libraries to CADSTAR. Users will also be able to convert back to P-CAD if required using the CADSTAR to P-CAD solution. The companies say this development addresses migration concerns related to the preservation of customers' legacy EDA data, by providing solutions and services that accurately and reliably migrate design data, including EDA libraries. They also say that new tool evaluation decisions such as whether or not to abandon legacy data and fears about the loss of investment made in previous designs are no longer an issue, as the constraining factors that previously locked companies into a single supplier solution have been removed.

Zuken also announced that TopSPICE is now available as a simulation engine for the CADSTAR suite of schematic and printed circuit board (PCB) design tools.

Cadence Design Systems, Inc. announced total revenue for the second quarter of 2004 of $287 million compared to $277 million in the same period last year. On a GAAP basis, Cadence recognized net income of $4 million, or $0.01 per share in the second quarter of 2004, compared to a net loss of $5 million, or $0.02 per share in the same period last year.

Magma Design Automation reported revenue of $36 million for the first quarter of fiscal 2005, compared to $22.8 million for the first quarter of fiscal 2004, an increase of 58 percent. Magma reported pro forma net income for the first quarter of fiscal 2005 of $7.7 million, or $0.18 per share (diluted). In accordance with GAAP, Magma reported a net loss of $(2.5) million, or $(.08) per share (diluted), for the first quarter of fiscal 2005.

Magma Design Automation also announced that its board of directors has authorized the company to repurchase up to 1,000,000 shares of common stock. Acquisitions for the share repurchase program will be made from time to time in private transactions or open market purchases as permitted by securities laws and other legal requirements. The program may be discontinued at any time without prior notice. The company currently has approximately 33.7 million shares outstanding. No time limit was set for the completion of the program.

Mentor Graphics Corp. announced second quarter pro forma diluted earnings per share of $.14, up 17 percent year on year, on revenue of $169.6 million. Earnings on a GAAP basis were a loss of $.47 per share, a result principally of income tax charges on a one-time dividend from a foreign subsidiary. Revenue grew 8 percent over the year ago quarter, while bookings grew 6 percent.

Synplicity, Inc. announced financial results for the quarter ended June 30, 2004. Revenue for the quarter was $14.2 million, a 16 percent increase from revenue of $12.2 million for the quarter ended June 30, 2003 and a 5 percent sequential increase from revenue of $13.5 million for the quarter ended March 31, 2004. On a GAAP basis, net income was $469,000 or $0.02 per diluted share for the quarter ended June 30, 2004, which included amortization of intangible assets from acquisitions of $222,000 and stock-based compensation expense of $57,000.

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EDAC’s Numbers - The EDA Consortium’s Market Statistics Service (MSS) announced that EDA industry revenue for Q1 of 2004 was $995 million, a 6-percent increase over Q1 2003. * Services revenue increased to $76 million, a 31-percent increase over Q1 2003. * Semiconductor intellectual property was $78 million, a 15-percent increase over Q1 2003. * EDA license and maintenance revenue was $840 million in Q1 2004, a 3-percent increase over Q1 2003, and 84 percent of the total reported revenue. * Computer-aided engineering generated revenue of $470 million in Q1 2004, a 6-percent increase over Q1 2003. * PCB and multi-chip module layout revenue was $85 million in Q1 2004, a 5-percent increase over Q1 2003. * IC physical design and verification revenue of $285 million was down slightly from $288 million in Q1 2003.

Synopsys Inc. reported revenue of $281.7 million for the third quarter of fiscal 2004, a 6-percent decrease compared to revenue of $300.4 million for the third quarter of fiscal 2003. For the 9-month period ended July 31, 2004, revenue was $861.5 million compared to revenue of $860.5 million for the same period in 2003. On a GAAP basis, third quarter of fiscal 2004 produced a net income of $41.8 million, and GAAP net income for the 9-month period ended July 31, 2004 was $102.7 million, compared to $105.1 million for the same period in fiscal 2003.

ARM Holdings plc and Artisan Components, Inc. announced that the companies have entered into a definitive agreement under which ARM will acquire Artisan. Details include:

* Warren East, CEO of ARM will continue as CEO of the combined companies, with Lucio Lanza, Chairman of Artisan, and Mark Templeton, President and CEO of Artisan, joining the Board of Directors of ARM as a non-executive director and an executive director, respectively. Templeton is expected to enter into a service contract with the company with effect from completion of the transaction.

* The completion of the transaction is expected to occur in Q4 2004 and is subject to ARM and Artisan stockholder and regulatory approvals and other customary closing conditions.

* Based on closing prices for ARM’s ADSs as of August 20, 2004, the implied value is $33.89 per Artisan share, representing an aggregate consideration of approximately $913 million.

* As of June 30, 2004, under U.S. GAAP, Artisan had revenues and profits after taxes in the previous 12 months of $82.9 million and $17.3 million, respectively, and had net asset value of $205.1 million, of which $140.4 million was cash, cash equivalents and marketable securities.

* ARM has agreed to pay a break-up fee to Artisan of approximately $18 million payable upon certain termination events under the transaction agreement. Alternatively, Artisan has agreed to pay a break-up fee to ARM of approximately $31 million or $18 million, depending on the nature of the termination event, payable under the transaction agreement upon certain termination events.

EMA Design Automation announced the formation of the EMA Consulting Services Group to “make available high quality, enterprise-wide OrCAD Capture CIS implementations. Key factors are library data management and interfaces into the customer’s MRP system to leverage items such as cost information, parts availability, and preferred part lists. The EMA Consulting Services Group also provides web-based CIS deployments.”

FishTail Design Automation, Inc. announced the signing of exclusive distribution agreements with both Saros Technology Ltd. in Europe and Advinno Technologies in Southeast Asia. The company says the distributors will provide sales and support to customers in their regions.

Fujitsu Ltd. and Cadence Design Systems announced a “Premier Design Partner” agreement, under which the companies say they will create advanced SoC design environments. The worldwide Fujitsu Group and all of its design centers will have access to tens of thousands of licenses covered by the agreement. In addition, Cadence will provide personnel support to the Fujitsu Group, Fujitsu and Cadence will jointly develop methodologies that merge design and process technologies, and the companies plan to jointly expand their global business collaboration to markets such as in the U.S. and China.

Kilopass Technology, Inc. announced that Global UniChip Corp. (UniChip) has signed a corporate agreement to add Kilopass’ embedded non-volatile memory (NVM) technology, XPM, to UniChip’s IP portfolio. In addition, UniChip says it has joined Kilopass Technology’s Design Services partner program.

Jack Peng, Founder, President and CEO of Kilopass Technology, is quoted: “We are delighted to establish this partnership with UniChip. UniChip has a strong team of industry veterans with the necessary experience and capabilities customer seek in SOC design service providers. They will help accelerate the adoption of our XPM technology into designs created for high volume products.”

MatrixOne completed the acquisition on Synchronicity Software, Inc., a move first announced in June at DAC 2004. Per the Press Release: “The combination of MatrixOne and Synchronicity provides a breakthrough solution for any company that has high-value electronic content in their products.”

Mentor Graphics Corp. announced it has acquired Palmchip Corp.’s Parallel and Serial ATA IP business, which the company says “extends Mentor’s position as the leading provider of communication standards-based IP by adding Palmchip’s industry-leading ATA IP to its broad portfolio of standards-certified cores, and increases its IP offerings for the growing storage market.”

Mike Kaskowitz, General Manager of the IP Division at Mentor Graphics, is quoted in the Press Release: “When we look to augment our IP portfolio, we look to those vendors that uphold the same high standards we do. This acquisition enables us to offer our customers and Palmchip’s IP customer base a broader selection of certified cores for the storage market that provide them with a smooth transition as their design needs evolve.”

MVC Capital announced that 0-In Design Automation, Inc., one of MVC Capital’s portfolio companies, has been acquired for stock plus a multi-year earn-out by Mentor Graphics Corp.

Details per the Press Release: “As a result of the acquisition, the Fund is receiving 685,679 shares of Mentor Graphics stock, with a current market value of approximately $7.5 million. Of these shares, 603,386 shares are freely-tradable and will be valued daily by the Fund. The Fund is currently valuing these shares at $6.6 million. The balance of the shares are required to be held in escrow for a one-year period and, under the terms of the transaction, the Fund’s rights to receive all or a portion of these shares are subject to certain contingencies. While the current market value of the escrowed shares is approximately $900,000, the Fund has initially placed no value on them due to these contingencies. The terms of the acquisition also include a multi-year earn-out, based upon future revenues, under which the Fund may be entitled to receive additional cash consideration.”

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EDAC's Market Statistics Service (MSS) announced a 2-percent growth in Q2 2004 over Q2 2003 for license and maintenance, the largest EDA revenue category. Total Q2 2004 revenue, which included semiconductor IP, was $993 million, a 4-percent increase over Q2 2003. Services revenue at $70 million showed an 11-percent increase over the same quarter last year.

Computer-aided engineering generated revenue of $474 million in Q2 2004, 4 percent more than the same period in 2003. IC physical design and verification revenue was $282 million, down from $285 million in the same period last year. Revenue for PCB and multi-chip module layout was $84 million in Q2 2004, 1 percent less than in Q2 2003. Semiconductor IP revenue was up 28 percent to $84 million over Q2 2003, due in part to growing SIP participation in MSS reporting with CAST and Tensilica initiating participation in the second quarter.

North America revenues increased by four percent to $523 million, Europe revenues of $180 million were up 4 percent, and Japan at $176 million was down five percent. The rest of the world had total revenues of $115 million, up 19 percent from Q2 2003. Reporting companies employed 20,000 professionals in Q2 2004, 6 percent more than Q2 2003, a new high in employment reported by the MSS since it began tracking employment data in Q1 2000.

Nonetheless, Walden Rhines, EDAC Chairman and Chairman and CEO of Mentor Graphics, struck a solemn note in the Press Release: "Despite very modest growth in the EDA industry, there are no indications of overall strength. Growth in services versus last year is positive, but the sequential decline is not. Good growth in some areas, like analysis tools, RTL simulation, system-level design/verification, floorplanning and resolution enhancement, was offset by weakness in physical design/verification and logic synthesis. Similarly, growth in Pac Rim was offset by weakness or slow growth in other regions."

Apache Design Solutions announced that "Q3 2004 marks the company's seventh consecutive record quarter." Andrew Yang, CEO of Apache said that the Q3 results were "well balanced, with existing customers adding quantities of licenses for world-wide deployment, new first-time customers, and a number of renewals."

Magma Design Automation revised its outlook for the second fiscal quarter ended Sept. 30, 2004. Magma now expects total revenue for the quarter to be in the range of $35 million to $39 million, matching the target revenue range the company announced during its July 28 earnings call.

However, Magma alarmed some in the industry when it said it expects total orders (bookings) to be in the range of $37 million to $45 million for the second quarter, below the target range of $70 million to $90 million that the company gave as guidance during its July 28 earnings call. Magma President & COO Roy Jewell is quoted in the Press Release: "A small number of mid-size orders that were expected to close in the quarter were delayed by the customers. These customers indicated they still intend to complete their purchases with Magma, and although they could not close the transactions within the quarter-ending time frame we still expect them to be completed - none were lost to competitive pressures. We see many of our customers having a lack of visibility in their businesses and continuing to spend their R&D budgets judiciously. As a result, we see no change in our previously stated perspective that overall EDA spending will remain flat to down for the next year."

Ambric, Inc. announced completion of its Series A financing. The $10.4 million round was led by both ComVentures and OVP Venture Partners, and included all of Ambric's seed-stage investors, including Northwest Technology Ventures and private investors. The company was founded by Jay Eisenlohr, President and CEO, and Anthony Mark Jones, Vice President of Engineering and CTO.

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Cadence Design Systems, Inc. announced total revenue for the third quarter of 2004 of $302 million compared to $269 million in the same period last year. On a GAAP basis, Cadence recognized net income of $20 million, or $0.07 per share in the third quarter of 2004, compared to a net loss of $14 million, or $0.05 per share in the same period last year. Using a non-GAAP measure, earnings in the third quarter were $52 million, or $0.19 per share, on a fully diluted basis as compared to $34 million, or $0.12 per share, on a fully diluted basis, in the same period last year.

Mentor Graphics Corp. announced third quarter pro forma diluted earnings per share were $.05, on revenue of $162 million. On a GAAP basis, the company reported a loss of $.08 per share, driven lower primarily by special charges for in-process R&D associated with the acquisition of 0-In Design Automation. Revenue grew 3% over the year ago quarter, while bookings grew 2%. By geography, bookings in PacRim climbed 20%, North America was up 5%, and Europe was down 10%. Japan was flat, but continued at bookings levels nearly double the historical rate of the late 1990s. Revenue by region was 40% Americas, 30% Europe, 20% Japan, and 10% Pacific Rim.

Company Chairman and CEO Wally Rhines was quoted in the Press Release: "Although growth in the third quarter was slow, it was primarily due to the timing of major orders. Year-to-date bookings have grown over 8% and we expect an all-time record level in fourth quarter and full year bookings growth of 10%."

Nassda Corp. announced financial results for the quarter ended September 30, 2004, the fourth quarter of Nassda's fiscal 2004. Revenue for the quarter ended September 30, 2004 was $11.0 million, a 31% increase from $8.4 million for the quarter ended September 30, 2003 and was substantially unchanged from $11.0 million for the quarter ended June 30, 2004. Net income for the quarter ended September 30, 2004 was $175,000, or $0.01 per diluted share, a decrease of $148,000 from $323,000, or $0.01 per diluted share, for the quarter ended September 30, 2003 and a decrease of $891,000 from $1.1 million, or $0.04 per diluted share, for the quarter ended June 30, 2004. Total revenue for fiscal 2004 was $41.5 million, an 18% increase from $35.1 million for fiscal 2003. Net income for fiscal 2004 was $2.6 million, or $0.09 per diluted share, a decrease of $1.0 million as compared to net income for fiscal 2003 of $3.6 million, or $0.12 per diluted share.

TransEDA reported 40% growth one year after the merger with TNI-Valiosys.

X-FAB Semiconductor Foundries AG announced sales revenues increased by 27 percent to EUR 38.3 million, with an operating result of EUR 2.4 million in the third quarter. This compares to an operating loss of EUR 8.2 million in the same period of 2003. Earnings before interest and taxes (EBIT) also improved to EUR 1.3 million, following negative earnings of EUR 7.8 million in the third quarter of 2003. Net income as of September 30, 2004 was EUR 6.1 million, with EUR 0.4 million attributable to the third quarter. In the previous year, the company reported a loss of EUR 15.4 million for the first nine months and a loss of EUR 8.4 million for the third quarter. Sales revenues in the first nine months of fiscal year 2004 totaled EUR 105.3 million, up 26 percent versus the same period last year.

Denali Software Inc. announced it is a new member in the ARM Connected Community, whereby Denali will have access to resources to help developers get "ARM Powered" products to market faster.

EMA Design Automation and the Chronology Division of Forte Design Systems announced a strategic partnership. EMA says it will provide exclusive distribution and support throughout North America for Chronology's TimingDesigner timing analysis product.

Emulation and Verification Engineering (EVE) announced that Crescendo Technologies Ltd. has become EVE's exclusive distributor in China. Under terms of the distribution agreement, Crescendo Technologies will market and support EVE's products throughout China.

LSI Logic announced the formation of the RapidChip Platform ASIC Partner Program, a cooperative effort between LSI Logic and third-party providers of IP, design services and EDA tools. The 13 initial companies participating in the program include: ARM, Arrow, Denali Software, GDA Technologies, Memec, PLDApplications, Pinpoint Solutions, Synplicity, Silicon Infusion, TeraSystems, Daito Electron Co., Innotech, and Reptechnic Design.

Synfora, Inc. has named Design Automation Solutions, Inc. (DASI) as its channel partner for the South Central U.S. The companies announced that Scott Spurlin and Doug Peterson will manage the DASI team for Synfora.

Tower Semiconductor Ltd. has named QualCore Logic Inc. to be a member of the Tower Authorized Design Center (TADC) program. The program helps Tower's customers by linking Tower Semiconductor to design firms to provide hardware designers with support for the Tower fabrication flow.

True Circuits, Inc. announced it has signed Amos Technologies as an authorized sales representative in Israel.

Aprio Technologies Inc. formally announced the company, its funding, and the company's intent to play in the DFM space. Prior to the November 1, 2004 announcement, the company was in a "stealth mode." Aprio says initial products will be announced soon. Aprio was founded in January of 2003 by Clive Wu and Daniel Ho. Randy Smith joined the company in December 2003. The company has had two rounds of funding, with a total to date of $10 million. Previously, Aprio CEO & CTO Wu was Engineering Vice President at Numerical Technologies. Wu has a PhD from Stanford, and has authored 10+ patents on resolution enhancement technology (RET) and DFM. Daniel Ho is Aprio's co-founder and Vice President of Engineering and Operations. Previously, he e was a founding member of Ambit Design Systems, and also worked at both Valid Logic and Cadence Design Systems. Randy Smith is Aprio's Vice President of Sales and Marketing. Previously, he was a founding member of Tangent Systems, later acquired by Cadence. Smith also served in senior positions at TriMedia Technologies, Artisan Components, Gambit Automated Design, and Celestry Technologies.

Bluespec Inc. announced that it has secured $4.5 million of additional funding, with the round led by inside investors Atlas Venture and North Bridge Venture Partners. Bluespec says its total funding now stands at $8.5 million.

Silicon Design Systems, Inc. announced the addition of Gemini Funds as an investor, and said the company has expanded the amount of its series B investment funding to $9.2M. Gemini joins Carmel Ventures and Infinity Partners in the recently closed Series B funding led by Carmel Ventures. Gilo Ventures II led the Series A funding, and also participated in Series B. Tali Aben from Gemini is joining the Silicon Design Systems Board of Directors.

Xoomsys Inc. announced that it has secured $7 million in its first round of venture financing, which included funds from Benchmark Capital and Morgenthaler Ventures. The company also announced that Naren Gupta, Vice Chairman of Wind River Systems, and Buno Pati, Founder and CEO of Numerical Technologies have also invested in Xoomsys. Alex Balkanski from Benchmark Capital and Bob Pavey from Morgenthaler Ventures will join the Xoomsys Board of Directors. Balkanski is a General Partner at Benchmark Capital and previously headed up C-Cube and DiviCom. Pavey is a General Partner at Morgenthaler Ventures. He is past president of the National Venture Capital Association. Buno Pati will serve as Chairman of the Board.

Beach Solutions announced it has acquired VCX Software, Ltd. VCX runs the www.theVCX.com. Beach says it is committed to enhancing theVCX.com portal and supporting the numerous commercial and informational websites that utilize the VCX Gateway search engine. Terms of the agreement were not disclosed. The VCX staff, technology and IP are transferring to Beach.

LogicVision, Inc. announced that it has entered into a definitive agreement to acquire SiVerion, Inc. by issuing two million shares of its common stock and $2 million in cash at closing, plus a contingent future payment of up to $2 million. SiVerion will become a business unit of LogicVision, will retain all its employees, including its president Thomas Martis, and will continue its operations in Arizona. Gregg Adkin, a general partner of Valley Ventures, SiVerion's primary investor, will join LogicVision's board of directors. The terms have been unanimously approved by the boards of directors of both companies, and the transaction is expected to be completed in Q4 2004, pending approval by SiVerion's stockholders.

Synopsys, Inc. announced the acquisition of Cascade Semiconductor Solutions, Inc. The companies say that Cascade's digital IP complements Synopsys' PCI Express Verification IP and PHY (Physical Layer of the PCI Express protocol), and creates "a complete PCI Express IP solution." Synopsys and Cascade say that together they have PCI Express design wins at 25+ companies.

Synopsys also announced it has acquired "certain assets" and hired the engineering team of LEDA Design. LEDA Design has 80+ digital and mixed-signal IP design engineers and support personnel located in Yerevan, Armenia, who will now join the Synopsys DesignWare IP engineering team. The terms of the transaction were not disclosed.

Synopsys also announced that its Board of Directors has renewed its stock repurchase program last renewed in December 2003. Per the Press Release: "Under the renewed program, the Company may repurchase Synopsys common stock with a market value up to $500 million (not including amounts purchased to date under the program) on the open market. Purchases may be made beginning immediately and ending at such time as the authorized funds are spent or the Company discontinues the program. All purchases shall be made at prevailing prices and will be funded from available working capital. The repurchased shares may be used for ongoing stock issuances, such as for existing employee stock option and stock purchase plans and acquisitions. During fiscal 2004, Synopsys acquired a total of approximately 16.9 million shares, at an average price of approximately $25.02."

Perhaps most significantly, Synopsys announced it has signed agreements to acquire Nassda Corp. in an all-cash transaction at $7.00 per share and, subject to the closing of the acquisition, to settle all outstanding litigation by Synopsys against Nassda and certain Nassda officers, directors and employees. The aggregate purchase price will be approximately $192 million, or approximately $92 million net of Nassda's estimated cash at closing. In addition, upon closing, the Nassda officers, directors and employees who are defendants in the litigation between Synopsys and Nassda will make settlement payments to Synopsys in the aggregate amount of $61.6 million.

The definitive agreements for the acquisition have been approved by the boards of directors of both Synopsys and Nassda, as well as by a special committee of Nassda's board. The acquisition is subject to approval by the holders of a majority in interest of Nassda's outstanding common stock. Certain directors, officers and employees of Nassda who own in the aggregate approximately 60 percent of Nassda's outstanding common shares have agreed to vote in favor of the transaction. The acquisition is further subject to approval by a majority of votes cast at Nassda's upcoming special meeting of stockholders, excluding votes cast by the defendants in the litigation between Synopsys and Nassda, certain associated parties of the defendants, and Nassda's officers and directors. The acquisition is also subject to customary regulatory approvals and other closing conditions.

Rex Jackson, Vice President and General Counsel of Synopsys, is quoted in the Press Release: "This acquisition successfully resolves the litigation between our two companies and sends a strong message of Synopsys' commitment to protecting and preserving its intellectual property, By acquiring Nassda rather than continuing through the courts, Synopsys can preserve Nassda's products and continue long-term support of Nassda's customers."

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EDAC’s Market Statistics Service (MSS) announced that Q3 2004 EDA License and Maintenance revenue, the largest EDA revenue category, declined 3% over Q3 2003. Total Q3 revenue, which included semiconductor IP, was $953 million, a 2% decrease from Q3 2003. Wally Rhines, EDAC Chairman and Chairman and CEO at Mentor Graphics, is quoted in the Press Release: “Despite a weak third quarter, the EDA market has shown a positive three percent growth rate on a year-to-date basis. The weakness in Q3 was focused in North America, where all major categories were down versus Q3 2003. On a product-line basis the recent Q3 weakness was driven primarily by the IC/ASIC Physical Design categories, while a number of other key categories that have usually shown growth remained relatively flat versus a year ago.”

MSS reported that EDA’s largest tool category, Computer-Aided Engineering (CAE), generated revenue of $453 million in Q3 2004 - no change from the same period in 2003. IC Physical Design & Verification revenue at $272 million was down nine percent from $298 million in the same period last year. Revenue for Printed Circuit Board (PCB) and Multi-Chip Module (MCM) Layout totaled $81 million in Q3 2004, one percent less than in Q3 2003. Services revenue at $66 million showed a 5 percent increase over the same quarter last year. Semiconductor IP revenue rose eight percent to $81 million over third quarter of last year. This rise was in part due to growing SIP participation in MSS reporting with CAST and Tensilica initiating participation in the second quarter. North America revenues declined by nine percent to $472 million while Europe revenues of $192 million showed a four percent rise, and Japan at $183 million was also up four percent. Double-digit growth continued in the rest of the world, which showed total revenues of $107 million, up 11 percent from Q3 2003. Reporting companies employed almost 20,500 professionals in Q3 2004, four percent more than Q3 2003. This was the third consecutive quarter of new highs in employment reported by the MSS since it began tracking employment data in Q1 2000.”

Mentor Graphics announced that its fourth quarter 2004 bookings and revenues had achieved record levels, with revenues expected to exceed Thomson First Call consensus estimates of $204 million. Bookings for the fourth quarter were up about 40%, year over year. The company also grew backlog significantly, up approximately 35% from the fourth quarter of 2003. Fourth quarter special charges are expected to result in GAAP basis earnings below guidance. Earnings per share on a pro forma basis are expected to modestly exceed consensus estimates. Fourth quarter bookings performance was broad-based across all regions and product lines, and not driven by any particular large transactions. All regions performed well with bookings in North America up 15%, Europe up 50%, and Japan and the Pacific Rim both up over 100% over the fourth quarter of 2003.

Nassda Corp. announced financial results for the quarter ended December 31, 2004, the first quarter of Nassda's fiscal 2005. Revenue for the quarter ended December 31, 2004 was $11.3 million, an increase of 16% from $9.7 million for the quarter ended December 31, 2003 and an increase of 2% from $11.0 million for the quarter ended September 30, 2004. Net income for the quarter ended December 31, 2004 was $1.3 million, or $0.05 per diluted share, an increase of 135% from $572,000, or $0.02 per diluted share, for the quarter ended December 31, 2003 and an increase of $68.6 million from a net loss of $(67.3) million, or $(2.50) per diluted share, for the quarter ended September 30, 2004. Operating expenses for the first quarter of fiscal 2005 were lower than expected, primarily due to lower litigation costs. As a result, Nassda says it was able to achieve an operating margin of 14% for the quarter ended December 31, 2004.

Xilinx, Inc. announced the launch of a $100M corporate venture fund, that the company says will fuel industry innovation within the company’s growing “ecosystem for programmable system design.” Initially, the venture fund activity will be focused in Europe and the U.S., with an emphasis on high-speed DSP, embedded processing and high-speed connectivity. Ecosystem Venture Fund proposals are reviewed by Xilinx business development for potential investments ranging from $250K to $5M. Applicants must meet the following criteria: Demonstrated commitment to the Xilinx ecosystem from a Xilinx executive sponsor to validate and advocate for the candidate company; Early customer validation of the proposed technology; Well-managed companies with sound business fundamentals and good potential for growth and profitability; Interest and/or engagement by other investors.

Synopsys, Inc. announced the Federal Trade Commission (FTC) has requested additional information and documentary material in connection with its review of Synopsys’ proposed acquisition of Nassda Corp. Synopsys says it will promptly respond to the FTC request. The FTC request extends the waiting period under the Hart-Scott-Rodino Antitrust Improvements Act of 1976. Synopsys announced on December 1, 2004, that Synopsys and Nassda had entered into a merger agreement providing for the acquisition of Nassda by Synopsys in an all cash transaction at $7.00 per share and, subject to the closing of the acquisition, to settle all outstanding litigation by Synopsys against Nassda and certain Nassda officers, directors and employees.

Nassda Corp. also announced that the FTC has requested additional information and documentary material in connection with its review of the proposed merger between Nassda and a subsidiary of Synopsys.

Cadence Design Systems, Inc. announced that it has signed a definitive agreement to acquire Verisity Ltd. Under the terms of the agreement, Cadence will acquire Verisity in an all-cash transaction. Upon closing of the acquisition, which is subject to customary shareholder and government approvals, Verisity stockholders will receive $12 in cash in exchange for each outstanding share of Verisity stock. Upon completion of the acquisition, Moshe Gavrielov, CEO of Verisity, will join the Cadence executive management team, and Yoav Hollander, founder and CTO, will, according to the Press Release, “play an integral role in setting Cadence’s verification technology direction.”

Mike Fister, President and CEO, Cadence Design Systems, is quoted: “The global electronics industry is under unprecedented pressure to develop and bring to market innovative products as quickly as possible. Our acquisition of this highly innovative team and successful business is consistent with Cadence’s focus on enabling the world’s leading electronics companies to address the demand for increasingly complex systems.”

Moshe Gavrielov is also quoted: “Customers are demanding solutions that automate the entire verification process and make it more predictable from planning to closure. This requires the integration of our VPA solution with a unified verification infrastructure. The combination of the two companies will greatly accelerate the delivery of these integrated solutions.”

Jasper Design Automation announced that it has acquired Safelogic. The terms of the transaction were not disclosed. The companies say the acquisition “brings together technology leaders in complementary areas within the formal verification market, creating a combined company with the EDA industry’s strongest solution for verification and debugging of block-level designs using assertions and high-level requirements. Safelogic brings to Jasper one of the world’s fastest formal proof engines … [and] the merged company has one of the formal industry’s strongest engineering teams, with development sites in Mountain View, Calif., Berkeley, Calif., and Göteborg, Sweden.”

Pär-Jörgen Pärson has joined the Jasper board of directors, and Jonas Risberg, a Safelogic board member, will participate on Jasper’s board as a board observer. All Safelogic employees became employees of Jasper Design Automation in December 2004, when the transaction closed. Safelogic was originally founded in 1999.

Harry Foster, chairman of the IEEE-1850 PSL Committee and chief methodologist at Jasper Design Automation, is quoted in the Press Release: “Safelogic is widely recognized as having made a major contribution to the development of the PSL standard, particularly as it relates to formal proof. In contrast to the many rudimentary and incomplete implementations out there, Safelogic has the most comprehensive support of PSL in the formal industry. This, combined with Jasper’s support of Verilog-based requirements and commitment to SystemVerilog Assertions, puts the combined company at the forefront of assertion language support.”

Kathryn President and CEO made these comments by phone: “I’m very excited about this merger, although it took a while to close. Jasper first got wind of the technology and technologists at Safelogic back in middle of last year when some formal tools developed by Safelogic outperformed the competition at a specific event. That was the tip of the iceberg. This is the team that has developed what is unquestionably the best of class in the world, best for ease of use and ease of adoption for formal verification. Now we’re finding incredible, complementary chemistry, and good camaraderie between the teams.”

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AMD, Analog Devices, Freescale, and IBM announced that they are the first companies to publish certified scores for processors tested against the new DENbench suite, EEMBC’s new Digital Entertainment benchmarks. The first processors to be evaluated under the new benchmarks are the AMD Geode NX1500, the Analog Devices ADSP-BF533, the Freescale MPC7447A, and the IBM 750GX.

EEMBC says the DENbench suite has 65+ benchmark tests that allow developers of set-top boxes, PDAs, mobile phones, and in-car entertainment systems to evaluate the performance

Applied Wave Research, Inc. (AWR) and Auriga Measurement Systems, LLC announced an OEM agreement aimed at providing new modeling and extraction solutions. Under the terms of the agreement, Auriga will embed AWR’s Microwave Office design software into the company’s upcoming measurement and model extraction test system.

Giga Scale Integration Corp. announced that it has launched a new website, ChipEstimate.com, that provides free access to the company's InCyte chip estimation tool. After registering, visitors can download a free copy for immediate use. In addition, upgrade subscriptions providing access to additional IP vendor and foundry data are available at the ChipEstimate.com website.

IMEC announced that Samsung Electronics Co. LTD. has become the first strategic partner within IMEC's M4 (Multi-Mode Multi-Media) research program, which IMEC says focuses on the mobile terminal for the future ubiquitous network era. Under this agreement, Samsung and IMEC will develop technologies for future portable communication products. IMEC also has relationships with Freescale, Infineon and Xilinx within the M4 technology programs.

MatrixOne announced the MatrixOne Materials Compliance Central business process application, which the company says is designed to help companies to comply with new environmental regulations in affect for the product development process.

SilTerra announced it will provide Virage Logic Corp.’s IPrima Foundation Platform to Its 130-nanometer process customers IPrima Foundation has memory, logic and I/Os optimized to SilTerra’s 130-nanometer process. Under the terms of the agreement, SilTerra customers can download design kits with the IPrima Foundation IP Platform from the "Members" section of Virage Logic’s website.

Synopsys, Inc. announced a service to allow users of Verisity's Specman Elite testbench product to migrate to Synopsys' VCS RTL verification tool. The company says the Native Testbench (NTB) migration service converts Specman Elite verification environments to VCS environments and includes tool, language and methodology training.

Virage Logic announced it is extending its distribution model from a customer-paid licensing and royalty-bearing model to include a new "Foundry Pays" option in which foundries can license Virage Logic IP directly and provide it to their customers.

Actel Corp. announced net revenues of $40.3 million for the fourth quarter of 2004, down 1 percent from the fourth quarter of 2003 and up 2 percent from the third quarter of 2004. For the full fiscal year, net revenues were $165.5 million, up 10 percent from fiscal 2003. Pro-forma net income, which excludes acquisition-related amortization and other non-recurring items, was $0.6 million for the fourth quarter of 2004 compared with $3.0 million for the fourth quarter of 2003 and $1.2 million for the third quarter of 2004.

Ansoft Corp. announced financial results for its third quarter of fiscal 2005 ended January 31, 2005. Net income for the third quarter was $3.0 million, or $0.23 per diluted share, representing a 115% increase when compared to net income of $1.4 million, or $0.11 per diluted share in the previous fiscal year's third quarter. On a GAAP basis, net income for the third quarter was $2.8 million, or $0.21 per diluted share, compared to GAAP net income of $941,000, or $0.07 per diluted share in the previous fiscal year's third quarter. Revenue for the third quarter totaled $17.4 million, an increase of 24% compared to $14 million reported in the previous fiscal year's third quarter.

Apache Design Solutions announced that the company’s sales in creased 3X in 2004 compared to the previous year, Q4 2004 is the company’s eighth consecutive record quarter. In addition, the company is relocating its headquarters to a new facility in Mountain View, CA.

Cadence Design Systems reported fourth quarter revenues were $343 million, compared to $311 million for the same period last year. Full year revenues totaled $1.20 billion, an increase of 7 percent over 2003 total revenues of $1.12 billion. On a GAAP basis, Cadence recognized net income of $60 million, or $0.20 per share, in the fourth quarter of 2004, compared to net income of $15 million, or $0.05 per share, in the same period last year. On a full year basis, Cadence net income for 2004 was $74 million, or $0.25 per share, compared to a net loss of $18 million and a diluted net loss per share of ($0.07) for the year 2003.

Mentor Graphics announced revenues of $214.9 million for the fourth quarter of 2004. Diluted earnings per share for the quarter on a pro forma basis were $.39, and on a GAAP basis were $.20. Book-to-bill reached its highest level since 1996 and backlog reached a level not seen since year 2000. Bookings rose over 35% for the quarter and 20% for the year.

Synopsys, Inc. reported results for the first quarter ended January 31, 2005. For the quarter, Synopsys reported revenue of $241.3 million, a 15% decrease compared to revenue of $285.3 million for the first quarter of fiscal 2004, but in line with the Company's targets. The decrease was expected, and is due primarily to a lower percentage of up-front license revenue, driven by the shift in the fourth quarter of fiscal 2004 in Synopsys' license mix away from software licenses on which revenue is recognized when the product is shipped toward licenses on which revenue is recognized over the term of the license.

Synplicity announced financial results for the fiscal quarter and year ended December 31, 2004. Revenue for the quarter ended December 31, 2004 was $15.1 million, a 14 percent increase from revenue of $13.2 million for the quarter ended December 31, 2003 and a 7 percent sequential increase from revenue of $14.1 million for the quarter ended September 30, 2004.

Taiwan Semiconductor Manufacturing Company (TSMC) announced revenue and net income for the quarter ended December 31, 2004. Fourth quarter revenue reached NT$63.87 billion, while net income and fully diluted earnings per share came to NT$22.18 billion and NT$0.96 per share (US$0.15 per ADS unit), respectively. For the full year of 2004, TSMC's revenue set a new record, NT$255.99 billion, 26.8% higher than in year 2003. Net income for the entire year grew 95.3% to NT$92.32 billion, also a new record. In US dollar terms, revenue for 2004 was US$7.65 billion, an increase of 30.3% while net income grew to US$2.76 billion, an increase of 100%.

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