Blogs  | Buyers' Guide  | Issues  | Resource Catalog  | Subscribe  | Advertise  | Career Center  | eNewsletters  | iDesign  | About Us
Affiliate Sponsors:    
        IEC               
FREE ISSUE Download!
Resource Center
Resource Catalog
Find Consultants
Find a Job
Departments
From the Editor
News
Head2Head
Dot.Org
Viewpoint
Vendor Reports
FPGA Synthesis Support Expands

Sales and Support Announced for IP Library

Core Used in Breakthrough DSP Architecture

Complete Hardware-Proven Solution for PCI Express-Based SoCs

Keynote Address and Panels for DesignCon 2007

First OpenGL ES 2.0 Silicon Shown at CES 2007

TeamEDA launches ADVANCED VERIFICATION SYSTEM

Wireless Applications Take Center Stage

Providing Solutions for Your Design Problems

Accelerating Algorithms in Low Power, High Performance Architectures

When You Have a Hammer, Everything�s a Nail!

Magma Design Automation introduces Cobra:

Timely Deployment of Silicon Is Meaningless Unless ...

MATLAB/SIMULINK Interface in Active-HDL 6.2
Product Showcase
EdXact: Bringing Innovation Into The Verification Flow

InCyte

Semiconductor Technologies > IP--Core - PLL and DLL Hard Macros

Platform Express

SafeNet Security IP

MOSAID Virtual Silicon Semiconductor IP

Carbon Design Systems' SOC-VSPT

True Circuits Product Showcase

InCyte from Giga scale IC

Accelerate Forward with Poseidon Systems

PCI Express Integration and Verification

Celoxica

Programmable Digital Frequency Synthesizer (DFS) PLL

TimingDesigner

Synplicity

NEW from Summit Design

Tuner & Builder

Develop DFM Tools. Better. Faster.

cLGA® socket

On-Demand Web Seminar Sponsored by Avnet Electronics Marketing

Featured Jobs
Systems Architects and ASIC Engineers

Senior ASIC Design Engineers
Editorial Center
Editorial Calendar
Contact John
Advertising Opportunities
Circulation
Rates
Ad Specs (pdf)

Dear ASIC Designer,

Your feedback will provide eASIC and Flextronics with valuable guidance for our co-development of Structured ASIC arrays. In return, you will have access to our technical documentation.

The log-in name and password will be emailed to those who fill out the required design information.

Additionally, you will enter our drawing for iPod !

Apple iPod


All fields in red are required.
Do not register more than once.
Your
Design
Design start date
Shipping target date
Number of gates

Number of I/Os

Number of RAM blocks
Total number of RAM bits


Number of clock domains
Required IPs

(Hold CTRL to select multiple)
Other IPs
Required I/Os

(Hold CTRL to select multiple)
Other I/Os
Production units/expected
volume (roughly)





End-product industry segment












Would you be interested to get via email product updates and
news announcements from eASIC ?

Any other comments/insights you would like to share regarding
your current or future needs for Structured ASIC products:

Contact information:

First Name:
Last Name:
Title:
Company:
Phone:
Fax:
Mobile:
Street Address:
Town:
State: (US only)
Zip Code:
Country:
E-mail:*
*Please fill out your workplace email address.
Download password won’t be sent to commercial
ISP address such as Yahoo, Hotmail, etc.
Website:
Would you like to subscribe to ChipDesign Magazine?
Yes   No

Please do not click the submit button more than once.

 
Sign up for Email Newsletter
Celoxica MAY
Virtual Silicon Apr
Innovative Semi JUNE/JULY
KLA-Tencor Apr 05
EVE Feb 2005
True Circuits June 2005
GigaScale 125 Feb 05