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In this Issue:

1. Viewpoint: The Evolving Semiconductor Infrastructure vs. The Inconvenient Truth
2. Magma Licenses IBM's Physical Design Software
3. Javelin Introduces System Physical Prototyping
4. Blue Pearl Software Introduces Timing Constraint Generation Software
5. Agilent Technologies Ships Electromagnetic Design System
6. CEVA and ASTRI Announce the CEVA-TeakLite DSP
7. Texas Instruments Reinforces 20-year Commitment to India
8. In-Depth Coverage Links
• » Quality of Results is Everything for FPGA Designs—Or Is It?
• » The AVAD Search for Perfection in Analog and Mixed-signal Design.
9. Featured Book
• » DNA Computing: New Computing Paradigms
10. Happenings -- Conferences

Sponsors:

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1. Viewpoint - Exclusive

The Evolving Semiconductor Infrastructure vs. The Inconvenient Truth

Jacques Benkoski, entrepreneur in residence, US Venture Partners (http://www.usvp.com/)

By now, most people have heard of Al Gore's movie on global warming and the impending crisis it represents for our planet. That is a crisis if there ever was one, and Gore's clear attempt to raise awareness—and his call to action—is timely and remarkable in its message's effectiveness.

Similarly, at every node transition in the semiconductor industry, we are finding dramatic articles and presentations throughout the ecosystem about impending crises and why the industry will come to an end because of a new parameter or physical or economical evolution. No need to remind everyone about the deep-submicron barrier, the productivity gap, or subwavelength lithography wall; intra-die variability, thermal density, insane mask costs, the shift to software, the list goes on. The world is coming to an end again unless the semiconductor industry adopts the new technologies that have been developed to address those issues just as they become serious. Full Story »

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2. News

Magma Licenses IBM's Physical Design Software

Magma Design Automation Inc. announced it has licensed IBM technology for physical synthesis and routing that was developed through IBM's long-term relationship with the Research Institute of Discrete Mathematics at the University of Bonn in Germany. This agreement begins an ongoing relationship in physical synthesis and routing addressing deep-submicron design, including lithography-aware routing, among Magma, IBM, and the University of Bonn. Magma intends to leverage the IBM technology to integrate novel algorithms into Magma products. These include analytical formulations for routing—as opposed to the heuristic approaches used by most EDA companies today—resulting in reduced via count and significant yield improvement compared to existing EDA tools.
Magma Design Automation Inc. » http://www.magma-da.com/

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3. News

Javelin Introduces System Physical Prototyping

Startup Javelin Design Automation has emerged from stealth mode to announce its System Physical Prototyping (SPP) technology, which enables the evaluation of early architecture tradeoffs and logic feasibility based on physical effects. Javelin's SPP-powered product, to be announced later this summer, brings architectural, logic, and physical domains together in a single environment, letting engineering teams evaluate physical design feasibility from the earliest architectural stage in the ASIC or SOC development cycle. Previously, engineers relied on statistical estimation methods, such as spreadsheets or implementation tools never intended for the purpose of doing SPP, which can lack accuracy and fail to optimize the design. The SPP technology eliminates the time associated with long, serial, iterative implementation flow cycles.
Javelin Design Automation » http://javelin-da.com/main/

4. News

Blue Pearl Software Introduces Timing Constraint Generation Software

Blue Pearl Software Inc. has launched its new Cobalt Timing Constraint Generation software, which is used in the design of complex ICs and intellectual property (IP) blocks. Cobalt reduces the time required to achieve timing closure and improves the quality of results by automatically generating false and multicycle path timing constraints. Cobalt quickly identifies these paths in full-chip designs and chip modules specified at the register-transfer-level in synthesizable Verilog. It then automatically generates timing constraints in the Synopsys Design Constraint format. By generating all of the timing-exception constraints at the functional RTL level, Cobalt eliminates optimization of paths that make no contribution to design performance. In addition, it can eliminate many weeks of error-prone manual effort, improve the QoR, and lower the design risks.
Blue Pearl Software Inc. » http://www.bluepearlsoftware.com/

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5. News

Agilent Technologies Ships Electromagnetic Design System

Agilent Technologies Inc. has announced the availability of its Electromagnetic Design System (EMDS) for high-frequency RF and microwave circuit designers. EMDS makes full 3D electromagnetic simulation accessible to high-frequency designers everywhere. EMDS allows analysis and visualization of EM effects that provide insight into the performance of high-frequency RF circuit designs, such as component-level bond wires, connectors, packages, machined parts, and antennas. Designers use EMDS to make informed decisions and adjustments to designs before physical prototyping begins, reducing or eliminating design iterations and saving months in a typical product-development cycle. The first release of EMDS provides basic design-flow integration with Agilent's Advanced Design System (ADS), letting users bring layout designs from ADS into EMDS for full 3D analysis.
Agilent Technologies » http://www.agilent.com/

6. International News

CEVA and ASTRI Announce the CEVA-TeakLite DSP

CEVA Inc., licensor of digital signal processor (DSP) cores, multimedia, and storage platforms to the semiconductor industry, and Hong Kong Applied Science and Technology Research Institute Company Limited (ASTRI) have jointly announced the CEVA-TeakLite DSP and associated multimedia software. Chosen by ASTRI's IC Designs Group, it will be developed into a fully integrated, low-power audio SoC platform solution. CEVA-TeakLite's unique features combine optimal performance and complete audio and imaging codec software and is the key factor for ASTRI's decision to license the DSP. Using a single source for both the DSP and the software, the platform offers ASTRI the benefit of a highly optimized system that delivers power and performance advantages as well as ease-of-integration.
CEVA Inc. » http://www.ceva-dsp.com/
ASTRI » http://www.astri.org/

7. International News

Texas Instruments Reinforces 20-year Commitment to India

At a recent meeting with press hosted by Thiru Dayanidhi Maran, the Honorable Minister of Communications & IT for India, Texas Instruments Inc. outlined how continued support of open technology standards will let India reach its goal of 500 million mobile phone subscribers by 2010. Gilles Delfassy, senior vice president of TI's Wireless Terminals Business Unit, also announced that TI is increasing its wireless design presence in India with a new research and development center in Chennai. TI's history in India began with a research and development center in Bangalore more than 20 years ago and has now expanded with the new R&D center in Chennai dedicated to a platform of technologies that will span across TI's product portfolio.
Texas Instruments » http://www.ti.com/

Intel is hiring! Take a look here for more details....

8. In-Depth Coverage Links

For FPGAs, Quality of Results or QoR—most often meaning the maximum frequency, or fmax, at which a given design runs in a specific FPGA—is probably the most used and abused term when it comes to selecting either an FPGA or FPGA design tools. To learn more, read Juergen Jaeger's "Quality of Results is Everything for FPGA Designs—Or Is It?"

Chip Design Editorial Feature >> http://www.chipdesignmag.com/display.php?articleId=421&issueId=0

What analog/mixed-signal designers need is a suite of tools that work with all industry-standard simulators, simulation file formats, and simulation environments to provide complete analysis, verification and debugging (AVAD). To learn more, read Wu-Yi Chin's "The AVAD Search for Perfection in Analog and Mixed-signal Design."

iDesign Editorial Feature >> http://www.chipdesignmag.com/display.php?articleId=478

9. Featured Book

EDA for IC Implementation, Circuit Design, and Process Technology
edited by Luciano Lavagno, Louis Scheffer, and Grant Martin
ISBN: 0849379245
Publisher: CRC Press

CRC Press presents a comprehensive overview of the design automation algorithms, tools, and methodologies used to design integrated circuits. The Electronic Design Automation for Integrated Circuits Handbook is available in two volumes. The second volume, EDA for IC Implementation, Circuit Design, and Process Technology, thoroughly examines real-time logic to GDSII (a file format used to transfer data of semiconductor physical layout), analog/mixed signal design, physical verification, and technology CAD (TCAD). Chapters contributed by leading experts authoritatively discuss design for manufacturability at the nanoscale, power supply network design and analysis, design modeling, and more.
CRC Press » http://www.crcpress.com/

10. Happenings -- Conferences

Flash Memory Summit
Wyndham, San Jose, CA
August 8-10, 2006
http://www.flashmemorysummit.com/

IEEE Custom Integrated Circuits Conference
Doubletree Hotel, San Jose, CA
September 10-13, 2006
http://www.ieee-cicc.org/

IEEE International SoC Conference
Omni Hotel, Austin TX
September 24-27, 2006
http://www.ieee-socc.org/

GSPx: The International Signal Processing Conference and Expo
Santa Clara Convention Center, Santa Clara, CA
October 30 - November 2, 2006
http://www.gspx.com/modules.php?name=tv2mobile-fall

CSS 2006
San Francisco, CA
November 20-22, 2006
http://www.iasted.org/conferences/2006/sanfrancisco/css.htm

IEEE International Electron Devices Meeting (IEDM)
Hilton Towers, San Francisco, CA
December 11-13, 2006
http://www.his.com/~iedm/

CHIP DESIGNER e-NEWSLETTER CONTACTS

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Editorial Director: John Blyler, jblyler@extensionmedia.com

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