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In this Issue:
New White Paper featured on Chip Design:Evolving the Coverage-driven Verification Flow
TCI PLLs and DDR DLLs are high quality, low jitter, silicon proven hard macros. They are available in TSMC, UMC, GlobalFoundries and Common Platform processes from 180nm to 40nm.
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1. Editor’s Note
In much of the world May flowers are taking a backseat to hail, snow, floods, hardship, disasters and uncertainty. Spring is a time to look forward, and also a time to look out for each other. That is why this issue includes a look in Community News at how the EDA family tries to help its own. As an industry watcher I like to highlight such efforts from time to time and to note that along with competition comes common ties and fellowship. We’re each trying to succeed in the present, but we are all building the future.
Back in the Very Near Future (which begins as soon as you scroll downwards), Mark Waller of Pulsic Ltd. explains what designers had better begin considering now if they want their products to enjoy any present in Advanced Process Nodes Demand Next-Generation Shape-Based Routing. Then we delve into our usual news abstracts and In Depth features, including programming GPUs and verifying tricky software/hardware configurations. We also look forward to next month’s DAC and list some of the pioneers of the trade that will be honored.
To see our additional newsletters please visit: www.chipdesignmag.com/enewsletters/
Gold Sponsor: Eve
EVE - HW/SW CO-VERIFICATION WORLDWIDE LEADER
For hardware verification engineers and embedded software developers, EVE’s ZeBu platforms are used to debug SOC hardware, accelerate embedded software development ahead of silicon availability, and ultimately shorten time to tapeout and improve design quality, while avoiding the drawbacks of traditional acceleration/emulation/FPGA prototyping systems.
By Mark Waller, VP of R&D, Pulsic Ltd.
The days of manual layout by custom designers are numbered. With TSMC’s recent 20 nm announcement, we can see that the move to advanced nodes continues at a rapidly growing pace. The industry has learned from the 65 nm and 45nm experience that process rules for advanced nodes have reached a degree of complexity that is too much too comprehend efficiently through manual design. The time has arrived for shape-based routing tools that are as leading-edge as the processes.
Custom design has been going on as long as chip design, generally using some combination of manual and simplistic shape-based routing solutions. This was sufficient because the size of the designs were manageable enough that an engineer could meet process rules by visualizing and implementing a design relatively easily primarily using his or her own skills and expertise. There is still a reluctance on the part of many designers to adopt automation because many feel that they can do it better with hand-crafting, which may sometimes be true for a relatively few transistors but does not hold for the new, highly complex devices that are becoming the norm in the IC industry. The increase in complexity of the design and process rules means that it is becoming impossible to handle the complexity without automation, and even if complete hand-crafting were possible, shrinking product schedules don’t allow time for it
Full Story >> http://www.chipdesignmag.com/display.php?articleId=4138
Cadence Design Systems, Inc. has lain out its new vision for the semiconductor industry, in its EDA360 plans. The company calls on the EDA communities to address what is calls a growing "profitability gap" that threatens the vitality of the electronics industry. They see systems and semiconductor companies are undergoing a disruptive transformation so profound that even the best-known companies will be impacted. The EDA industry now stands at a crossroads where it must change in order to continue as a successful, independent market. Without this change, EDA will struggle to solve the increasingly complex problems customers are facing now and in the future.To download a full copy of the EDA360 vision paper visit http://www.eda360.com
Cadence >> www.cadence.com
Silver Sponsor: Mixel
Mixel is a leading provider of mixed-signal IP cores to the semiconductor and electronics industries. Mixel’s mixed-signal IP portfolio includes high-performance PHYs (D-PHY™ & M-PHYSM), SerDes, Transceivers, PLLs, and DLLs, which are used in mobile applications, such as MIPI®, MDDI, networking, and storage.
Portable designers crave higher efficiency in smaller and thinner form factors. To meet this need, Fairchild Semiconductor offers a portfolio of high performance MicroFET MOSFETs packaged in an ultra-compact and thin footprint (1.6mm x 1.6mm x 0.55mm). This portfolio contains a number of commonly used topology choices, including, single P-Channel and Schottky diode combo, single N-Channel and Schottky diode combo, dual P-Channel, dual N-Channel, complementary pair, single N-Channel and single P-Channel. They are designed with advanced-performance PowerTrench MOSFET process technology that yields exceptionally low values for RDS (ON), total gate charge (QG) and Miller Charge (QGD). Their advanced packaging delivers excellent power dissipation and conduction loss characteristics compared to conventional MOSFET packaging.
Fairchild Semiconductor >> www.fairchildsemi.com
Bronze Sponsor: DAC
47th Design Automation Conference - Mark Your Calendar!
DAC - June 13-18 - Anaheim, CA. The largest electronic design and design automation event! 190+ EDA, IP, and Design Services exhibitors, 200+ papers, panels, tutorials, User Track sessions. Exciting Keynotes, Management Day, and the new Embedded/SOC Enablement Day. Check out 20 new workshops and colocated events. ACM & IEEE members save 25%!
Forte Design Systems launched its Cynthesizer Ultra high-level SystemC synthesis software, which is tightly integrated with its CellMath product family. The company’s technology and patented intellectual property (IP) offers improved quality of results by creating better datapath components. The product uses CellMath Designer as an embedded datapath optimization capability to create datapath components as needed for use in the high-level synthesis process. Together they perform automated design-space exploration that will search for the best set of components for each individual design. The software improves power consumption and timing, and reduces area by up to 40% compared to previous versions.The company will demonstrate these products in Booth #750 at the 47th Design Automation Conference (DAC) June 14-16 at the Anaheim Convention Center in Anaheim, Calif.
Forte Design Systems >> www.ForteDS.com
Designers are experiencing growing manufacturing closure problems in advanced ICs, such as mismatches between SVRF-based design rules and inaccurate or outdated place and route models, leading to rude surprises late in the design cycle. Now Mentor Graphics Corporation has introduced a new Calibre InRoute design and verification platform. This product enables designers to natively invoke Calibre tools within the Olympus-SoC place and route system to achieve true manufacturing closure during physical design. It automatically detects and fixes DRC violations and performs design for manufacturing (DFM) enhancements while optimizing for area, timing, power and signal integrity. Together the platforms improve design quality, eliminate late-stage surprises, and significantly reduce time to closure.
Mentor Graphics Corporation >> www.mentor.com/
The Portland Group, a subsidiary of STMicroelectronics, announced that its entire line of PGI Accelerator compiler products, including its new PGI 10.4 release, now support the latest NVIDIA graphics processing units (GPU) based on the Fermi architecture. The NVIDIA Tesla 20-series supports many new features for the HPC space as well as support for version 3.0 of the CUDA toolkit. These compilers provide full support for CUDA Fortran and add support for allocatable device arrays within Fortran modules along with several API enhancements. CUDA Fortran is an extended version of the Fortran 2003 programming language that gives software developers direct control over all aspects of GPU programming. The new complier release also enhances support for the PGI Accelerator directives-based programming model on Fermi platforms.
The Portland Group >> www.pgroup.com/
Tanner EDA released version 15 of the company’s HiPer Silicon full-flow design suite, giving designers a complete analog design flow from schematic capture, circuit simulation, and waveform probing to physical layout and verification. New features and functionality include a redesigned waveform editor, a new database for storage and management of simulation data, and HiPer DevGen for device and structure generation for layout productivity. This optional add-on focuses on silicon quality and yield to generate production-ready devices. By accelerating the most time-consuming aspects of the layout process, this new tool substantially reduces the amount of time required for analog layout while improving quality and design consistency. Integrated device/structure logic ensures a consistent and high quality approach to the layout of complex analog structures across design engineers, design teams, and engineering sites.
Tanner EDA >> www.tannereda.com/
People in the EDA industry are getting together to help Erach Desai, a longtime EDA watcher, and his family. His 16-year old daughter, Jacqueline, was diagnosed with stage-four bone cancer. The family is asking for “heart-felt prayers, benevolent wishes, positive energy, and good karma to help Jacqui on the odyssey of her life.”
Friends are organizing a fundraiser at EVE in San Jose on May 27th to help the family meet expenses. Magma's vp of product marketing Bob Smith will be pouring wine from his winery Jazz Cellars. And, Magma will match dollar-for-dollar the highest contribution to The Desai Family Fundraiser made by any of the other EDA vendors up to a maximum of $50,000. “It is our hope that this will encourage the other vendors to participate and that we can collectively raise a large total contribution for the family,” said Rajeev Madhavan, Magma’s CEO.Details are at http://fundraiserforthedesaifamily.org/
The IEEE Council on Electronic Design Automation (CEDA) will present four achievement awards during the opening session of the 47th Design Automation Conference (DAC) Tuesday, June 15, at the Anaheim Convention Center in Anaheim, Calif.
The first IEEE CEDA Distinguished Service Award will be given to Professor Giovanni de Micheli, director of the Integrated Systems Centre at Ecole Polytechnique Federale de Lausanne (EPFL), Alfred E. Dunlop of Crossbow Consulting and Dick Smith, now retired. The three are being recognized for their efforts to create CEDA.
This year’s A. Richard Newton Technical Impact Award, awarded jointly by CEDA and the ACM Special Interest Group on Design Automation (SigDA), will be given to Dr. Randal E. Bryant of Carnegie Mellon University for developing Reduced Ordered Binary Decision Diagrams.
Dr. Bryant will be given the Phil Kaufman Award, presented by CEDA and the Electronic Design Automation Consortium, during the session.
Finally, CEDA will recognize the elevation of Professor Andrew B. Kahng from the University of California at San Diego to IEEE Fellow. He will be honored for his contributions to the design for manufacturability of integrated circuits and the technology roadmap of semiconductors.
For more details, visit: www.c-eda.org.
In this article Brian Caslis explains that to effectively debug a complex hardware/software solution, a designer needs to combine both processor and hardware debug techniques. For example, FPGAs allow designers to combine processor debug with an embedded logic analyzer for both hardware debug and as a bus analyzer.
Pity the tasks of the hardware verification engineer. He or she needs to see the processor execution state fully time-correlated with the hardware waveforms. The complete set of processor registers and the register and memory values within the processor must be shown in 4 state logic that can show binary state zero and one plus states uninitialized and X. Thankfully, as Marc Bryan points out, using an embedded processor can provide the necessary level of automation to address these challenges.
2010 IEEE International Interconnect Technology Conference
Hyatt Regency San Francisco Airport Hotel, Burlingame, CA USA
June 7-9, 2010
Now seeking papers on back-end memory materials & technology.
IEEE International High Level Design Validation and Test Workshop 2010
Anaheim Convention Center (co-located with DAC 2010)
June 10-12, 2010
47th Design Automation Conference (DAC)
Anaheim, CA USA
June 13-18, 2010
5th Annual Workshop on Architectural Research Prototyping
June 19, 2010
ACM IEEE International Symposium Computer Architecture
June 19-23, 2010
SEMICON West 2010
Moscone Center, San Francisco CA USA
July 13-15, 2010
SEMICON Russia 2010
Expocenter, Moscow, Russia
July 14-16, 2010
Flash Memory Summit
Hyatt Regency, Santa Clara, CA USA
August 17 - 19, 2010
PCB West 2010
Santa Clara Convention Center, Santa Clara, CA USA
September 28 - 30, 2010
Irritated because your favorite event is missing from the list? Send detailed information and read me the Riot Act at firstname.lastname@example.org
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Editor: Jim Kobylecky, email@example.com
Editorial Director: John Blyler, firstname.lastname@example.org
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