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In this Issue:
New White Paper featured on Chip Design:Synopsys White Paper: Understanding the real cost of prototyping hardwareSponsors:
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"Why send your ASIC/FPGA designs offshore, when you can get high quality and affordable design services right here in the U.S. SiliconXpress is a fabless chip provider, with offices in Santa Clara, CA and Lubbock, Texas. We offer one-stop design, fabrication, and test/packaging services for our Mil/Aero and commercial clients."
1. Editor’s Note
Not only can blocks of IP add interfaces to budding SoCs, they can describe the balls of assumptions and biases we use to interpret (and misinterpret) our social environments. In this issue, Rob Evan of Altium makes an analogy between how we handle changing personal electronics and how we look at changing requirements in EDA. See what’s fashionable in “Keeping up with technology–it’s a relationship thing.” Then we visit Blogsphere for editor, consultant, and blogger Pallab Chatterjee’s tie between having our IP and keeping it too in “Bringing Cloud Based Document Security to Semiconductor IP.” And then wrap up the world with our regular features. Full Story >> http://www.chipdesignmag.com/kobylecky/ To see our additional newsletters please visit: www.chipdesignmag.com/enewsletters/ |
TCI PLLs and DDR DLLs are high quality, low jitter, silicon proven hard macros. They are available in TSMC, UMC, CHRT and Common Platform processes from 180nm to 40nm.
By Rob Evans, Technical Editor, Altium Limited
OK, it’s time to confess. Did you take the plunge by buying a new HD DVD player or perhaps, many years ago, a Beta video recorder? Or, wisely as it would have turned out, perhaps you held back on moving to the latest consumer technology, just to see what would eventuate. What did happen, of course, has gone down in technology folklore as classic early-adopter calamities–Beta, although technically superior, was shafted by the VHS juggernaut, and HD DVD suffered a humiliating defeat to BlueRay.
In both your private and professional life adopting new technology is inevitable and necessary, but the trick is to back the right technology horse, and do it sooner rather than later. Research, staying abreast of the latest technology, and even intuition all help to narrow these decisions. Yet eventually the choice is between taking the plunge or being left behind. We all embrace change, even if reluctantly.
Full Story >> http://www.chipdesignmag.com/display.php?articleId=3570
Mixel is a leading provider of mixed–signal IP cores to the semiconductor and electronics industries. Mixel’s mixed–signal IP portfolio includes high–performance Phys, SerDes, Transceivers, PLLs, DLLs, and analog building blocks, which are used in mobile applications, such as MIPI, MDDI, networking, and storage. For further information, contact us at
marketing@mixel.comBy Pallab Chatterjee
The semiconductor industry and other IP oriented businesses have to transmit confidential documents to both members of the company when they are in remote locations and to third parties (customers, partners and vendors). This correspondence with confidential value includes price quotes, RFP responses, roadmaps, specifications, competitive analysis, product design options, and business plans, The primary method is through the marking of the document as confidential on the document and then distributing it normally. This normal distribution includes email attachments of the actual document in standard business format (ppt, doc, xls, pdf, etc).
The difficulty with this approach, especially if you are dealing with early release information or raw information is, control of the document after distribution. Confidela has developed a web based application (in its current form free to use at http://www.confidela.com ) called Watchdox. The product is targeted for several applications including the secure handling of presentations, data and quotes/documents relating to IP and products in the semiconductor industry. The key aspects of the product are the encryption of the document, the ability to validate the recipient of the documents and restrict their ability to forward, print, copy or view the document. The view restrictions are currently in the form of expiration time for document access and a second level of security which visually masks the document on the screen with the exception of a “spotlight” window magnifier which revels portions of the screen selectively with the cursor so he content can be read but not screen or photo captured. The documents under this system can be protected with a watermark in case the print fucntion is enabled.
Full Story >> http://www.chipdesignmag.com/display.php?articleId=3571
Cadence Design Systems, Inc. announced first-silicon results on 32nm Common Platform high-k metal-gate (HKMG) technology, manufactured at IBM. Along with the Common Platform alliance, comprised of IBM, Chartered Semiconductor Manufacturing and Samsung Electronics, the company collaborated to tackle systematic and random variability in advanced node designs. The results provide a rich and expansive data set modeling the HKMG process in relation to layout rules, design rule checking and device interconnect models. In addition, they capture critical information related to device and interconnect variability, including systematic, random, within-die and die-to-die variation, as well as manufacturing effects including lithography, thermal, stress, proximity effects, and copper deposition.
Cadence >> www.cadence.com
Bronze Sponsor: Zocalo
If your project is using or considering Assertion Based Verification, you need to know about Zazz™ from Zocalo Tech.
www.zocalo-tech.comBeSang Inc. has developed a multi-layer stacked three-dimensional (3D) integrated circuit (IC) technology. This 3D IC technology enables ultra low-cost solid-state drives (SSD), semiconductor memories, image sensors, and high-performance logic products with large embedded memory blocks. It includes four single-crystalline silicon layers having 200 nm to 60 nm feature size vertical device structures which are uniquely processed at low temperatures, below 400 degree Celsius. The four single-crystalline silicon layers are formed above a silicon substrate with a metal interconnection region between them. The technology combines the control logic on the bottom substrate with the 3D memory arrays. This 3D scheme allows heat to be dissipated much more efficiently.
BeSang Inc. >> www.besang.com/
Bronze Sponsor: International Test Conference
At ITC, test and design professionals can confront the challenges the industry faces, and learn how these challenges are being addressed by the combined efforts of academia, design tool and equipment suppliers, designers, and test engineers.
http://www.itctestweek.org/Azuro, Inc. has introduced version 5 of its PowerCentric low-power clock tree synthesis (CTS) solution with extended support for complex SoC designs. Key features include a 30% reduction in CTS runtimes on designs with multiple modes and corners, enhanced clock gate optimization and clock tree buffering algorithms, comprehensive support for UPF 2.0 (IEEE 1801) power domain configuration format, ground breaking “Trial CTS” capability delivering accurate post-CTS design timing with runtimes of less than one hour per one million placeable instances, top level clock balancing through hardened sub-chips with back-annotated parasitics, and full database save with rapid restore.
Azuro >> www.azuro.com
Mentor Graphics Corporation announced the Verification Academy, a unique, highly-accessible approach to meet the educational needs of verification engineers. The goals are to provide the skills necessary to mature an organization’s advanced functional verification process capabilities. To this end, the Verification Academy provides a methodological bridge between high-level value propositions (related to advanced verification technology) and the low-level details (related to specific tool and verification language details). It features Harry Foster as the primary instructor and can be accessed around the clock at: http://verification-academy.mentor.com/. A web seminar to introduce the Verification Academy to prospective users is scheduled for August 12, 2009, 9:00 AM – 10:00 AM (PST). For more information on the seminar visit: http://www.mentor.com/products/fv/events/verification-academy-webseminar
Mentor Graphics Corporation >> www.mentor.com/
EVE has launched of ZeBu-Server, a scalable emulation system capable of handling up to one-billion application specific integrated circuit (ASIC) gates. Priced at less than a penny per gate for large configurations, it offers a high level of automation, short compile time, multi-user capabilities and greater execution speed than previous generations. Its transactor catalog eases and accelerates the installation of the run-time environment. It is suitable for all system-on-chip (SoC) verification needs across the entire development cycle, from hardware verification, hardware/software integration to embedded software validation. It can be used as a multi-user, multi-mode accelerator/emulator with a typical performance of 10 megahertz (MHz) on a 40-million gate design.
EVE >> www.eve-team.com
STMicroelectronics will partner with GLOBALFOUNDRIES to produce products based on 40nm Low Power (LP) bulk silicon technology. The 40nm LP process is ideal for the next generation of wireless applications, handheld devices, and consumer electronics, which require excellent performance and long battery life. First tape out and production is planned to start in 2010. Current production is centered at a state-of-the-art 300mm manufacturing campus in Dresden, Germany–otherwise known as Fab 1. In July 2009, GLOBALFOUNDRIES also broke ground on Fab 2, a $4.2B wafer manufacturing facility in Malta, N.Y. Once complete, Fab 2 is expected to be the most advanced semiconductor foundry in the world.
GLOBALFOUNDRIES >> www.globalfoundries.com
STMicroelectronics >> http://www.st.com/stonline/
The U.S. Department of Energy’s Argonne National Laboratory will open its gates to the community on Saturday, August 29, from 9:00 a.m. to 4:30 p.m. for a day of discovery and fun for the whole family. The event is free and open to the public. Visitors can see how Argonne, the nation’s first national laboratory, is helping to solve some of the world's toughest challenges in energy, environment and national security and learn more about science and technology. Argonne operates world-class user facilities to help advance America's scientific leadership, including one of the world’s fastest and most energy efficient supercomputers. Even if you don’t live within an easy walk of this center, there are more and more facilities that are open to visitors and tours. You just have to find them and some neighbors to take along (grin).
Information about this open house is available online at www.anl.gov/Community_and_Environment/Open_House.html and on the Argonne National Laboratory Facebook page.
With the industry relying on the productivity gains from reuse of semiconductor intellectual property in chip design, how suitable that IP really is becomes crucial. But the question of IP quality is hotly debated. There area many aspects and varying perspectives, depending on whether you are a supplier or a consumer. Fortunately, Piyush Sancheti is ready with the answers in “Streamlining IP-based Chip Design.”
Full Story » http://www.chipdesignmag.com/display.php?articleId=3208
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There are an increasing number of chips that have to use both digital and analog components to economically fill their design objectives. That leads to a growing need to understand how to best create reusable and portable analog IP. KT Moore reviews developments and promises clarity in “Creating a Methodology for Analog IP Reuse.”
Full Story » http://www.chipdesignmag.com/display.php?articleId=2997
Signal and Image Processing (SIP 2009)
Honolulu, HI
August 17–19, 2009
http://www.iasted.org/conferences/home–654.html
Euromicro Conference on Digital System Design
Patras, Greece
August 27–29, 2009
http://www.iuma.ulpgc.es/dsd09/
International Workshop on Reconfigurable and Multicore Embedded Systems (WoRMES’ 2009)
Vancouver, Canada
August 29 – 31, 2009,
http://embedded.cs.ccu.edu.tw/WoRMES2009/
(held conjunction with The IEEE/IFIP International Conference on Embedded and Ubiquitous Computing)
International Conference on Field Programmable Logic and Applications
Prague, Czech Republic
August 31 to September 2, 2009
http://fpl2009.org/index.php
SBCCI2009, Symposium on Integrated Circuits and Systems Design
Pirâmide Natal Resort and Convention, Natal, Brazil
August 31 to September 3, 2009
http://www.lasic.ufrn.br/chiponthedunes2009/sbcci/
PATMOS 2009
Delft, The Netherlands
September 9–11, 2009
http://kobalt.et.tudelft.nl/patmos09/home.general.html
22nd IEEE International SOC Conference
Wellington Park Hotel, Belfast, Northern Ireland, UK
September 9–11, 2009
http://www.ieee–socc.org/
2009 Custom Integrated Circuits Conference
DoubleTree Hotel, San Jose, CA
September 13–16, 2009
http://www.ieee–cicc.org/
Intel Developers Forum US, San Francisco
Moscone Center West, San Francisco, CA
September 22–24, 2009
http://www.intel.com/IDF/
2009 CMOS Emerging Technologies Workshop
Metropolitan Hotel, Vancouver, BC, Canada
September 23-25, 2009
http://www.cmoset.com/2009_Vancouver_Workshop.html
International Symposium on System–on–Chip 2009
Tampere, Finland
October 5–7, 2009
http://soc.cs.tut.fi/2009/index.php
IEEE Workshop on Signal Processing Systems (SiPS 2009)
Tampere Hall, Tampere, Finland
October 7–9 2009
http://www.sips09.org/
ARM Developers’ Conference 2009
Santa Clara Convention Center, Santa Clara, CA
October 21-23, 2009
http://www.rtcgroup.com/arm/2008/
International Test Conference
Austin, Texas
November 3-5, 2009
http://www.itctestweek.org/
IP-Embedded Systems Conference 2009
Grenoble, France
December 1-3, 2009
http://www.design-reuse.com/ipesc09/
2009 International Conference on Field-Programmable Technology
University of New South Wales, Sydney, Australia
December 9-11, 2009
http://fpt09.cse.unsw.edu.au/
IEEE International Conference on Electronics, Circuits, and Systems, ICECS 2009
Medina, Yasmine Hammamet, Tunisia
December 13-16, 2009
http://www.icecs2009.org/
Disappointed because your event is not on the list? Send detailed information to jkobylecky@extensionmedia.com
Editor: Jim Kobylecky, jkobylecky@extensionmedia.com
Editorial Director: John Blyler, jblyler@extensionmedia.com
Advertising/Sponsorship Opportunities: Karen Popp, kpopp@extensionmedia.com
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There’s Intellectual Property, and then there’s intellectual property. When I was growing up in the starch mill town of Argo, Illinois, there were two places I really wanted to see—the just created Disneyland, and the fabled Argonne National Laboratory which, to my imagination, had to be the “Fantasyland” of Science. Both seemed impossibly far away, on other planets really. In my imagination white-coated, bespectacled researchers mixed easily with robots, wizards, spells, spacecraft, time travelers, and dragons (though I resembled Herbie Popnecker more than Harry Potter). All were to be wondered at. All were impossible.