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1. Editor’s Note
To see our additional newsletters please visit: www.chipdesignmag.com/enewsletters/
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"TLM–2.0 in Action" Tutorial Now Online
You are invited to a free video tutorial exploring the concepts and mechanics of the OSCI transaction–level modeling standard, TLM–2.0. Presented at the 2009 Design and Verification Conference, the tutorial’s examples–based approach demonstrates how to get the most value out of using the standard.
2. Viewpoint — ExclusiveRethinking the Cell Library Design Process for Advanced Nanometer Process TechnologiesBy Henrik Pallisgaard, Nangate A/S
The end of the line for the traditional evolutionary library approach The complexity of the cell library development task has been steadily growing. Due to increasingly complex design rules and the need to support new point tools, tools chains and additional library model view formats, library design teams have been struggling to keep up with the development. Consequently, “best practices” have gradually evolved into “let’s reuse everything practices”, where as much as possible from previous library generations is reused in new libraries – including the initial transistor netlists, transistor ordering and relative transistor sizing. Even the logic configurations of legacy libraries are routinely copied – either by automated migration flows or through semi–manual efforts. Full Story >> http://www.chipdesignmag.com/display.php?articleId=3378
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Mixel is a leading provider of mixed–signal IP cores to the semiconductor and electronics industries. Mixel’s mixed–signal IP portfolio includes high–performance Phys, SerDes, Transceivers, PLLs, DLLs, and analog building blocks, which are used in mobile applications, such as MIPI, MDDI, networking, and storage. For further information, contact us at
marketing@mixel.comBy Raghavan Menon, VP of Engineering, ASIP Solutions, Virage Logic
IP cores are a critical part in any ASIC/SoC development, so designers need to efficiently locate, select, and evaluate from a variety of different IP cores. Each of these steps is critical in determining the best IP core for a target application. Let’s examine each step in more detail to understand what resources and techniques are available to make this critical IP core decision.
Step One: Locate: A Broad Search for Specific IP Cores
In order to ensure there is a large set of IP cores available to make our final decision, it is important to start with a broad search for as many options as possible. This broad search can start with something as simple as a Google search for a particular IP core. This step identifies products, but also includes press releases, partnership announcements, magazine articles, blogs, and a host of other items that are not relevant. If you are unlucky enough to search for something like a “DDR Controller,” hoping to find a Double Data Rate memory controller IP core, you will be surprised to see many hits for “Dance Dance Revolution” pad controllers.
Full Story >> http://www.chipdesignmag.com/display.php?articleId=3379
4. NewsProgram Enables System Design Interoperability Synopsys, Inc. announced its System–Level Catalyst Program to accelerate the adoption of system–level design and verification. Open to EDA vendors, IP vendors, embedded software companies and service providers, the program is designed to benefit mutual customers by advancing tool and model interoperability as well as availability of system–level models and services. Members of the System–Level Catalyst Program gain access to the company’s system–level and rapid prototyping products. Founding members include: Agilent EEsof, Altera, ARC International, Carbon Design Systems, Cebatech, ChipVision Design Systems, Cofluent Design, CoWare, CriticalBlue, Doulos, Emsys, Enterpoint, Forte Design Systems, GreenSocs, IBM, Imperas, JEDA Technologies, Jungo, Lauterbach, MCCI, NoBug, SDV Ltd., Steepest Ascent, Synfora, Target Compiler, Tensilica, VaST Systems and Xilinx. Synopsys, Inc. >> www.synopsys.com/
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Jul 26–Jul 31, 2009 San Francisco, California Moscone Center
The world’s premier EDA and semiconductor design conference and exhibition. DAC features over 60 sessions on design methodologies and EDA tool developments, plus the NEW User Track presentations. The exhibition includes leading EDA, silicon and IP providers.
www.dac.com
5. NewsInterconnect Modeling Format Launched for Advanced Process TechnologiesTaiwan Semiconductor Manufacturing Company, Ltd. unveiled iRCX, an interoperable EDA data format, for its 65 nm and 40nm technologies. The format unifies interconnect modeling data delivery, and ensures data integrity and interpretation. EDA tools which support iRCX format will be able to receive accurate interconnect modeling data from files developed and supported by the company. Interconnect related EDA applications, including place & route, RC extraction, electromigration analysis, power integrity analysis, and electromagnetic simulation are to benefit from the format. iRCX is the first of several interoperable EDA interface formats co–developed between the company and its design tool partners as part of the TSMC Open Innovation Platform (OIP). TSMC >> www.tsmc.com/
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SEMICON West is the must–attend event of the year! See the latest products and technologies for high–tech manufacturing. Meet the people moving electronics innovation. Explore developments in 3D IC design and TSV packaging. Discover opportunities in MEMS, flexible and printed electronics, solid state lighting, and nanoelectronics at the new Extreme Electronics. Find solutions to increase productivity, improve performance, and advance product development.Check out the Infinite Possibilities July 14–16, 2009, Moscone Center, San Francisco, CA.
www.semiconwest.orgSynfora, Inc. announced PICO Extreme Power, an algorithmic synthesis tool to automatically minimize power consumption at the system–level based on a variety of techniques, including automatic multi–level clock gating insertion. Researchers at Rice University demonstrated a 23.5 percent reduction in dynamic power over an identical design using a standard flow. Similarly, the Indian Institute of Science (IISc) evaluated the effectiveness of the approach using eight complex applications from video, imaging and wireless domains. The results indicate as much as 50% savings in dynamic power for executing a single task in some of the applications and as much as 30% savings while executing a large number of tasks.
Synfora >> www.synfora.com
Mentor Graphics Corporation announced the introduction of PADS 9.0. This release adds new levels of functionality, scalability and integration, enabling designers to leverage many of the company’s unique and innovative technologies for design, analysis, manufacturing and multi–disciplined collaboration. With the scalable flow users can cost–effectively design their products from standard to the industry’s most complex, highest performance, and densest PCBs. Functionality now integrated and available in the scalable flow includes the addition of manufacturing and collaboration tools, and powerful thermal, signal and power integrity analysis, as well as many core design entry and layout enhancements. The PADS flow provides maximum designer productivity and reduces time to market while implementing the most advanced PCB fabrication and IC/FPGA technologies into electronic products.
Mentor Graphics Corporation >> www.mentor.com/
LFoundry released a high performance process design kit (PDK) for A/MS electronic designs, developed using Tanner EDA’s HiPer Silicon software, for its LF150 modular 0.15 µm Low Power and RF CMOS process. This grants Tanner EDA customers access to European pure–play foundry CMOS technology. The process provides up to six levels of aluminium interconnect, a polymide passivation and I/O voltages of 1.8V, 3.3V and 5.0V. Optionally a MiM capacitor is also available. The process is based on a 0.15 µm CMOS proven technology and offers excellent versatility for ASIC designers. EDA Solutions is the exclusive European representative for Tanner EDA.
EDA Solutions Limited >> www.eda–solutions.com
austriamicrosystems and Fraunhofer Institute for Integrated Circuits (IIS) announced a cooperation agreement, where both members plan to develop a new generation of magnetic motion sensing integrated circuits, which will be based on Fraunhofer’s patented HallinOne magnetic sensor technology. They will specifically target for applications within the industrial, medical and automotive markets. The proprietary HallinOne sensor technology allows measuring of magnetic fields in horizontal and vertical dimensions, providing magnitude and direction of the magnetic field at any measured point. It can be implemented in a standard CMOS process, and can be seamlessly integrated with signal processing on a single die.
austriamicrosystems >> www.austriamicrosystems.com/
Fraunhofer Institute for Integrated Circuits IIS >> www.iis.fraunhofer.de/EN/
46th Design Automation Conference to Offer Nine Workshops
Choose from nine in–depth workshops on timely and practical topics. This year’s workshops include “DFM and the Manufacturing Interface”; “Workshop for Women in Design Automation (WWINDA)”; “New and Emerging Technologies”; “Physical Verification”; System–Level and Embedded Workshops; “Moving from Traditional to Equation–Based DRC”; and “General Interest” which addresses the needs of young faculty and others who are considering a career in academia.
“DAC workshops allow attendees to stay current in focused technology areas, to learn about new topics from world–class experts, and to network with others who share similar interests,” said Andrew B. Kahng, general chair, 46th DAC Executive Committee. “We hope that this year’s workshop lineup will provide high value to attendees and successfully continue the trend of expanding DAC beyond what can fit into the technical sessions, panel sessions and tutorials.”
The 46th DAC will be held July 26 – 31 at the Moscone Center in San Francisco. For additional information about the 46th DAC workshops, visit http://www.dac.com/events/searchevents.aspx?EventType=Workshop&confid=95.
Not that long ago full–circuit analog/radiofrequency (RF) performance simulation seemed practically impossible. Now analog fastSPICE simulators are revolutionizing analog/RF verification. Paul Estrada tells us how analog/RF design teams are using analog fastSPICE simulators to develop a new generation of devices. Greet the future in “Full–Circuit Performance Simulation Tackles Big Analog/RF Designs.”
Full Story » http://www.chipdesignmag.com/display.php?articleId=2002&issueId=26
Sometimes it’s hard to see the chain when you are wrapped up as one of the links. Keeping the whole healthy while forging new connections is one of the ways that standards groups and associations strengthen the industry. Marco Racanelli shows how one subcommittee is working to create an analog supply chain ecosystem. Sit in on some straight talk and “unmixed” signals in “GSA Mixed–Signal/RF Subcommittee Is Facilitating an Analog Ecosystem.”
Full Story » http://www.chipdesignmag.com/display.php?articleId=3051&issueId=32
International Symposium on Rapid System Prototyping
Paris, France
June 23–26, 2009
http://www.rsp–workshop.org/
IEEE International Conference on Application–specific Systems, Architectures and Processors
Radisson Hotel Boston, Boston, MA
July 7–9, 2009
http://www.asap–conference.org/
SEMICON West 2009
Moscone Center, San Francisco, CA
July 14–16, 2009
http://www.semiconwest.org/
ASQED 2009 (Asia Symposium on Quality Electronic Design)
KL, Malaysia
July 15–16, 2009
http://www.isqed–asia.org/
SAMOS IX: International Symposium on Systems, Architectures, Modeling and Simulation
Samos, Greece
July 20–23, 2009
http://samos.et.tudelft.nl/samos_ix/
IWLS 2009 (International Workshop on Logic & Synthesis)
Cadence Research Laboratories,
Berkeley, California
July 24–26, 2009
(Co–located with DAC).
http://www.iwls.org/
System Level Interconnect Prediction 2009
Moscone Center, San Francisco, CA
July 26–27, 2009
(Co–located with DAC)
http://sliponline.org/
IEEE Symposium on Application Specific Processors, SASP 2009
San Francisco, California
July 27–28, 2009
(Co–located with DAC)
http://www.sasp–conference.org/
46th Design Automation Conference (DAC)
Moscone Center
San Francisco, Calif.
July 26–31
http://www.dac.com
IEEE International Midwest Symposium on Circuits and Systems (MWSCAS 2009)
Cancún, México
August 2–5, 2009
http://www–elec.inaoep.mx/mwscas2009/
Signal and Image Processing (SIP 2009)
Honolulu, HI
August 17–19, 2009
http://www.iasted.org/conferences/home–654.html
Euromicro Conference on Digital System Design
Patras, Greece
August 27–29, 2009
http://www.iuma.ulpgc.es/dsd09/
International Workshop on Reconfigurable and Multicore Embedded Systems (WoRMES’ 2009)
Vancouver, Canada
August 29 – 31, 2009,
http://embedded.cs.ccu.edu.tw/WoRMES2009/
(held conjunction with The IEEE/IFIP International Conference on Embedded and Ubiquitous Computing)
International Conference on Field Programmable Logic and Applications
Prague, Czech Republic
August 31 to September 2, 2009
http://fpl2009.org/index.php
SBCCI2009, Symposium on Integrated Circuits and Systems Design
Pirâmide Natal Resort and Convention, Natal, Brazil
August 31 to September 3, 2009
http://www.lasic.ufrn.br/chiponthedunes2009/sbcci/
PATMOS 2009
Delft, The Netherlands
September 9–11, 2009
http://kobalt.et.tudelft.nl/patmos09/home.general.html
22nd IEEE International SOC Conference
Wellington Park Hotel, Belfast, Northern Ireland, UK
September 9–11, 2009
http://www.ieee–socc.org/
2009 Custom Integrated Circuits Conference
DoubleTree Hotel, San Jose, CA
September 13–16, 2009
http://www.ieee–cicc.org/
Intel Developers Forum US, San Francisco
Moscone Center West, San Francisco, CA
September 22–24, 2009
http://www.intel.com/IDF/
International Symposium on System–on–Chip 2009
Tampere, Finland
October 5–7, 2009
http://soc.cs.tut.fi/2009/index.php
IEEE Workshop on Signal Processing Systems (SiPS 2009)
Tampere Hall, Tampere, Finland
October 7–9 2009
http://www.sips09.org/
Editor: Jim Kobylecky, jkobylecky@extensionmedia.com
Editorial Director: John Blyler, jblyler@extensionmedia.com
Advertising/Sponsorship Opportunities: Karen Popp, kpopp@extensionmedia.com
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In this issue we feature two outstanding technical articles. In the first, Henrik Pallisgaard, co–founder of Nangate A/S, takes us inside design challenges at the nanometer level. Expect big results from tiny packages in Rethinking the Cell Library Design Process for Advanced Nanometer Process Technologies. Then Raghavan Menon, VP of Engineering at Virage Logic, picks up the design challenge with a methodology for IP selection. Rise with the best in IP Metrics Article: Selecting IP in a Complex Design Environment. Next simplify your complex world with our insightful news abstracts and regular features. But don’t forget to start planning for DAC now. We preview the workshops in our DAC Spotlight. And we convey Virage’s wish to visit them at the TSMC Open Innovation Forum.
Modern semiconductor fabrication processes for nanometer technologies, at 32nm and below, present significant challenges for chip designers, design tool vendors and physical IP providers alike. The latest sub–wavelength technologies certainly have the potential to enable implementation of IC’s with unprecedented density, speed and energy efficiency, but in order to effectively exploit these capabilities the fundamental building blocks upon which all physical synthesis flows are based – namely the standard cell libraries – deserve renewed and careful attention. Henrik’s article illustrates a new methodology that deploys more automation and intelligence into the design process.