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Is IP re–use or chip estimation in your future? Explore all the IP you need from over 200 suppliers and estimate your next chip’s size and power with IP of interest. Find it free, all in one place. We have the answers you need. FREE at ChipEstimate.com!
1. Editor’s Note
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TCI PLLs and DDR DLLs are high quality, low jitter, silicon proven hard macros. They are available in TSMC, UMC, CHRT and Common Platform processes from 180nm to 40nm.
2. Viewpoint — ExclusivePhysical Synthesis is Broken—Why Clocks Are Crippling Migration to 45nm and BelowBy Marc Swinnen, Director of Product Marketing, Azuro, Inc.
The clock timing gap can only be understood if one re–examines some of the most fundamental assumptions underlying our IC design methodology – the role of the clock in sequential design. Full Story >> http://www.chipdesignmag.com/display.php?articleId=3273
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Mixel is a leading provider of mixed–signal IP cores to the semiconductor and electronics industries. Mixel’s mixed–signal IP portfolio includes high–performance Phys, SerDes, Transceivers, PLLs, DLLs, and analog building blocks, which are used in mobile applications, such as MIPI, MDDI, networking, and storage. For further information, contact us at
marketing@mixel.comBy Matt Gutierrez, Director of Marketing, Synopsys, Inc.
In the course of the design and analysis of a typical 65 nanometer (nm) systems–on–chip (SoC) project, it’s not uncommon to generate more than two to three terabytes of data for even moderately–sized designs. In addition, the design teams producing all of this data are increasingly separated by geography, language and specialization, which of course adds to the overall challenge of efficiently executing design programs. Yet, despite – and to some degree because of – this combination of program complexities, getting accurate and timely information on program status to all stakeholders – from the designers to the C–Level executives – in a form that can be quickly analyzed and acted upon has never been more important to the fiscal success of a design project.
Full Story >> http://www.chipdesignmag.com/display.php?articleId=3274
4. NewsEDA Companies in Definitive Merger Agreement Mentor Graphics Corporation and LogicVision, Inc. have signed a definitive merger agreement pursuant to which Mentor Graphics will acquire LogicVision. The transaction is expected to be tax–free to the stockholders for U.S. federal income tax purposes. The transaction has been structured as a stock–for–stock reverse triangular merger whereby a wholly owned subsidiary of Mentor Graphics will merge with and into LogicVision, with LogicVision surviving the merger as a wholly owned subsidiary of Mentor Graphics. The transaction is subject to the approval of LogicVision stockholders as well as customary closing conditions (but is not subject to regulatory approvals). The transaction is expected to close during the third calendar quarter of 2009. Mentor Graphics Corporation >> www.mentor.com/ LogicVision >> www.logicvision.com
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Join the 6th annual GSA & IET International Semiconductor Forum to be held June 2–3, 2009 in Munich, Germany. The 2009 Forum promises a strong program of speakers with tracks featuring business, executive, technology and operations topics most relevant to the European semiconductor community.
http://www.gsaietsemiconductorforum.com/
5. NewsPhysical Verification Test Drive Program Revved UpMagma Design Automation Inc. announced the availability of the Quartz DRC and Quartz LVS 2009.05 physical verification tools. This new version includes functionality improvements for advanced process nodes, including 45/40 and 32/28 nanometer, through optimizations specifically targeted for standard multi–core, multi–CPU computers. To ease adoption, this version offers improved compatibility with third–party legacy physical verification tools. The company also announced the “Liberate Me” program, enabling engineers to test drive the programs at no charge for 60 days. The tools eliminate iterations between physical design and physical verification. In–situ metal fill, hotspot fixing and other chip finishing operations are performed within Talus. Magma >> www.magma–da.com |
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Jul 26–Jul 31, 2009 San Francisco, California Moscone Center
The world’s premier EDA and semiconductor design conference and exhibition. DAC features over 60 sessions on design methodologies and EDA tool developments, plus the NEW User Track presentations. The exhibition includes leading EDA, silicon and IP providers.
www.dac.comSpringSoft, Inc. and UMC announced a foundry–certified Laker process design kit (PDK) for UMC 65nm manufacturing technologies. This jointly developed PDK is the result of collaboration to address the specialized design and leading–edge manufacturing requirements of their mutual customers. The companies’ on–going cooperation is focused on delivering a series of Laker–UMC PDKs that enable design teams to bring differentiated products to market faster. The kit supports mixed–mode technologies and low–k dielectrics. Technology options can then be implemented including mixed signal/RFCMOS and embedded memories to further customize the process. The PDK includes device symbols, highly optimized parameterized cells (i.e., Laker MCells), pre–validated design rules and the latest technology files.
SpringSoft >> www.springsoft.com
UMC >> www.umc.com
Simucad Design Automation announced affordable Universal Token based licenses for its complete PDK–based EDA software solution. This provides access to all Simucad and Silvaco software tools without re–issuing licenses. When a tool starts, it draws a tool–specific number of tokens from a universal token pool residing on the customer's license server. Tokens are never permanently consumed; when applications finish, their allocated tokens are automatically returned to the pool and made available for immediate re–use by any other tool. Unlike traditional licensing, no limitation is made on what tools are permitted to be used. Provided there are enough tokens in the pool, any application can be utilized.
Simucad Design Automation >> www.simucad.com
The PowerCentric low power clock tree synthesis tool from Azuro, Inc., is included in TSMC’s new Integrated Sign–Off Flow. This is an automated RTL to GDSII chip implementation flow that tightly integrates foundry technology files, pre–qualified library, IP, EDA tools, and sign–off margin recommendations into a fully automated scripted production–quality flow that has been proven and refined over hundreds of applications. The insertion of the tool into the Flow is completely transparent to users. Chip design teams taping out to the foundries can adopt the unique low power CTS capability within an extensively pre–tested pre–integrated production–ready flow including a full set of automated scripts and user documentation.
Azuro >> http://www.azuro.com
IMEC has presented functional 22nm CMOS SRAM cells made using EUV lithography. The 0.099µm² SRAM cells are made with FinFETs and have both the contact and metal1 layer printed using ASML’s full field extreme ultraviolet (EUV) Alpha Demo Tool (ADT). The ultra–small circuit structures were made using Applied Material’s most advanced deposition systems. For the front–end–of–line process, IMEC used its high–k/metal–gate FinFET platform. The FinFETs consist of HfO2 as dielectric and TiN as metal gate and NiPt silicide for the source/drain. The minimum active FIN pitch is 90nm. The FinFET layers were printed using ASML’s 1900i immersion lithography tools.
IMEC >> http://www.imec.be
The 46th Design Automation Conference (DAC) will include a “Community–Driven” DAC Pavilion Panel for the first time, featuring a topic chosen by the DAC community. Members of the DAC community are invited to visit http://tinyurl.com/pavilionpanel to vote for their favorite of four topics by May 31.
Topic 1: Wearable Sensor Networks: High–Tech Haute Couture
Topic 2: Power Scavenging: Waste Not, Want Not
Topic 3: Netbooks: Where Mobile and PC Industries Collide
Topic 4: Survival Strategies: Staying Relevant in Today’s Job Market
The topic that receives the most votes will be presented in the DAC Pavilion on Wednesday, July 29 from 10 to 10:45 a.m. The panelists and moderator will be announced on June 15, 2009. DAC will take place July 26 – 31, 2009 at the Moscone Center in San Francisco.
Design Automation Conference (DAC) >> www.dac.com
Advanced FPGA design demands verification innovation! Joe Rodriguez demands we do it intelligently and reduce risk too. See what your programmable hardware search can gain, or lose, in “Reducing the Risk of FPGA Innovation.”
Full Story » http://www.chipdesignmag.com/display.php?articleId=3002
Programmable hardware can not only save you time and development cost, it can protect your innovations. Let Mandel Yu introduce you to a new class of primitives, Soft PUFs, that you can use to develop security–oriented applications not possible before. Scout out this new territory in “Exploiting Uniqueness of FPGA Silicon for Security Applications.”
Tech Ed North America 2009
Los Angeles, CA
May 11–15, 2009
http://www.msteched.com/teched/default.aspx
NMI International Conference on CMOS Variability (ICCV 2009)
Savoy Place, London
May 12–13, 2009
http://www.nmi.org.uk/conference/
IEEE Computer Society Annual Symposium on VLSI, 2009
Tampa, Florida
May 13–15, 2009
http://www.eng.ucy.ac.cy/theocharides/isvlsi09/index.htm
International Symposium on Circuits and Systems (ISCAS 2009)
Taipei International Convention Center, Taipei, Taiwan
May 24–27, 2009
http://www.iscas2009.org/
16th Annual Reconfigurable Architectures Workshop (RAW 2009)
Rome, Italy
May 25–26, 2009
http://www.ece.lsu.edu/vaidy/raw/
IMEC Technology Forum 2009 (ITF2009)
Crowne Plaza Hotel ‘Le Palace’, Brussels
June 2–4, 2009
http://www.itf2009.be/
International Symposium on Rapid System Prototyping
Paris, France
June 23–26, 2009
http://www.rsp–workshop.org/
International Symposium on Rapid System Prototyping
Paris, France
June 23–26, 2009
http://www.rsp–workshop.org/
IEEE International Conference on Application–specific Systems, Architectures and Processors
Radisson Hotel Boston, Boston, MA
July 7–9, 2009
http://www.asap–conference.org/
SEMICON West 2009
Moscone Center, San Francisco, CA
July 14–16, 2009
http://www.semiconwest.org/
ASQED 2009 (Asia Symposium on Quality Electronic Design)
KL, Malaysia
July 15–16, 2009
http://www.isqed–asia.org/
SAMOS IX: International Symposium on Systems, Architectures, MOdeling and Simulation
Samos, Greece
July 20–23, 2009
http://samos.et.tudelft.nl/samos_ix/
IWLS 2009 (International Workshop on Logic & Synthesis)
Cadence Research Laboratories,
Berkeley, California
July 24–26, 2009
(Co–located with DAC).
http://www.iwls.org/
System Level Interconnect Prediction 2009
Moscone Center, San Francisco, CA
July 26–27, 2009
(Co–located with DAC)
http://sliponline.org/
IEEE Symposium on Application Specific Processors, SASP 2009
San Francisco, California
July 27–28, 2009
(Co–located with DAC)
http://www.sasp–conference.org/
46th Design Automation Conference (DAC)
Moscone Center
San Francisco, Calif.
July 26–31
http://www.dac.com
IEEE International Midwest Symposium on Circuits and Systems (MWSCAS 2009)
Cancún, México
August 2–5, 2009
http://www–elec.inaoep.mx/mwscas2009/
Signal and Image Processing (SIP 2009)
Honolulu, HI
August 17–19, 2009
http://www.iasted.org/conferences/home–654.html
Euromicro Conference on Digital System Design
Patras, Greece
August 27–29, 2009
http://www.iuma.ulpgc.es/dsd09/
International Workshop on Reconfigurable and Multicore Embedded Systems (WoRMES' 2009)
Vancouver, Canada
August 29 – 31, 2009,
http://embedded.cs.ccu.edu.tw/WoRMES2009/
(held conjunction with The IEEE/IFIP International Conference on Embedded and Ubiquitous Computing)
International Conference on Field Programmable Logic and Applications
Prague, Czech Republic
August 31 to September 2, 2009
http://fpl2009.org/index.php
SBCCI2009, Symposium on Integrated Circuits and Systems Design
Pirâmide Natal Resort and Convention, Natal, Brazil
August 31 to September 3, 2009
http://www.lasic.ufrn.br/chiponthedunes2009/sbcci/
Intel Developers Forum US, San Francisco
Moscone Center West, San Francisco, CA
September 22–24, 2009
http://www.intel.com/IDF/
Editor: Jim Kobylecky, jkobylecky@extensionmedia.com
Editorial Director: John Blyler, jblyler@extensionmedia.com
Advertising/Sponsorship Opportunities: Karen Popp, kpopp@extensionmedia.com
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In this issue Azuro’s Marc Swinnen thinks it’s time to get synthesis back in synch. See why and how in Physical Synthesis is Broken—Why Clocks Are Crippling Migration to 45nm and Below. Next Matt Gutierrez of Synopsys focuses in on how to breakdown barriers of geography, language and specialization. His Going Graphical to Better Manage Design Schedules displays the right direction. Then solve your present tense puzzles with our news abstracts and regular features. And then round it out with a look at the excellent programmable hardware coverage we bring you every month in our star sibling Programmable Logic Device Designer and its stellar predecessor, the FPGA Developer waiting at Chip Design’s newsletter page: 
Ten years ago, the EDA industry faced a crippling divergence in timing caused by rapidly rising wire capacitances relative to gate capacitances. Today timing is diverging once again, but this time it is around clock tree synthesis (CTS). This divergence is called the “clock timing gap” and, while its ultimate cause has remained largely unrecognized by designers, the effect is so severe that it is having a critical impact on the economic viability of migration to the 45nm and below.