Happy Holidays and welcome to the December 2007 issue of FPGA Developer where the Xmas bytes are merry and bright. We complement Chip Design magazine by covering the realm of programmable devices -- including FPGAs and Structured ASICs providing opinions from industry experts, and high lighting technology articles. See below for subscribe and unsubscribe options.
Where's Waldo? Accelerating an Object Recognition Algorithm Acceleration
Structured ASICs Afford Clear Advantages for Mil/Aero Applications
Integrated Real-Time Trace Support Simplifies Configurable Processor Applications
Equivalence Checker Dedicated to FPGA Synthesis Verification
Synplify Premier software provides the fastest method for finding hardware bugs providing simulator-like visibility into a live running FPGA with real-world stimulus.
By Jim Kobylecky, Editor
They won’t stop caroling! How can I get my head back into Captain Bligh and the Mutiny of the Cowboys, when the grizzled grey beards in the back cubicles keep singing “Deck the Halls with FETs” and “I’m Dreaming of a Pure Geranium Diode?” You guessed it; they’ve been celebrating the 60th birthday of the transistor all month long.
What they SHOULD be celebrating is this issue of the FPGA Developer. We start up with a special high-speed holiday computing viewpoint by Greg Edvenson of Pico Computing. Greg illustrates how hardware parallelism can speed up a soft search in “Where's Waldo? Accelerating an Object Recognition Algorithm Acceleration.” Or if ensuring world peace in the holiday season is your goal, consult with Barry West of AMI Semiconductor. He’ll suggest that “Structured ASICs Afford Clear Advantages for Mil/Aero Applications.” Then close the year with our usual eye-opening regular features. Full Story»
By Greg Edvenson, Senior Engineer, Pico Computing
Recently, we were looking for a way to demonstrate how compute-intensive image processing applications can be accelerated using FPGA-based platforms, and using C programming methods. Software designers often assume that high performance requires a high clock speed. We wanted to show how much processing can be performed by taking advantage of hardware parallelism, at much lower clock rates and lower power consumption than would required in a traditional processor.
We work with quite a few military/security customers. For some of these customers, “finding the bad guy” is an application of great interest. But even in non-military applications, object and feature recognition is a key component of many image processing algorithms. Such algorithms are used in robotics systems, in quality control applications, in advanced vehicle systems, and many others. Feature recognition can also be used to pick out a certain vehicle on a road, or a specific face in a crowd. Full Story»
By Barry West, AMI Semiconductor, principal systems architect for Mil/Aero and Digital Products/Services
There are compelling reasons in many markets to use a structured ASIC when compared to other custom logic platforms. The primary reasons include low production cost and low power when compared to FPGAs. When compared to full custom ASICs the list includes low NRE, support for low volume production and quicker development time. These benefits are especially advantageous for military and aerospace applications, and are complimented by several others, making structured ASICs particularly compelling in these unique and often severe avionics, munitions, battlefield, and space environments. This article looks at some of the specific benefits structured ASICs offer to the mil/aero market by reviewing requirements for several different application areas and how structured ASICs are used to meet them.
In avionics applications for both the commercial and military sectors where flight critical electronic devices are exposed to neutron-induced single event upset issues (SEU), structured ASICs have distinct advantages over volatile SRAM-LUT based FPGAs. Structured ASICs are hardwired devices and don’t have functional dependencies on the contents of SRAM tables. They are not nearly as sensitive to radiation effects that can inadvertently change the functionality of an FPGA during a mission. Also, FPGAs require time at power up to program the device for its functional requirements which can cause concerns in the case of system power down or reboot during flight. Structured ASICs are live at power up and are functionally ready for use much quicker than an FPGA. These safety and reliability concerns make most FPGAs a poor fit for flight critical applications. Full Story »
Synplify Premier software provides the fastest method for finding hardware bugs providing simulator-like visibility into a live running FPGA with real-world stimulus.
The newest member of Microtronix Datacom Ltd.’s family of video IP development kits will help video display designers create highly integrated HD 1080p, 100-/120-Hz frame rate conversion television sets or panel display systems. Developed in cooperation with Altera, the ViClaro III HD Panel Display Interface features the highest density Cyclone III FPGA, the EP3C120 device, as well as an HD multimedia interface (HDMI) and USB 2.0 PHY. With its system integration capabilities, the kit is an ideal starting point for developing HDTV systems, broadcast video conversion/processing applications, HD projectors or plasma/LCD TVs, DVD recorders and cameras, video test and measurement equipment, and medical diagnostic equipment.
Microtronix >> www.microtronix.com
Mentor Graphics Corporation has announced that its Precision Synthesis solution, combined with Xilinx SmartGuide technology, results in significant design time savings. Test results conducted jointly over the past twelve months show that users saved an average of 40% in mapping and place-and-route (P&R) time. The combined solution preserves unchanged portions of the design when making small changes, reducing overall design iteration time. Tests also show that over 97% of the components went unchanged and quality of results (QoR) was maintained in the process. The companies report that these results have also been verified by mutual customers. It is an automatic, “push-button” technology that optimizes incremental design changes.
Mentor Graphics >> www.mentor.com
Synplify Premier software provides the fastest method for finding hardware bugs providing simulator-like visibility into a live running FPGA with real-world stimulus.
Actel Corporation’s new Icicle Kit showcases the ultra low-power attributes of the company's 5-microwatt IGLOO FPGA. The $99 kit allows designers to program, evaluate and modify their IGLOO-based portable designs. The small cell phone-sized evaluation board consumes less than one-seventh the power of competitive development solutions. It is an environmentally-friendly, RoHS-compliant solution that integrates a nonvolatile, 125,000-gate AGL125 FPGA with built-in, rechargeable lithium-ion battery, USB-to-UART interfaces, and power management circuits. It includes a sophisticated programming stick for extended functionality and a free, unlimited-use license for the company’s Integrated Design Environment (IDE) Gold edition. There is also a user's guide and tutorial, printed circuit board (PCB) schematics, layout and sample design.
Actel >> www.actel.com
Altera's new Embedded Evaluation Kit Cyclone III Edition provides a low-cost "hands on" way for embedded designers to assess the company’s Nios II processor, SOPC Builder system design software, and custom applications. It combines a Starter Board and a touch screen LCD in a unique plexiglass case, allowing developers to launch example applications with just the touch of a finger. It also serves as an ideal development platform for software designers new to FPGA-based processors. It includes several tutorials and design examples such as hardware acceleration of image processing applications and a remote FPGA update design that demonstrates how FPGA developers can update hardware designs over the Internet to add new product features or deliver bug fixes.
Altera >> www.altera.com
Tensilica, Inc. has added an optional full-speed, non-intrusive instruction trace capability to all of its Diamond Standard and Xtensa configurable processor cores. The trace capture macrocell is Nexus 5001 compatible and ideal for debugging complex, challenging real-time applications such as engine and motor control. Software control and use of the on-chip TRAX hardware is fully integrated into the company’s Xplorer integrated design environment (IDE) to speed development and debug. The company’s configurable processors can be exactly configured and matched to applications. Adding instructions to the processor can accelerate data processing to meet real-time constraints in an area and power efficient way, allowing the smaller, lower-power, optimized processor to replace a much bigger general-purpose processor core.
Tesilica >> www.tensilica.com
Munich’s OneSpin Solutions GmbH has a sequential equivalence checking solution dedicated to and priced for the FPGA market. Their stand-alone 360 EC-FPGA equivalence checker supports all sequential optimizations performed by FPGA synthesis tools. It enables designers to verify functionality without disabling the advanced synthesis optimizations vital to achieving functional, performance and cost goals. Support inclues all Altera Stratix and Cyclone FPGAs, also HardCopy, most Xilinx Spartan and Virtex products; and the Synplicity Synplify Pro synthesis flow — including gated clock conversion. Their tool verifies functional equivalence between RTL code and post-synthesis FPGA netlist, and between the post-synthesis netlist and post-place-and-route FPGA netlist.
OneSpin Solutions >> www.onespin-solutions.com
Readers may be wondering about the quest of FPGA High Performance Computing Alliance’s “Maxwell” at the British Computer Society IT Awards we reported on last issue. Yes, the unique supercomputer, built in Scotland by the FHPCA with the support of Scottish Enterprise, did come home with a medal. The FPGA supercomputer scored runner-up’s status in the much coveted BT Flagship Award for Innovation. Maxwell’s use of FPGAs requires much less space and cooling than a conventional microprocessor system. It is also over 100 times more energy-efficient and up to 300 times faster. The Alliance is led by EPCC at the University of Edinburgh and comprises Alpha Data, Nallatech, Xilinx, Algotronix, Scottish Enterprise and the iSLI.
FHPCA >> www.fhpca.org
Is there place for Low-Speed Computing? I’m not sure, but there are different kinds of computing with different advantages and disadvantages. Let Clive (Max) Maxfield take you for a robotic tour of the Wild Side in “The Computing Universe.”
Featured Story >> http://www.chipdesignmag.com/idesign/
For really old computing, why not start at the beginning? There were gearheads long before Maxwell, and we’re just beginning to uncover their story. Look back a few months (and a few thousand years) with your editor to consider “Clan of the Cave Engineer — Part I: The Antikythera Mechanism.”
Featured Story >> http://www.chipdesignmag.com/display.php?articleId=1304
International Conference on Microelectronics (ICM 2007)
December 29-31, 2007
Nile Hilton, Cairo, Egypt
www.ieee-icm.com
2008 International CES
January 7-10, 2008
Las Vegas Convention Center, Las Vegas, Nevada
www.cesweb.org
International Solid-State Circuits Conference 2008
February 3-7, 2008
San Francisco Marriott Hotel, San Francisco, California
www.isscc.org/isscc/index.htm
DesignCon 2008
February 5-6, 2008
Santa Clara Convention Center, Santa Clara, California
www.designcon.com/2008
DVCon 2008
February 19-21, 2007
Doubletree Hotel, San Jose, California
www.dvcon.org
FPGA 2008
February 24-26, 2008
Monterey Beach Resort, Monterey, California
www.ece.wisc.edu/~kati/fpga2008
International Symposium on Quality Electronic Design (ISQED'08)
March 17-19, 2008
DoubleTree Hotel, San Jose, CA
www.isqed.org
Editor: Jim Kobylecky, jkobylecky@extensionmedia.com
Editorial Director: John Blyler, jblyler@extensionmedia.com
Advertising/Sponsorship Opportunities: Karen Popp,
kpopp@extensionmedia.com
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