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Chip Design Buyers Guide
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Interoperability
Solution Guides
Mentor Graphics Questa Vanguard Program
Synopsys Interoperability Guide
Cadence and Third Party Solution Guides
Switched Interconnect Technologies
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Product Showcase
EdXact: Bringing Innovation Into The Verification Flow
Semiconductor Technologies > IP--Core - PLL and DLL Hard Macros
MOSAID Virtual Silicon Semiconductor IP
Carbon Design Systems' SOC-VSPT
True Circuits Product Showcase
Accelerate Forward with Poseidon Systems
PCI Express Integration and Verification
Programmable Digital Frequency Synthesizer (DFS) PLL
Develop DFM Tools. Better. Faster.
On-Demand Web Seminar Sponsored by Avnet Electronics Marketing
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Focus Reports
Object-Oriented Programming— Steep Learning Curve Ahead
OOP is �nally starting to look promising.
Collaboration Models
Working With the “Enemy” Requires Flexibility and Commitment
[Focus Report] What makes chips different?
IBM, Samsung team up to differentiate chips with embedded software modules, but can it work this time?
Chip-Package-Board Co-Design: It's a Brave New World
In the case of today’s bleeding-edge SoC, SiP, PiP, and PoP components, it’s no longer
Second-Tier EDA Vendors Must Collaborate to Survive
With today's mature chip-design flow, innovative point solutions must support multiple vendor formats and strive to work within established standards.
Future Verification Appears Uncertain
The EDA market is struggling to solve new verification challenges.
Will changes in investment patterns dampen the market rollercoaster?
Know the Key Aspects of IP Integration
DFM and DFY: Old Solutions to New Problems
The semiconductor industry's shattered supply chain must be reintegrated, replacing clever point solutions with holistic and economical flows.
Automotive Electronics Rise To Meet Consumer Demand
With the complexity and quantity of automotive electronics steadily increasing, designers are turning to better EDA tools and programmable solutions.
Military Seeks Systematic Approach to IC Design
The EDA community is focusing on point solutions while system-level development continues to evolve.
Virtual Prototypes Form ESL Bridge
Sometimes, the best way to understand an abstract phrase like ESL is to focus on understanding the constituent processes.
Analog-RF IP Integration Challenges SoC Designers
As market forces continue to push more analog and RF functionality into digital SoCs, designers face a host of development issues.
Latest Challenges & Trends in Chip Verification
The sophistication of verification tools and techniques has increased with design complexity.
Navigating the Silicon Jungle: FPGA or ASIC?
FPGA, structured-ASIC, and ASIC design implementations can be differentiated by tradeoff studies and an understanding of the basics behind each target platform.
Structured ASICs: A Reality Check
A virtual roundtable addresses the issues surrounding the technology
Verification Tools
Adding more tools improves the probability of silicon success
Focus Report: Electronic System-Level (ESL) Tools
A bolt-on to RTL or a new methodology?
Hardware Tools for Design
Risk reduction always comes at a cost--trial and error will determine how much.
Focus on Analysis Tools
To point or integrate, that is the question
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Visit Dot.org
Learn About Important Industry Organizations
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Find A Job
Product Development Test Engineer

2005 EDITORIAL CALENDAR
| Issue | Focus Report | Editorial Features |
| Dec/Jan (2004-05) |
Buyers’ Guide Issue |
|
| Feb/Mar | ESL |
|
| April/May | Analog-RF Design |
|
| June/July | ASIC |
|
| Special Issue | Resource Catalog |
|
| Aug/Sept | HDL Simulators |
|
| Oct/Nov | Test |
|
| Dec/Jan | Buyers’ Guide |
|
Design articles are user-based case studies that demonstrate the solution to specific problems through the use of new tools or methodologies. By covering issues from different perspectives-high-end, middle range, and programmable designs-the content will be a vehicle for cross-fertilization of ideas and increased sharing of function-specific knowledge.
Focus reports are an annotated listing of all the EDA tools in one tool category. By providing reference to uniform data categories, the focus reports allow designers to quickly scan all the product offerings and get contact information to the various vendors.
Guidelines for Submitting Articles
Chip Design provides engineers and technical management with an opportunity to contribute a technical article. Contributionsare written "by engineers for engineers." The target audience is EDA users who design ICs; power users pushing the state of the art, upper mainstream users advancing levels of integration, and the developers of systems on a programmable chip, the largest PLDs.
A contributed article is not a place to hype a product's features and capabilities. It is a place to talk about technical challenges and solutions, in the context of (1) a proposed or new standard or one that is evolving; (2) an application story from a company using a solution that you advocate; (3) how to use a particular architectural building block; (4) how to use a particular software tool or methodology.
There are a number of ways to discuss a new architecture, subsystem, software or tool:
Good: you can ignore these details in most cases
Bad: it affects the nominal cases much less and only matters for the corner cases in certain extreme situations.
Submission procedures
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