Synopsys
Fujitsu Microelectronics America, Inc.
Multicore in the Age of the Unthinkable
Recently, I had the opportunity to read and finish in one weekend, ‘The Age of the Unthinkable’, by Joshua Cooper Ramo...
Reader Wants Print, not Links
How do the readers of Chip Design - mostly engineers if one believes the polls - prefer to receive editorial content? Print...
Wishing you were (virtually) here
Yesterday I participated in an interesting experiment .... EETimes' Virtual conference on Multicore. It was an interesting...
How Low Can We Go?
In an article this week in one of the industry trade publications, an iSuppli source was quoted as saying, “The usable...
CADENCE INTEROPERABILITY GUIDE
As the electronics industry moves toward advanced CMOS process geometries at 65nm and below, considerable power management challenges have emerged that cannot be met by a desig ...
By: Susan Runowicz-Smith, Group Director, Cadence Design Systems, Power Forward InitiativeAMIQ
Sentinel: Power, Noise, Reliability Platform for Chip-Package-System Co-DesignApache Design Solutions
ENOVIA Synchronicity DesignSync DFIIIDassault Systèmes
eInfochips releases highly configurable, URM compliant HDMI UVC for verification of HDMI compliant deviceseinfochips
Hummingbird®: Pushing the Limits of Cadence Applications and Exceed UsersHummingbird
MunEDA WiCkeD™: Improve Design Performance and YieldMunEDA
EDAConnect-SiPPerception Software
PLDA - Premier PCIe IP Products featuring Support for Cadence ToolsPLDA
Semiconductor IP SolutionsVirage Logic Corporation

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