Circuit and Process Advances at ISQED Deliver Improved Performance


Last week’s International Conference on Quality Electronic Design (ISQED) held in Santa Clara bridges the gap between, and the integration of, electronic design tools and processes, integrated circuit technologies, processes and manufacturing to achieve the best possible design quality. At the conference, the multiple keynotes by Chenming Hu, TSMC Distinguished Professor at the University of California at Berkeley Graduate School, Brad Brech, a member of the IBM Academy of Technology, and Bill Swift, the Vice President of Engineering at Cisco Systems presented a look at the evolving device technology, sustaining innovation for smarter computing in data centers, and a system-level perspective on semiconductors for intelligent networks, respectively.

At the keynote luncheon, Ed Petrus, the Director of Custom Architecture for the Deep Submicron Division of Mentor Graphics, examined the trends and issues with analog/mixed-signal design tools. Additional keynotes on the second day included presentations by Sanjiv Taneja, the Vice President of Product Engineering at Cadence Design Systems and Perry Goldstein, the Director of Sales and Marketing for Marshall Electronics. Taneja discussed advances in physically aware, high-capacity RTL synthesis for advanced nanometer designs, while Goldstein gave an end-systems look at the lifecycle issues of audio products for both consumer and professional applications. 

Professor Hu kicked off the plenary session with a look at changes to transistor structures ranging from vertical FinFET devices to the latest developments in ultra-thin-body (UTB) devices. Future devices such as the UTB transistors, pillar structure devices, and tunneling transistors are all on the horizon as feature sizes shrink to 10 nm and below. However, as features shrink, the operating voltages also have to shrink. Thus, much of Hu’s research is studying ultra-low operating voltages – as low as 0.1 V Vdd – and the creation of tunneling transistors that can turn on or off with less than a 0.1 V change in gate voltage.

Driving this need for smaller and higher-performance devices are the ever-increasing performance demands of data centers and intelligent networks, as Brech and Swift respectively detailed in their keynote presentations. According to Brech, smarter computing overcomes the challenges of new analytics, cloud, big data, and security requirements through the use of appropriate technologies. Thus, doing things smarter and faster are the driving factors for the next generation of data centers. Intelligent networks go hand-in-hand with smarter computing in the data centers, and Swift examined the technology and business trends, as well as innovation drivers for advances in semiconductor technology that enable products and solutions for intelligent networks.

In the previous discussions,

There are many design aspects that can cause a design re-spin, with logic or functional errors leading the way by at least 2X any of the other causes. However, analog circuit tuning and mixed-signal interface issues also account for a significant percentage of re-spins.

the main focus has been on digital systems. However, many systems require interfaces to the analog world and thus analog/mixed-signal circuit integration with digital systems becomes an essential aspect of systems design. Toward that goal, Petrus discussed the unique challenges of designing custom ICs that leverage the smaller geometries such as Hu discussed in his keynote. These ICs are often assembled using multiple resources and various design methodologies that include IP reuse, top-down design, and bottom-up design. However, as Petrus pointed out, analog circuits are sensitive to layout, matching and proximity, and have demanding interface requirements, with advanced process nodes amplifying the design challenges.

Today’s mixed-signal SoCs often integrate many mixed-signal blocks that each contain a hierarchy of tightly-integrated analog and digital circuits. However, functionally verifying the mixed-signal designs remains a tough challenge, with simple simulation no longer able to do an adequate job. In fact, as Petrus explained using a graph supplied by Off-Chip Communications LLC, about 20% of all design re-spins were due to errors at the mixed-signal interface (see the Figure) – but 50% of design respins at 65 nm and below were due to issues with mixed-signal functionality. Although the chart’s numbers only show designs through 2007, the continuing shift to smaller features just exacerbates the re-spin challenges.

Thus, designers need a new discipline referred to as mixed-signal verification that combines skills in mixed-mode simulation, behavioral model generation, as well as characterization and test-bench development. The tools needed must achieve better verification of analog and digital interfaces, create a higher-level of abstraction for analog and mixed-signal blocks, verify the increased amount of digital logic in analog designs, automate the current manual custom design steps (especially in placement and routing), and adopt circuit analytics that tell the designer something about why and where the circuit is failing to perform.

RTL synthesis tools that are physically-aware and can deal with new physics effects, new device structures, interconnect stacks with vastly varying resistance characteristics, and process variations are the next challenge according to Taneja. Such RTL synthesis tools are needed to handle gigascale and gigahertz SoC designs and perform accurate and predictive modeling of the interconnect stack, vias, and other physical effects.

Dave Bursky
Chip Design Magazine

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