Overcoming Technology Hurdles to Continue Tracking Moore’s Law
At this week’s Intel Developer’s Forum in San Francisco, Intel Corp. provided a few technology roadmap details relating to the next two process nodes — 32 nm and 22 nm — that it expects to use to fabricate future-generation processors. According to Sean Maloney, the executive vice president and general manager of the Intel Architecture Group, “even as most companies struggle to get 45 nm processes on line and into volume production, Intel has already jumped that hurdle and is readying its 32-nm process for initial production in late 2009.” Transistors implemented on the 32 nm node will offer performance improvements of 19 percent (NMOS) and 28 percent (PMOS) over their 45 nm counterparts.
Dubbed a second-generation high-k metal gate process, the 32-nm node will initially be used to manufacture the Westmere processor, which the company expects to sample in late 2009. Westmere includes the company’s TurboBoost and Hyper-Threading capabilities and also incorporates AES encryption support on the CPU with new instructions and circuitry to speed the crypto algorithms. It is also the first CPU offered by Intel to include a closely-coupled graphics processor chip in the same package to improve graphics performance.
Following Westmere will be the next new microarchitecture processor, codenamed Sandy Bridge. This new processor will incorporate a sixth-generation graphics core on the same die and include AVX instructions for floating-point, media, and processor-intensive software. Additional processors targeted for the 32-nm node include device families with the codenames of Clarkdale and Gulftown. Also in the works is a family of devices targeted at mobile internet devices — Moorestown. These chips will achieve up to a 50X reduction in platform idle power. Following Moorestown will be Medfield, a third-generation platform that should be ready for sampling in 2011. This processor will be a full system-on-a-chip design that promises much smaller form factors and lower power designs than Moorestown.
Designs based on the 22-nm immersion-lithography process that is currently in development won’t be ready for a while. This third-generation high-k metal-gate technology further improves performance over the 45 and 32-nm process nodes and further lowers leakage currents, thus allowing systems to reduce idle power consumption.
Thus far Intel has only fabricated test structures and static RAM arrays to ensure that their process models are on target. At the forum they displayed a 12-in wafer with SRAM arrays. Each fingernail-sized array on the wafer contained 364 Mbits of SRAM (2.9 billion transistors). The 22 nm process allowed designers at Intel to shrink the size of a high-performance memory cell to just 0.092 square microns — the smallest memory cell in a working circuit reported to date. Another version of the cell optimized for low power is almost as small – just 0.108 square microns. Designers will thus be able to choose between the two depending on their system objectives.