Notable Analog Tool Advances Boost Designer Productivity
This year’s Design Automation Conference, recently held in San Francisco, CA, highlighted many advances in analog and digital circuit design tools, but in the analog and mixed-signal world many designers are hesitant to give up tried and true manual design techniques to implement their circuits. They feel analog design is still more of an art than a science and that most of the available tools can’t really come close to what a good analog designer can do. However, after hearing the pitches from several new and existing vendors of analog and mixed-signal design tools at this year’s DAC, I suspect many analog designers will be tempted to adopt some of the new tools to improve their productivity.
Although the major EDA tool suppliers–Cadence, Mentor and Synopsys—all have strong suites of analog and mixed signal design tools, smaller, highly-innovative companies are also crafting both suites of tools that cover the entire design flow, and vertical tools that solve specific problems. For those of you who didn’t make it to this years, DAC, here is a sampling of some of the new tools that support analog design.
Taking a “correct-by-construction” approach to analog IP delivery, newcomer Analog Rails from Chandler, AZ (www.analograils.com) offers an automated, parasitic-aware tool that they claim will significantly reduce support costs and schedule creep, and can deliver high-yield analog and mixed signal IP in hours rather than days, weeks, or months. The tools include a synchronized schematic and layout editor that allows designers to capture the complete design intent, including constraints, capacitance, and voltage back-annotation. The Analog Rails tool is also simulator agnostic, and includes the TSMC-approved MSIM simulator, infinite GnuCapplus Licenses, and can easily integrate any HSPICE compatible simulator into the flow.
Another fairly new face at DAC, Symica of San Jose, CA (www.symica.com) offers a suite of EDA tools for analog and mixed-signal IC design – from schematic capture to circuit simulation and layout. The tool suite handles analog, and analog behavioral and digital mixed-mode simulation in a flexible simulation environment. The tools also accept inputs from HSPICE- and Spectre-compatible netlists, and incorporate a powerful waveform viewer and analog-simulation result analyzer. This waveform tool offers all the functions designers expect (viewing results for TRAN, DC, AC, Sweep, Monte Carlo; customizable views of multiple plots; and may other features) and employs a simple-to-use graphical interface. A free version of the tool, Symica FE, allows users to try out most of the features on circuits with fewer than 500 transistors; however the free version does not support mixed-signal and Fast-SPICE simulation.
One of the trickiest aspects of analog circuit design is the placement of the devices and the routing to interconnect them. Taking aim at that aspect of design, Pulsic Inc. of San Jose (www.pulsic.com), offers a place-and-route solution for analog and custom digital design. The Pulsic Planning Solution builds on the work of last year’s planning tool released by the company, and offers easy-to-use guided flows to automatically implement precise, hand-crafted quality design layouts. The company’s Unity Analog Router delivers DRC-correct routing and completes routing patterns and topologies that an experienced analog designer would create when routing the layout by hand.
Adding analog prototyping to their tool suite, SpringSoft Inc. from Hsinchu, Taiwan (www.springsoft.com) showed off the Laker Analog Prototyping tool . The tool provides early feedback on the impact of layout parasitic and other layout-dependent effects, which can be particularly challenging to manage at the 20 nm process node. Key features include “smart” placement techniques that automatically generate multiple DRC-correct and routable options, hierarchical structure to handle thousands of transistors, and full support for a complete range of industry-standard parameterized device formatted, including MCells, PyCells, C++ PCells, and Tcl PCells.
Additionally, the tool enables automated constraint generation, layout exploration, and rapid implementation in a single flow. Built into the company’s Laker SDL flow, the analog prototyping tool automates the process of analyzing advanced process effects and generating constraints to guide circuit layout. The company claims that it results in a more-predictable design cycle and improves productivity with less time wasted on post-layout design adjustments when compared to convention design methods.
Another analog floorplanning tool demonstrated by JEDAT (Japan EDA Technologies) of Tokyo, Japan (www.jedat.co.jp) enables analog layout designers to automatically build accurate analog floorplans. The software includes constraint extraction and management, layout netlist with tuning from the circuit netlist, and analog block placement. The company claims the tool can deliver a fivefold improvement in layout efficiency while the layouts are high-quality and accurate thanks to multiconstraint-driven flexible layout hierarchy and flexible block boundaries. Additionally, the company has achieved a three to five time improvement in design time, as reported by over ten customers.
Design verification for analog circuits is the goal of the Analog+ suite of tools from Solido Design (www.solidodesign.com ). The tool provide rapid interactive device sizing with MonteCarlo accuracy, three-sigma statistical corners that truly bound analog performance, and final verification across all corners with a 2 to 10X speedup. Using adaptive machine-learning techniques the Analog+ Suite can complete tasks with fewer simulations compared to the hundreds of thousands of simulations typically required. The Monte Carlo+ tool in the suite is claimed by Solido to be the only EDA tool that can actually extract 3σ statistical corners. The patent-pending algorithm is fast, accurate, and scales up to tens of thousands of devices and beyond.
Chip Design Magazine