From the ultra-small 3D transistors described in papers at this month’s International Electron Devices Meeting (IEDM) in Washington, D.C., to the 2.5D and 3D multichip structures described at the 3D Architectures for Semiconductor Integration and Packaging (ASIP) conference held in Burlingame, Calif., designers are finding more ways to pack more transistors on a chip and to pack more functions into a limited area on a printed-circuit board. For instance, at IEDM TSMC Shien-Yang Wu and his team of researchers described a 16-nm FinFET process in paper 9.1 that they feel is one of the world’s most advanced semiconductor technologies.
The process is the first integrated technology platform to be announced below the 20 nm node, with key capabilities that include a 48-nm fin pitch and the smallest SRAM cell ever incorporated into an integrated process—a 128-Mb SRAM with a cell area of just 0.07 µm2 per bit. The process’ short-channel effects were well-controlled, with DIBL <30 mV/V, saturation current of 520/525 µA/µm at 0.75V (NMOS and PMOS, respectively) and an off-current of 30 pA/µm. Depending on the designer’s goal, the process delivers either a 35% speed gain or a 55% power reduction in comparison with TSMC’s existing 28-nm high-k/metal-gate planar process, and with twice the transistor density (Figure 1).
Figure 1: The 16 nm process platform developed by TSMC allows designers to get 55% reduction in operating power or a 35% improvement in operating speed vs the company’s established 28 nm high-K/metal-gate process.
Creation of a “superchip” was the goal of researchers at the New Industry Creation Hatchery Center at Tohoku University in Sendai, Japan. The heterogeneous 3D integration described by the Professor Mitsumasa Koyanagi in a plenary presentation at IEDM allows various kinds of device chips with different sizes, different functions, and different materials to be stacked to form the superchip. A key technology developed to achieve this consists of self-assembly and electrostatic (SAE) temporary bonding. To demonstrate the technology, the university fabricated several prototype superchips—examples include stacking MEMS chips, spin memory chips and a photonic device chip on a CMOS logic chip; a 3D back-illuminated image sensor with through-silicon vias stacked on top of an image processing chip; and a 3D microprocessor with self-test and self-repair functions.
The assembly process to create superchips starts with known good die (KGD) that are sorted from several device wafers and simultaneously bonded as a batch onto a carrier wafer (Figure 2, left). High alignment accuracy is achieved using the self-assembly and electrostatic bonding. The process repeats with additional carrier wafers. Multiple carrier wafers with the KGDs are then stacked onto a target interposer wafer. This allows multiple superchips to simultaneously be fabricated. The surface tension of liquid is used in the self-assembly scheme to simultaneously align many dies in parallel. Hydrophilic areas and hydrophobic areas are formed on the surface of the wafer or chip to obtain high alignment accuracy. As many as 500 chips have been simultaneously aligned with an average alignment accuracy of 0.05 µm within 0.1 seconds.
Figure 2: The assembly process to create superchips starts with known good die (KGD) that are sorted from several device wafers and simultaneously bonded as a batch onto a carrier wafer (left). The process repeats with additional carrier wafers and then multiple carrier wafers with the KGDs are then stacked onto a target interposer wafer using electrostatic bonding and debonding (right).
The electrostatic temporary-bonding and de-bonding method for assembly of the multiple carrier wafers allows the stacking integration of multiple chips (Figure 2, right). Many chips are simultaneously bonded onto the electrostatic carrier wafer (e-carrier) by the electrostatic force after the simultaneous alignment by self-assembly. The electrostatic force for temporary bonding is generated by applying a high voltage to the electrodes embedded in the e-carrier wafer. A high voltage with opposite polarity is applied to the electrodes for de-bonding the chips.
These two presentations are just the proverbial tip of the iceberg representing several hundred paper presentations at IEDM that covered process and manufacturing, memory technology, nano-device technology, power and compound semiconductors, advanced CMOS technology, and many other subjects. For more information, go to www.ieee-iedm.org.
Running concurrently with IEDM but on the opposite coast, the 3D-ASIP Conference in Burlingame delved into many aspects of 2.5 and 3D integration, ranging from basic integration, to various interposer technologies, to wafer handling and thermal challenges to name a few. Many of the presentations examined the evolution of assembly techniques to move from 2D to 2.5 D to true 3D implementations. Doug Yu, the Director of the Integrated Interconnect and Packaging Division at TSMC provided an overview of wafer-level system integration technology, while Robert Patti, the CTO of Tezzaron Semiconductor described a combination of dis-integration and then integration to create a high-density and high-performance memory stack (See “Advances in DRAM and non-volatile memories keep upping system performance”, Aug. 26, 2013). The architecture of the memory array provides 256 independent channels, each containing 256 Mbits of storage and capable of transferring data at 64 Gbits/s with a latency of just 9 ns
Another memory presentation by Eric Beyne, the Program Director for 3D System Design at IMEC examined high-bandwidth memory-logic 3D integration by either direct stacking or the use of interposers. One of the key aspects of leveraging the 3D integration is to reduce the power consumption of the chip-to-chip interconnects by lowering the voltage swing, widening the I/O to lower the transfer frequency, and use vertical interconnects in a chip stack to reduce the wiring length (Figure 3). Using 3D through-silicon vias and microbump interconnects designers at IMEC were able to assemble high-density chip stacks, but encountered issues with the increased power density. The high power density can result in thermal issues (increased temperatures) and higher temperatures could affect DRAM data retention since retention time decreases as temperature increases.
Figure 3: Multiple factors such as the I/O width, the load capacitance, the transfer frequency, and the operating voltage must be taken into account when estimating the power consumed in chip-to-chip interconnects. (Source, IMEC).
Just such thermal issues were discusses by Joseph Maurer a support contractor to DARPA, and by Muhannad Bakir, Associate Professor, School of Electrical and Computer Engineering at the Georgia Institute of Technology. At DARPA, Maurer described multiple projects aimed at pulling out the heat and improving thermal conductivity. Techniques such as the use of copper nanosprings; near-junction thermal transport with liquid cooling and high-thermal conductivity diamond substrates; the use of a 3D vapor chamber with vibrating elements; the use of thin-film superlattice materials; and still other approaches are all being explored. Examining the use of microfluidic cooling on 3D ICs, Bakir showed a potential solution using coolant cycled through a multichip stack composed of two processor layers and a memory stack (Figure 4). With such a stack there are concerns about the reliability of circulation system used the microfluidic cooling, as well as the endurance of the TSVs since they are under pressure from the liquid flowing between the layers.
Figure 4: Microfluidic cooling between layers of chips, can pull out the heat, but there are concerns about the reliability of the microfluidic I/O technology as well as power-supply noise and the durability of TSVs due to the pressure of the liquid coolant as it flows through the package. (diagram courtesy of Georgia Tech).
These few papers were just a few of the presentations at the 3D-ASIP conference. For more details, go to www.3dasip.org to view the program or purchase the proceedings.
Semiconductor Technology Editor