Archive for August, 2013

Advances in DRAM and non-volatile memories keep upping system performance

Monday, August 26th, 2013

In the drive to improve system performance, faster processors often end
up spotlighting system bottlenecks, especially in the memory subsystem. To
reduce those bottlenecks, designers are developing faster-accessing memories,
faster interfaces with reduced overheads, and even new memory architectures and
technologies. At this month’s MemCon conference in Santa Clara, Calif., presentations
highlighted many of the developments in storage subsystems and devices that
promise improve memory subsystem performance. Memory interfaces such as DDR3
will soon give way to DDR4 and the low-power DDR3 will give way to LPDDR4,
while new interfaces such as HMC (hybrid memory cube), Wide I/O 2, eMMC 5.0, and
NVMe are gaining acceptance for future system designs.

When designers try to start implementing systems based on these new
standards, having functional models that can link into the memory subsystem
help verify system designs before any hardware gets built. Released at the
conference, new verification IP models developed by Cadence Design Systems for
DDR4, LPDDR4, Wide I/O 2, eMMC 5.0, and HMC allow designers to check out their
designs, while providing them with trace debugging, address scrambling, and
backdoor memory access. The models support all leading third-party simulators,
verification languages, and methodologies, thus enabling SoC designers to
verify the correctness of the interfaces to the specialized memories.

New memory architectures, such as the Dis-integrated 3D RAM developed
by Tezzaron Semiconductor (Figure 1a) and the Hybrid Memory Cube developed by
Micron Semiconductor (Figure 1b) in conjunction with Samsung, SK Hynix, Open
Silicon, IBM, ARM, Altera, and Xilinx, promise to provide much higher bandwidth
– in the case of the HMC module, a bandwidth of 160 Gbytes/s, which is a 15X
boost in memory bandwidth over a DDR3 memory module, while Tezzaron is
projecting a data bandwidth of 16 Tbits/s for its novel memory structure.


Figure 1a: The high-density memory subsystem proposed by Tezzaron consists of multiple layers of DRAM memory cells and access transistors. These layers sit on top of a layer of sense amplifiers and control logic, which, in
turn, sits on top of another chip that contains the I/O circuits.

Figure 1b: The hybrid memory cube developed at Micron also consists of multiple thinned chips that each contain multiple blocks of DRAM cells.  The multiple chips are stacked using through-silicon vias and sit on top of a logic chip that controls access to all the memories and the I/O operations.


Both the Tezzaron and Micron solutions have a somewhat similar approach
– multiple layers of thinned DRAM storage chips all interconnected and then connected
to a lower layer or two that contains the control logic and I/O. In Tezzaron’s
concept, there are 256 independent memory channels with each channel containing
256 Mbits of storage and delivering a 64 Gbit/s bandwidth. This gives the
DiRAM4 stack the capability of delivering 21 billion transactions per second.
Micron’s hybrid memory cube consists of a single package containing multiple
memory die and one logic die, stacked together and interconnected using
through-silicon via (TSV) technology. Within an HMC, memory is organized into
vaults. Each vault is functionally and operationally independent. Each vault
has a memory controller in the logic base (called a vault controller) that manages
all memory reference operations within that vault. Each vault controller
determines its own timing requirements. Refresh operations are controlled by
the vault controller, eliminating this function from the host memory controller.

One additional presentation at MemCon discussed the future of ReRAM (resistive
RAM) as a possible DRAM replacement. A new material developed by 4DS, dubbed
MOHJO (metal oxide heterojunction operation) allows the company to develop ReRAMs
with a high cycle live, low power dissipation, good data retention, reduced
manufacturing time and cost, and it also solves the word-line drop problem that
occurs with other ReRAM solutions. The MOHJO material is deposited on the
back-end of the process flow, on top of a standard CMOS manufacturing flow. The
material has low-current reset state that permits large blocks of memory to be
erased, and MOHJO-based memories can be especially useful in solid-state drive
systems by lowering the energy consumption by almost 100X. In comparison to
flash, spin-torque technology (STT), phase-change memories (PCM), and MOHJO,
the MOHJO technology has about the same endurance as PCM storage, but its
endurance is significantly lower than STT memories yet higher than flash. Read
and write performance of the MOHJO memories is symmetrical and ranges from 10
to 50 ns, which is about 200X faster than flash but competitive with STT and
PCM memories (See the table). The company expects this technology to be used in
both flash replacement applications, as well as a nonvolatile cache in hybrid DRAM

Performance comparison of Flash, STT, PCM and MOHJO technologies

Dave Bursky

Semiconductor Technology Editor

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