The recently held Semicon West and Intersolar Conferences in San Francisco were interesting examples of technology extremes. At Semicon, for example, major efforts are underway to define the equipment and fabrication facilities needed to produce chips based on 450 mm diameter wafers, while at the other extreme at Semicon, device and equipment designers were challenging each other to define and design ultra-small transistors and the lithography and other systems capable of fabricating devices with gate dimensions of 14 nm, 10 nm, and even smaller features. Intersolar also had it extremes, with presentations discussing energy efficiency of photovoltaic cells measuring a few square inches to the performance aspects of multi-square-meter PV panels and the implementation of large multi-acre commercial PV arrays.
Large research consortiums such as IMEC (formerly the Interuniversity Microelectronics Centre) in Leuven, Belgium, LETI (Laboratoire D’Electronique et de Technologies de L’Information) in Grenoble, France, Sematech in Albany, NY, as well as foundries such as Global Foundries, TSMC, and others are all working hard to define and qualify the processes needed for future-generation chips. Over the past few decades, scaling has lowered the cost of transistors by integrating more and more devices on a chip, even as the cost to fabricate the chips continued to increase.
However, Kurt Ronse, director of advanced patterning at IMEC explains that the extremely high cost of fabrication tools and facilities to implement features of 14 nm and smaller, has led to an increasing cost per transistor. The higher cost comes as a result of the use of triple or quadruple patterning with 193 nm immersion lithography. Such patterning techniques require many more masks to create the ultra-small features, and the higher number of masks adds considerably to the fabrication cost. Subi Kengeri, the Vice President of Advanced Technology Architecture at Global Foundries confirmed the rising cost of lithography comparison to other factors in a TechXpot presentation. In the graph he presented, various steps in the manufacturing process—etch, CMP, Doping, Metrology, metal deposition, dry etch, diffusion and dielectric deposition, and lithography were compared for relative costs (Figure 1). In most cases only moderate cost increases were observed. However lithography costs escalated the most for 193i for nodes below 20 nm.
According to Ronse, it will still be a few years before EUV systems can be used in mass production, but only EUV systems can enable the 50% scaling needed to reach the 10 nm node. Current EUV research has led to UV power sources capable of delivering about 55 W. However, for a tool capable of commercial production, UV sources capable of 250 W will be needed. Such sources are not expected until 2015 at the earliest. Additionally, Ronse is hopeful that at the 10 nm node, EUV lithography can reverse the cost escalation trend since double or triple patterning would not be needed to create the 10 nm features (Figure 2).
Figure 2: Researchers at IMEC also agree that lithography costs have become a significant portion of the fabrication flow. In this graph the 28 nm node is used as the relative reference, with the 20 nm node costing almost 50% more and the N+1 193i showing an almost 80% cost increase over the 28 nm node, while the use of EUV promises to reduce the cost increase to just 20% vs the 28 nm node.
At the device level there has been much written about the three-dimensional FinFET structures and the high performance that such transistors can deliver. However, there is a competition brewing between FinFET advocates and the supporters of planar fully-depleted silicon-on-insulator (FDSOI) device structures. Additionally, to further boost device performance, researchers are looking beyond silicon for the channel material in future transistor structures — options being researched include III-V materials, silicon-germanium, germanium, and carbon nanotubes.
As Maud Vinet, the FDSOI Manager at LETI explained, the planar FDSOI structure requires fewer masks and is easier to scale than the 3D structure of the FinFET. Additionally, with FDSOI designers can take one of two directions – they can opt for lower power consumption at comparable performance to current designs, or they can design for higher performance at comparable power levels. This quarter Vinet expects LETI’s development partner, STMicro, to start releasing FDSOI 14 nm design kits, while in early 2014, device and process models for 10 nm FDSOI designs should be ready for STMicro to develop the design kits for release to the availability in the third quarter of 2014.
Dave Bursky, Chip Design Magazine