Archive for May, 2013

New Processor Core Options Try Some ARM Wrestling

Monday, May 13th, 2013

When designing a system on a chip (SoC) that employs one or more embedded processor cores, the choice of available processors continues to expand. At last month’s Design West conference in San Jose, Calif., designers were presented with many processor options. Leading the pack, ARM, with its broad array of cores offers a wide range of performance choices, ranging from the Cortex-M0 at the low end of the performance spectrum to the 64-bit Cortex A57 at the high end. Although ARM’s cores dominate some SoC market segments, they aren’t the only game in town. EDA tool suppliers Synopsys and Cadence have acquired core suppliers ARC and Tensilica, respectively, and recently, Imagination Technologies acquired MIPS. Thus the number of independent processor core IP providers dropped considerably, but not for long.

One newcomer to the U.S. market, Andes Technology, has crafted multiple, synthesizable processor-core families, the N7, N8, N9, N10, N12, and N13, that offer 32-bit cores with gate counts that start at just 12k gates (for the N7). For applications that don’t require legacy compatibility these cores can challenge ARM and other vendors for embedded applications. Based on a proprietary instruction-set architecture (ISA), the N7 family cores can deliver about 1.19 MIPS/MHz, which is about 20 percent higher than the ARM Cortex-M0. Additionally, the cores consume about 30 percent less power at the same performance level as the M0. The low-gate-count core, referred to as the Hummingbird, also requires a small amount of chip real-estate – less than 0.04 mm2 when fabricated using a 90 nm process. With optional features such as a prefetch buffer that can serve as a small instruction cache, the core can deliver up to 1.45 DMIPS/MHz, but to get the higher performance the gate count would increase to close to 30K gates.

Figure 1: One of the higher-end processor cores from Andes Technology is
the N12. It contains an eight-stage pipeline with dynamic branch prediction, a
memory-management unit and instruction and data caches.

 

The ISA consists of a mix of 16- and 32-bit instructions that execute on the N7, which has a simple two-stage pipelined architecture. On the high-end, the N12 and N13 series implement the ISA on an eight-stage pipeline and pack a memory-management unit, instruction and data caches, and dynamic branch prediction (Figure 1). Programming tools and a good compiler make the proprietary ISA a non-issue and allow designers to program using tools like GCC/Linux. The Hummingbird core is targeted at applications such as Bluetooth, the Internet of Things (IOT)/machine2machine communications, touchscreen controllers, and other embedded applications, the Hummingbird core licensing fees are considerably lower than what ARM charges for its M0 core, thus keeping down the cost of the SoC. The higher-performance cores take on performance-sensitive applications such as embedded Linux systems.

Figure 2: Between the commercial CPUs and a dedicated fixed-function solution is the ASIP (application-specific
instruction-set processor)—a block of customer-defined intellectual property (left). Tools from Target Compiler Technologies allow designers to craft the IP block and incorporate the block in an ASIC, thus enabling the designers t0 significantly improve the power efficiency as well as the performance of their ASIC solution (right).

 

 

Taking a different approach to crafting an embedded processor core, Target Compiler Technologies offers tools that let designers define everything from their own optimized processor cores to a complete multicore application-specific SoC. By allowing designers to craft their own application-specific intellectual property (ASIP) the company’s IP Designer tools allow architectural exploration, SDK generation (C compiler, instruction set simulator, debugger, etc.), and RTL generation. Once the IP blocks are defined, the MP Designer tools for multicore ASIC design perform code parallelization, communication and synchronization and multicore platform generation (Figure 2).

Figure 3: A single-tile xCore processor SoC platform from XMOS can
emulate up to eight “logical” processors and has areas set aside that designers
can use to customize the I/O and bus interface/communications channel. The
platform chips from XMOS can contain 1, 2, or 4 physical processor tiles (up to
32 logical processors) and can clock at up to 500 MHz.

 

Somewhere between a dedicated processor core and a fully-definable multicore platform sits the configurable processor SoC platform developed by XMOS. The company offers a partially-predefined multiple processor platform that contains 1, 2, or 4 processor “tiles”, with each tile able to run up to eight threads (or eight logical processors) and basic support blocks such as SRAM, PLLs, timing (schedulers, timers, clocks), Security (one-time-programmable ROM), and JTAG debug port (Figure 3). The remainder of the platform consists of configurable sections into which designers can drop special IP blocks from the XMOS library or their own their proprietary interface/special function logic IP that connects to the platform’s I/O ports and X-Connect interface channels/links.

Each processor tile can deliver up to 500 MIPS of compute power when running at 500 MHz. Each logical processor (a thread) shares processing resources and memory in the tile, but each logical processor has its own register files and gets a guaranteed slice of the tile processor’s compute power (125 MIPS at 500 MHz). The high performance of the processor tiles allows the xCore to take on many applications in consumer and audio systems, automotive systems, industrial control, and display/imaging systems.

Dave Bursky
Semiconductor Technology Editor

Highly-Integrated Solutions for IEEE 802.11ac Deliver Gigabit Wireless Networks

Wednesday, May 8th, 2013

The demand for higher and higher bandwidths on wireless networks has pushed data rates from a paltry 10 Mbits/s for early wireless networks that employed hardware based on the IEEE 802.11b standard to data rates peaking at 1.3 Gbit/s by leveraging the latest IEEE 802.11ac standard. This recently approved standard leverages advances in silicon integration to pack copious amounts of signal processing, multiple radios to set up multiple-input/multiple-output (MIMO) subsystems that employ as many as four transmit and four receive channels, and still more features. Although there is no relationship to cellular radio standards, many people refer to 11ac systems as 5G wireless since the 11ac standard is basically the fifth major standard for wireless networks (previous “generation” standards started with 802.11b, then 802.11g, followed by 802.11a, and then 802.11n, with each generation offering higher data transfer rates, and with 11a and 11n, moving the operating carrier from the 2.4 GHz band up to the 5 GHz band, with 802.11 devices typically offering dual band capability (2.4/5 GHz)

Although backward compatible with the 802.11a and 11n 5-GHz frequencies, the 802.11ac standard does not have a “legacy” mode to connect with 802.11b, and 11g wireless interfaces. By eliminating the lower frequency radio, designers opened up some area on the chip to add many new features such as beamforming and enhancements to deliver better quality of service (QoS). Additionally, other wireless interfaces have been added by some vendors – Bluetooth and NFC (near-field communication) interfaces have been integrated by a few of the 802.11ac chip suppliers. The QoS on a wireless network has become a key issue since many of the networks now stream extensive amounts of video and audio content, and no one enjoys video or audio content that breaks-up or starts and stops.

The various chip suppliers have each taken different integration approaches for their system-on-a-chip (SoC) solutions, with the differences showing up in the number of MIMO channels, the inclusion of Bluetooth, NFC, and even an FM radio receiver, Currently there are only a handful of chip suppliers – Broadcom, Marvell, Redpine Signals, Qualcomm-Atheros, and Quantenna that provide 802.11ac solutions. Broadcom, for example offers the BMC4335, which it calls a complete single-stream 5G WiFi system. Since this chip includes only one transmit and one receive channel, its maximum data rate is limited to 433.3 Mbits/s.

On the chip designers employed a 40 nm CMOS process and have integrated the media-access controller (MAC), the physical interface (PHY), RF circuits for both 2.4 and 5 GHz operation (legacy compatibility with 802.11a/b/g/n), an FM radio, as well as a Bluetooth radio capable of handling both the 4.0 low-energy protocol as well as the high-speed standard. The chip is platform-agnostic and can be added to any handset, tablet, or other platform. To ensure reliable connectivity and good area coverage, the chip also incorporates advanced beamforming to optimize the antenna radiation pattern, and both low-density parity check (LDPC) and space-time block coding (STBC) to reduce transmission and reception errors.

Building on that basic chip, Broadcom has multiple variants of the circuit that include 2×2 and 3×3 MIMO radios to achieve higher data throughputs. The BCM4360 and BCM43460 have three spatially multiplexed channels and can achieve data rates of up to 1.3 Gbits/s, while the BCM4352 and BCM43526 have two channels and max out their data rates at 866.6 Mbits/s.

Going full-bore with four MIMO channels, the Marvell Avastar 88W8864 delivers a 1.3 Gbit/s peak data rate and leverages both Beamforming and LDPC to ensure signal quality (Figure 1).

Figure 1: Providing a 2×2 MIMO capability that delivers data at rates of up to 866.6
Mbits/s the the Avastar 88W8897 from Marvell includes an NFC interface and
supports the Miracast point-to-point streaming interface for HD video.

Offering a top data rate of 866.6 Mbits/s, the Avastar 88W8897 offers a lower-cost alternative to the 4×4 channel chip. Unlike the Broadcom chips, both the 88W8864 and 88W8897 don’t include the FM radio, but they add an NFC capability and support for point-to-point HD video streaming using the Miracast specification.

Qualcomm-Atheros has 1-, 2- and 3-stream solutions in its VIVE family that deliver data rates ranging from 433.3 Mbits/s to 1.3 Gbits/s. The chips also include a Bluetooth 4.0 low-energy radio that can also operate in a high-speed mode. For tablets, the WCN3680 mobile 802.11ac solution features integrated Bluetooth 4.0 and FM capabilities, while for notebooks the QCA9862 and QCA9860 are 2- and 3-stream, dual-band 802.11ac solutions with integrated Bluetooth 4.0 connectivity. The company has also developed a triband chip in conjunction with Wilocity, the QCA9005, that co-integrates the 60-GHz 802.11ad standard referred to as WiGig. The WiGig interface provides multi-gigabit networking, data syncing, and video and audio streaming, while maintaining its wireless bus extension docking capabilities.

A two-chip solution, the QAC2300 from Quantenna offers a full 4×4 MIMO transceiver that combines both 802.11ac and 802.11n channels. By using both the 802.11ac and 802.11n channels in parallel the chipset can achieve transfer speeds of up to 2 Gbits/s. The two chips consist of a digital baseband with the 4×4 MIMO channels, and an RF chip that supports the 5 GHz 802.11ac standard. Also dividing their solution into two chips, Redpine Signals has crafted both a single-channel and a triple-channel baseband chip, the RS9117 and RS9333, respectively. Both incorporate Bluetooth 4.0 radios and a ZigBee interface (Figure 2).

 

 

Figure 2: Supporting a single channel, the RS9117 from Redpine Signals handles data
transfers of up to 433.3 Mbits/s and can also simultaneously transfer data over
the 802.11n interface, thus increasing the overall data transfer to over 500
Mbits/s.

Complementing the baseband chips are several RF transceiver options – the RS8221, 8331, and 8112. The RS8221 is a CMOS dual-band (2.4 and 5 GHz) RF and power amplifier that supports 1×1 or 2×2 channel configurations, while the RS8331 can handle 1×1, 2×2, or 3×3 MIMO configurations (Figure 3) and the RS8112 has a single-channel output that can simultaneously operate on both the 2.4 and 5 GHz bands.

Figure 3: A triple-channel (3×3 MIMO) dual-band RF front end, the RS8331 from Redpine
Signals, can simultaneously transfer data at 5 GHz for 802.11ac and at 2.4 GHz
for legacy 802.11 compatibility.

For someone who started out using sneaker-net and migrated to each generation of networking interface, that ability to deliver data at gigabit speeds is impressive. And, it won’t stop there. Future process and integration advances will allow yet higher data rates and improved QoS for better media streaming – especially important now that Ultra HD video systems (4K resolution) are already starting to appear.


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