Archive for February, 2013

Advances in IC development take center-stage at ISSCC

Saturday, February 16th, 2013

Are you ready for the annual pilgrimage to San Francisco for the upcoming International Solid State Circuits Conference as it shines its annual spotlight on the latest advances in chip integration and performance? This year’s 60th anniversary program with the theme “60 years of (Em)powering the Future” starts on Sunday, February 17 and runs through Thursday, February 21. The Sunday tutorials span a wide range of subjects, from LNA and Power Amplifier Design, to Energy Harvesting, to Circuit Design using FinFET devices.

Two special-topic sessions – one on Sunday “Batteries not Included – How little is Enough for Real Energy Autonomy?, and one on Monday evening – “Antiques from the Innovation Attic”, promise to provide some interesting discussions. Additional technical forums on Thursday, February 21, cover topics such as Emerging Technologies for Wireline Communications, Scientific Imaging, Frequency Generation and Clock Distribution, and Mixed-Silicon/RF Design and Modeling for Next-Generation CMOS.

One interesting evening session, scheduled for Tuesday, February 19, will examine “High-speed Communications on Four Wheels –What Will be in Your Next Car”. Another evening session on Tuesday will examine “SoC Design That Will Empower Killer Applications in the Year 2020”. Both these sessions promise to raise many interesting issues and challenges regarding future technologies.

Sandwiched between all these tutorials and panel sessions are the over 200 plenary and technical presentations that form the heart of every ISSCC. This year’s sessions cover a wide swath of circuit designs, from high-speed transceivers, to high-performance processors, high-density non-volatile memories, wireless technologies, analog techniques, data-converter approaches, and many other topics.

As in past years, the technical program kicks off with four plenary presentations on Monday morning. Lisa Su, the senior vice president and general manager for AMD discusses “Architecting the Future Through Heterogeneous Computing”, Yoshiyuki Miyabe, the managing director and CTO of Panasonic looks at “Smart Life Solutions, from Home to City”, Martin Van den Brink, the executive vice president and chief product and technology officer at ASML give his views on the “Continuing Shrinkage: Next-Generation Lithography – Progress and Prospects”, and the last plenary, presented by Carver Mead, Professor Emeritus at Caltech University examines “The Evolution of Technology”.

Over the past two decades the trend in transistor integration on a single chip has followed an exponential curve such that the 1 billion transistor integration mark was achieved some years ago, and today popular processor designs now contain more than 2B transistors on a die (see graph). The latest development from IBM Corp. exemplifies that trend. Researchers, in paper 3.1, describe a next-generation multiprocessor design that combines a half-dozen chips, with each chip packing six 5.5-GHz processor cores and a 48-Mbyte on-chip embedded DRAM L3 cache—all integrated on a 598 mm2 die.

Advances in transistor integration since the early 1990s have led to logic chip densities crossing the 1 billion device mark in recent years and processors containing over 2 billion transistors are now shipping. Further integration will push densities to 2.75 billion transistors with IBM’s disclosure of its latest six-core processor with on-chip embedded DRAM. (Graph courtesy of ISSCC.)


Each multicore processor chip contains 2.75 billion transistors and is fabricated using a 32-nm high-k/metal-gate SOI process and 15-levels of metal interconnect. Along with the processor chips, two memory chips—each containing 192 Mbytes of RAM to form an L4 cache—are all mounted on a 102-layer ceramic multichip module to form a 36 core/socket solution that dissipates almost 2 kW.

In the same session, paper 3.4 from AMD focuses on the other end of the system spectrum, presenting details of a four-core x86-compatible modular processing element based on its Jaguar CPU. The quad-core element is fabricated using a 28-nm 11-metal-layer process and occupies just 26.2 mm2. It has a power envelope of less than 0.5 W, is targeted for SoC integration, and can run at clock frequencies of up to 1.85 GHz.

Ultra-low-power processors targeted at mobile applications are the focus in session 9. In paper 9.1, Samsung describes a processor that contains two quad-core CPU clusters, in which one cluster consists of four high-performance CPUs running at 1.8 GHz, while the other cluster consists of lower-performance CPUs that run at 1.2 GHz and consume one-sixth the power of the higher-performance CPU cluster. The system can seamlessly switch back and forth between the two clusters to minimize power consumption. Renesas, in paper 9.2 details a dual core processor targeted at mobile applications that is co-integrated with a LTE/HSPA+ multimode baseband modem, 2D/3D graphics accelerators, and a power-management unit.

Non-volatile memories continue to get denser as highlighted in paper 12.5 from Micron, which details a 128 Gbit, 3-bit/cell NAND flash design using a 20-nm planar cell technology. New non-volatile memory technologies are also making density headway – paper 12.1 details a 32 Gbit resistive RAM developed by Sandisk and Toshiba. Fabricated in a 24 nm process and using diodes as selection devices, the memory keeps the array area very efficient by using the area under the storage array for support circuitry and by sharing the wordlines and bitlines between adjacent blocks. In a novel design researchers at Chuo University in Japan have developed a storage architecture that merges NAND flash memory and Resistive RAM targeted at big-data applications. Detailed in paper 12.9, the combined architecture tolerates a 32X higher BER from the NAND cells by leveraging reverse-mirroring, error-reduction synthesis, page-RAID, and error masking.

There are many more developments in analog, RF, biomedical, imaging, wireless interfaces, and many other topics that are just too numerous to cover in this short column. To view the advance program, please go to and for registration information, send email to

Dave Bursky
Chip Design Magazine

Multicore Processors Deliver PerformanceBoosts For Handheld Platforms

Tuesday, February 5th, 2013

As designers push to improve the performance of smartphones and other portable systems, they are turning more and more to multicore processors to speed the computations, handle more audio and video operations, and provide better connectivity – all while reducing the system power envelope. At this year’s International Consumer Electronics Conference (ICES), several new multicore systems-on-a-chip solutions were unveiled by Nvidia, Qualcomm, and Samsung. These solutions promise to raise the performance bar of handheld systems to new levels by allowing multiple applications to run concurrently, render 3D graphics to support the most complex gaming applications, and deliver real-time response. Let’s take a closer look at what each of the companies has done to deliver the performance needed for next-generation systems.

The highest performance solution from the trio comes from Samsung – the Exynos5 Octa leverages the big.LITTLE concept developed by ARM to craft a system-on-a-chip design that contains eight processor cores plus lots of other system logic in a high-density ball-grid-array package (see the photo). The cores are divided into two clusters – one contains four high-performance A15 ARM processors, while the other cluster consists of four power-efficient ARM Cortex A7 cores. Only one cluster of CPU cores can be active at any time, and the cluster not in use goes to sleep to reduce power consumption. When switching between clusters, there is a 30 to 50 ms switchover delay.

The A7 cores, when in use, reduce power consumption by 3.3X vs the quad A15 cluster, but still give the system enough performance to handle most of the basic housekeeping functions and many applications that don’t require the high performance of the A15 cores. Additionally, the A7 cores are much smaller than the A15 core – all four A7 cores occupy only about half the area as a single A15 cor

This high-density ball-grid array package houses Samsung’s Exynos 5 Octa processor that contains two quad-core clusters – one comprised of four Cortex A-15 high-performance cores and the other containing four low-power second-generation Cortex A7 cores.

e, so the area penalty to add the four A7 cores has minimal impact on the chip area.

Qualcomm has crafted two new multicore additions to its Snapdragon family – the Snapdragon 600 and Snapdragon 800. The top-of-the-line 800 series, fabricated on a 28-nm process, not only has Qualcomm’s latest CPU core, the Krait 400 in a quad-core configuration, but updated versions of the company’s GPU, the Adreno 330, and the Hexagon v5 DSP engine. Furthermore, a 4G LTE Cat 5 modem integrated on the chip allows Snapdragon to connect to the fastest mobile networks. The processor cores can run at clock rates of up to 2.3 GHz, each core is only active when needed, so the entire system is designed to conserve power whenever possible. Additionally, the video support includes the ability to capture and display ultra HD, which delivers four times the pixel density of the standard 1080p display. The chip also supports displays of up to 2560 by 2048 pixels as well as Miracast wireless video streaming at 1080p.

For more conservative system designs, the Snapdragon 600 embeds a quad core Krait 300 CPU cluster that runs at 1.9 GHz, a Adreno 320-series graphics processor, and support for low-power DDR3 memory. Designers also included many other enhancements that allow the chip to deliver about 40% better performance than the previous generation Snapdragon S4 Pro processor at even lower power consumption levels.

Last of trio, NVIDIA unveiled details of the Tegra 4, which integrates four ARM Cortex A15 cores plus a second-generation battery-saver core, similar to the approach used in the Tegra 3 processor. This variable symmetrical multiprocessor architecture developed by NVIDIA allows all four A15 cores to operate simultaneously or power-down when not needed, allowing the lower power battery-saver core to take over for housekeeping and non-performance-critical tasks such as music and video playback. The integrated graphics processor unit (GPU) contains 72 custom cores that help it deliver topnotch gaming performance as well as advanced media and web capabilities, including WebGL and HTML5. Lastly, the Tegra 4 ties into the company’s Icera 450 soft-modem chipset to deliver high-throughput HSPA+ communications with data rates as high as 28 Mbits/s. Additional Icera solutions, the Icera 410 and 400 are also compatible with the Tegra 4.

These multicore processors are just the tip of the proverbial iceberg with regards to the many product developments unveiled at ICES. Future columns will highlight some of the additional developments from CES.

Dave Bursky
Chip Design Magazine

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