Are you ready for the annual pilgrimage to San Francisco for the upcoming International Solid State Circuits Conference as it shines its annual spotlight on the latest advances in chip integration and performance? This year’s 60th anniversary program with the theme “60 years of (Em)powering the Future” starts on Sunday, February 17 and runs through Thursday, February 21. The Sunday tutorials span a wide range of subjects, from LNA and Power Amplifier Design, to Energy Harvesting, to Circuit Design using FinFET devices.
Two special-topic sessions – one on Sunday “Batteries not Included – How little is Enough for Real Energy Autonomy?, and one on Monday evening – “Antiques from the Innovation Attic”, promise to provide some interesting discussions. Additional technical forums on Thursday, February 21, cover topics such as Emerging Technologies for Wireline Communications, Scientific Imaging, Frequency Generation and Clock Distribution, and Mixed-Silicon/RF Design and Modeling for Next-Generation CMOS.
One interesting evening session, scheduled for Tuesday, February 19, will examine “High-speed Communications on Four Wheels –What Will be in Your Next Car”. Another evening session on Tuesday will examine “SoC Design That Will Empower Killer Applications in the Year 2020”. Both these sessions promise to raise many interesting issues and challenges regarding future technologies.
Sandwiched between all these tutorials and panel sessions are the over 200 plenary and technical presentations that form the heart of every ISSCC. This year’s sessions cover a wide swath of circuit designs, from high-speed transceivers, to high-performance processors, high-density non-volatile memories, wireless technologies, analog techniques, data-converter approaches, and many other topics.
As in past years, the technical program kicks off with four plenary presentations on Monday morning. Lisa Su, the senior vice president and general manager for AMD discusses “Architecting the Future Through Heterogeneous Computing”, Yoshiyuki Miyabe, the managing director and CTO of Panasonic looks at “Smart Life Solutions, from Home to City”, Martin Van den Brink, the executive vice president and chief product and technology officer at ASML give his views on the “Continuing Shrinkage: Next-Generation Lithography – Progress and Prospects”, and the last plenary, presented by Carver Mead, Professor Emeritus at Caltech University examines “The Evolution of Technology”.
Over the past two decades the trend in transistor integration on a single chip has followed an exponential curve such that the 1 billion transistor integration mark was achieved some years ago, and today popular processor designs now contain more than 2B transistors on a die (see graph). The latest development from IBM Corp. exemplifies that trend. Researchers, in paper 3.1, describe a next-generation multiprocessor design that combines a half-dozen chips, with each chip packing six 5.5-GHz processor cores and a 48-Mbyte on-chip embedded DRAM L3 cache—all integrated on a 598 mm2 die.
Each multicore processor chip contains 2.75 billion transistors and is fabricated using a 32-nm high-k/metal-gate SOI process and 15-levels of metal interconnect. Along with the processor chips, two memory chips—each containing 192 Mbytes of RAM to form an L4 cache—are all mounted on a 102-layer ceramic multichip module to form a 36 core/socket solution that dissipates almost 2 kW.
In the same session, paper 3.4 from AMD focuses on the other end of the system spectrum, presenting details of a four-core x86-compatible modular processing element based on its Jaguar CPU. The quad-core element is fabricated using a 28-nm 11-metal-layer process and occupies just 26.2 mm2. It has a power envelope of less than 0.5 W, is targeted for SoC integration, and can run at clock frequencies of up to 1.85 GHz.
Ultra-low-power processors targeted at mobile applications are the focus in session 9. In paper 9.1, Samsung describes a processor that contains two quad-core CPU clusters, in which one cluster consists of four high-performance CPUs running at 1.8 GHz, while the other cluster consists of lower-performance CPUs that run at 1.2 GHz and consume one-sixth the power of the higher-performance CPU cluster. The system can seamlessly switch back and forth between the two clusters to minimize power consumption. Renesas, in paper 9.2 details a dual core processor targeted at mobile applications that is co-integrated with a LTE/HSPA+ multimode baseband modem, 2D/3D graphics accelerators, and a power-management unit.
Non-volatile memories continue to get denser as highlighted in paper 12.5 from Micron, which details a 128 Gbit, 3-bit/cell NAND flash design using a 20-nm planar cell technology. New non-volatile memory technologies are also making density headway – paper 12.1 details a 32 Gbit resistive RAM developed by Sandisk and Toshiba. Fabricated in a 24 nm process and using diodes as selection devices, the memory keeps the array area very efficient by using the area under the storage array for support circuitry and by sharing the wordlines and bitlines between adjacent blocks. In a novel design researchers at Chuo University in Japan have developed a storage architecture that merges NAND flash memory and Resistive RAM targeted at big-data applications. Detailed in paper 12.9, the combined architecture tolerates a 32X higher BER from the NAND cells by leveraging reverse-mirroring, error-reduction synthesis, page-RAID, and error masking.
There are many more developments in analog, RF, biomedical, imaging, wireless interfaces, and many other topics that are just too numerous to cover in this short column. To view the advance program, please go to www.isscc.org and for registration information, send email to email@example.com.
Chip Design Magazine