Advances in non-volatile memories seemed to take center stage at this month’s IEEE International Electron Devices Meeting in San Francisco. With many technologists predicting the end of scaling for the NAND-flash memory cell over the next few years, researchers are searching for alternative non-volatile memory cell structures that will be able to scale well below the 14-nm process node. Many different memory technologies are up for consideration–magnetoresistive materials (including spintronic (spin-transfer torque, STT) cells), phase-change materials, carbon nanotubes, and still other materials such as graphene.
The floating-gate cell structure used in most NAND flash memories has evolved to a planar 2-D structure that overcomes many structure and reliability limitations of scaling, and in the future, the cell will evolve to a 3-D structure that maximizes cell size while minimizing the cell area. Such a change will reduce the cell noise and that will let designers realize a tight Vt placement and excellent reliability according to the results presented in a jointly authored paper (2.1) by Intel and Micron. A more exotic solution to improve storage capacity was described by Macronix International in paper 2.3. The approach employs a 3-D cell fabricated using an 8-layer vertical-gate structure and a double-gate thin-film-transistor BE-SONOS charge-trapping storage cell that the company feels could lead to a 1 Terabit memory using a 25-nm half-pitch with only 32 stacked layers. For a traditional vertical channel NAND structure, nearly 100 layers would be required to reach the same memory density.
As NAND flash memories store and erase data, the gate oxide gets damaged and eventually the memory cells wear out. However, by turning the transistor gates into tiny on-chip heaters, researchers at Macronix International can thermally anneal the oxide layer and heal the damaged oxide layer (see the figure).
Detailed in paper 9.1, the scheme allows the NAND cells to deliver a record-setting endurance of greater than 100 million program/erase cycles. To create the heating structure in each cell, designers modified the word line of the memory cell from single-ended to a double-ended structure by adding a second P—/N+ junction so that a current can be passed through the gate to generate Joule heating. Temperatures of over 800 °C can be generated in immediate proximity of the gate to thermally anneal the underlying oxide, thus repairing the damage from repeated program/erase cycles. The memory array area penalty is less than 10%, thus making the approach feasible for commercial use.
Novel materials are also making their way into non-volatile memories—for instance in paper 2.6 Samsung’s Advanced Institute of Technology detailed a switching device for 3-D nanoscale memory arrays that is based on Chalcogenide glasses (AsTeGeSiN). The process developed by Samsung includes a nitrogen plasma treatment that solves an aging degradation issue that was noted in previous Chalcogenide switching elements. Targeting the design of a 3-D crosspoint memory, researchers at IBM detailed the use of a mixed ionic-electronic conduction (MIEC) material for access devices in the array (paper 2.7). Showing the results of experiments with Threshold Vacuum Switch structures in paper 2.8, researchers at the National Applied Research Laboratories, the National Chio-Tung University, Mesoscope Technology, Fu-Jen University, Chung Yuan Christian University, all in Taiwan, and the University of California at Berkeley detailed their development of crosspoint bipolar and unipolar resistive random-access memories that will lead to 3-D stackable crosspoint RRAM applications.
STT-based memories were the focus in session 11, with paper 11.1 presented by researchers from Unite Mixte de Physique detailing the use of graphene as a replacement for conventional semiconductor channel and the implemention of spin transport in the graphene. They view graphene as a good candidate for spin information transport since the material’s mobility at room temperature outperforms that of any other material. Toshiba researchers, in paper 11.3 reviewed the progress in STT-magnetoresistive RAM technology and their work with STT writing on MTJ (magnetic tunnel junction) materials with perpendicular magnetization (P-MJT). Such a combination solves many of the challenges in creating an ideal non-volatile memory by creating a normally-off memory hierarchy.
Resistive RAM technology was the focus in session 20, with multiple presentations detailing the device physics of various memory cell structures. For instance, paper 20.1 from DISMI Universita di Modena e Reggio Emilia detailed the analysis of devices based on hafnium oxide (paper 20.1), while paper 20.2 from the University of Tsukuba analyzed the physics of three-layer ReRAM structures to better implement the memory cell stack structure. Additional papers in the session provided in-depth analysis of various cell structures including a non-linear ReRAM cell with a sub-1 µA operating current described by Samsung in paper 20.8.
There are many other noteworthy memory papers examining phase-change and RRAM cells in session 30, as well as many other sessions detailing advances in device structures, materials, interconnect and many other topics. Copies of the IEDM proceedings can be ordered from the IEEE via email at firstname.lastname@example.org.