About a year ago ARM unveiled its big.LITTLE processor architecture that seamlessly melded a low-power ARM7 processor core with one or more high-performance 32-bit A15 processors. In this approach, software execution could seamlessly switch between the high-performance cores and the low-performance low-power core, depending on the task at hand. This allowed designers to get the high-performance of the A15 cores when compute-intensive tasks were running, and save power when light tasks such as system housekeeping and monitoring functions had to be executed. Although not a radically new concept (Nvidia introduced a similar approach in its Tegra3 series processors that are used in various mobile applications such as tablets.), the ability to smoothly switch execution improves the user experience and helps extend the battery life.
However, system designers are always asking for higher performance, and to meet those demands, at this past October’s ARM Developer Forum held in Santa Clara, Calif., ARM unveiled its second-generation big.LITTLE multicore solution employing cores based on the new ARMv8 architecture. The ARMv8 represents ARM’s venture into 64-bit computing and the first ARM A50 series processor cores—the A53 and A57 – are the first cores to implement the v8 instruction set architecture, AARCH64. Both cores are also fully compatible with the large 32-bit ecosystem that supports previous ARM processor cores. Either core can also be used independently as a stand-alone solution, or combined into a big.LITTLE configuration that delivers high performance with excellent power efficiency. The two processors can seamlessly transition from their 32-bit execution mode to their 64-bit mode, thus providing performance scalability to 64-bit operation in mobile and enterprise computing applications.
The high-performance A57 core’s architecture includes a complex, out-of-order multi-issue pipeline, and can deliver about triple the performance of high-end processors used in today’s “superphones” in its 32-bit mode while maintaining the same power envelope. Designed for use in highly-scalable applications, the A57 core can be used in compute clusters that can range from a single core to beyond 16 cores. The core includes optimized instructions to improve software execution and new instructions to speed up encryption algorithms by close to 10X. Targeting some enterprise applications, the 64-bit support also includes enhanced floating-point performance.
Complementing the A57 core is the Cortex A53, claimed by ARM to be the world’s smallest 64-bit processor. The A53 delivers performance comparable to that of the Cortex A9 but is 40%+ smaller than the A9 when fabricated in the same process. Both the A57 and A53 are supported by the recently released ARM-developed blocks of IP – the CoreLink 400 AMBA 4 next-generation on-chip bus interconnect and the CoreLink 500 cache-coherency management logic.
ARM expects the cores to deliver multi-gigahertz performance when implemented on advanced CMOS and FinFET processes at 20 nm and eventually 14 nm process nodes. The small size of the cores will permit designers to include multiple instances of the cores on a system-on-a-chip solution that can range from a system containing a dual-core A57 block and a quad A53 processor block for a next-generation “superphone”, to an enterprise solution that could pack four quad A57 clusters for a compute server, or four quad A53 clusters for a low-power web server (See the figure).
Products employing the new cores are not expected to debut until 2014, but early licensees including AMD, Broadcom, Calexda, HiSilicon, Samsung, and ST Microelectronics have a jumpstart on product development and could potentially release products in late 2013.
Chip Design Magazine