Archive for September, 2012

High-Speed Storage Interface Reduces System Overhead

Friday, September 28th, 2012

Although solid-state disk drives (SSDs) with SATA interfaces fill part of the performance gap between traditional hard-disk drives (HDDs) and dynamic RAM (DRAM) main memory, the gap continues to grow as DRAM performance improves while native HDD performance has barely improved (see the graph).

Non-volatile storage in the form of solid-state disks fills the performance gap between hard-disk-drives and DRAM-based main memory.

Faster SATA interfaces have upped the data transfer rate to 6 Gbits and beyond for short bursts, but there is an overhead associated with the SATA interface – translating the native drive control and data stream into SATA signals from the drive, and then decoding the SATA signals from the host. This translation overhead also exists on the host side and thus adds significant overhead to the overall data request and transfer operations.

However, by removing the overhead through the use of an enhanced PCIexpress interface that adds only a handful of storage-specific instructions, the new non-volatile memory PCIexpress (NVMe) interface can deliver much higher data rates by using multiple serial PCIe channels. The new interface, NVMe 1.0, developed by an industry consortium of over 80+ members, was first published in early 2011. Prototypes of SSDs that employ the interface were demonstrated at both the Flash Memory Summit and the Intel Developer Forum (IDF), both recently held in Santa Clara and San Francisco, respectively. The storage-related commands added to the PCIe command set include ten administrative commands and three I/O related commands.

At the conferences, Integrated Device Technology demonsrated a NVME enterprise flash memory controller with native support for the PCIe Gen 3 interface. Additionally, IP-Maker and Teledyne LeCroy displayed a NVME demonstration platform that highlighted IP-Maker’s NVMe core intellectual property running in an FPGA and Teledyne LeCroy’s T3-8 analyzer viewing the core’s activities. Some of the other companies demonstrating prototypes and test systems included Agilent Technologies, Cadence Design Systems, Dell, EMC, IBM, Intel, LSI, Micron, NetApp, OCZ Technology, SanDisk, STEC, and Vitident Systems.

The NVMe standard defines a command set optimized for storage and is scalable for the future while avoiding the need to burden the device with legacy support requirements. Existing applications and software infrastructure built upon the SCSI architectural model can be handled by defining a translation document that defines a mapping between SCSI and NVM Express specifications. That will permit a seamless transition to NVM Express by preserving existing software infrastructure investments. This translation may be done as a layer within the NVMe driver.

Currently, the adoption of PCIe SSDs is hindered by the many different implementations and unique drivers provided by each SSD vendor that the SSD OEM customer must validate. Each SSD vendor implements a different subset of features in a different way leading to needless extra qualification effort by the OEM. The NVMe standard eliminates that tower of Babel by defining a common register programming interface, command set, and feature set definition. This permits standard drivers to be written for each operating system and enables interoperability between various SSD vendors, thus shrinking the OEM qualification cycles.

By using the latest Gen 3 version of the PCIe interface, designers can transfer 6 Gbytes/s over an eight-lane channel vs only 6 Gbits/s using the latest SATA standard. Latency is also reduced by several microseconds since the SATA overhead is eliminated and the PCIe interface can directly attach to the host CPU’s chipset. This can also lower system cost and power since no external host-bus adapter is needed. The need for reduced latency is critical – Intel, for example, highlighted an issue that Amazon encounters. For every 100 ms delay it takes a site to load, Amazon loses 1% of their sales. In a comparison between NVMe and SCSI/SAS storage interfaces, Intel claims the older SCSI/SAS interface has a latency of 6 microseconds, while the NVMe interface drops the latency by more than 50% to just 2.8 microseconds.

NVMe is basically a scalable host-controller interface designed for Enterprise and Client systems and leverages the PCI express serial interface. The interface provides an optimized command issue and completion path. It includes support for parallel operation by supporting deep queues – up to 64K commands within an I/O Queue and up to 64K I/O Queues. Additionally, the interface has many Enterprise capabilities like end-to-end data protection (compatible with T10 DIF and DIX standards), enhanced error reporting, and virtualization. An enhanced version, NVMe 1.1, which includes additional features to enhance Enterprise and Client system performance, is expected to be released later this year. For more about NVMe, go to www.nvmexpress.org.

Dave Bursky
Technology Editor
Chip Design Magazine

It’s a “Touchy-Feely” World for Mobile Devices

Saturday, September 1st, 2012

Touch-screen technology has gone from a curiosity at the turn of this century to almost a “check-list” feature that just about every cell phone, tablet, and many other products incorporate as part of their base functionality. To achieve that, silicon suppliers and materials suppliers have been working hard to craft the “ideal” solutions to allow multiple simultaneous finger touches (multitouch), thinner screens by reducing the number of layers needed to implement the touch-sensor grid, and even provide haptic feedback to confirm that the touch-panel “buttons” were pressed. Many of the latest developments in these areas were discussed in early August at the DisplaySearch Emerging Displays conference held in Santa Clara, Calif.

All the presentations at the event were interesting, from the basic overviews of various touch-screen technologies, to forward-looking presentations that discussed emerging and novel touch technologies and new approaches to haptic feedback. Of all the presentations, there were several that I felt provided a glimpse of the future for touch and haptics technology.

One such presentation, “The Future of Multisensing” by Douglas Young, the VP and General Manager of Neonode Inc., projected future integration directions targeting cost reduction and new features. In their vision, Young expects to see the often separate touch-screen controller integrated into the system’s application processor, thus shrinking component count and system cost. The first step in that direction was the creation of a single-chip analog/digital front end, the NN1001, which was developed in cooperation with Texas Instruments. This chip has a high scanning rate (1000 Hz) but ultra-low-power operation (just 10 microamps) so it can remain active even when the application processor is in sleep mode.

Young also expects to see proximity sensing incorporated into systems. Such a sensing scheme would permit touch-less object detection (of up to 30 cm) and the use of near-device gestures while providing a fast response with only a millisecond or so of latency. Also possible with touch-less detection are 3D and plane sensing as shown in Neonode’s concept device (see Figure 1).

Figure 1: Touchless sensing developed by Neonode Inc. allows concepts such as 3D and Plane Sensing to be implemented as this conceptual design illustrates.

Touch-less operation would also eliminate the need for a glass overlay, thus reducing display thickness and weight, as well as allow underwater operation by sealing the equipment into a waterproof case since no direct contact with the display panel is required.

To improve and lower the cost of the touch-screen panels, Dr. Michael Spaid, VP of Product Development at Cambrios discussed the use of silver nanowires as a replacement for the Indium-Tin-oxide (ITO) conductive layer currently used by almost every touchscreen panel. The silver nanowires provide high conductivity (10 to 70 ohms/square depending on the nanowire concentration), are highly transparent, and are a lower-cost alternative to ITO. Additionally, stated Spaid, since the nanowire sheet resistance is lower than that of ITOs, the nanowires can be used in larger-area displays than practical with ITO films.

The multilayer glass sandwich typically used for most mobile backlighted display panels causes a significant amount of light transmission loss and is also subject to the most abuse during the mobile device’s lifetime. To improve the display durability and to reduce the light transmission loss, Dr. Wagulh Ishak, Division Vice President, at Corning Glass, the Corning West Technology Center, detailed Cornings efforts to develop the second generation of its popular Gorilla Glass and to create an ultra-thin glass it calls Willow Glass that offers a 30 to 70% reduction in display module thickness. Both of these activities were highlighted in Dr. Ishak’s presentation “Evolutionary Glass, Revolutionary Displays: Why and How Advanced Glass Matters”. The second-generation Gorilla Glass offers options that allow a 25% increase in damage resistance or up to a 20% decrease in panel thickness, as well as a potential for cost reduction. The glass also offers improved optical and scratch performance.
The Corning Willow Glass combines the benefits of glass with the ability to bend and flex without breaking, thus providing improved durability. The glass is so thin that it can be bent into extremely curved shapes, as demonstrated by the hand holding a flexed sheet of the thin glass (Figure 2).

Figure 2: An ultra-thin but rugged and flexible glass, Willow Glass, developed by Corning, can be bent into various shapes without breaking

Such glass enables companies to build lighter, thinner devices that could also employ new form factors thanks to the flexible glass.
Forming actual buttons on a touch-screen display through the use of electrowetting technology, Dr. Micah Yairi, the Chief Technical Officer at Tactus Technologies presented details of the novel approach to a haptics touch screen in his paper “Dynamic Touchscreens and Surfaces”. Electrowetting uses an applied electric field to move liquid into and out of an expandable pocket in a tactile elastomer layer (Figure 3).

Figure 3: In the Tactus Technology microfluidic keypad, tiny pockets in a tactile layer can be filled with liquid to create buttons. The scheme uses the electrowetting properties of the liquid to draw the liquid into the pockets and send the liquid back to the local reservoirs when the buttons are no longer needed.

The expandable pockets in the tactile layer are positioned over the display regions that indicate a button. When electrowetting draws the liquid from local reservoirs into the pocket, the surface of the pocket rises by 0.25 to 2.5 mm to form a physical button, which provides tactile feedback when pressed.

Dave Bursky
Semiconductor Technology Editor
Chip Design Magazine


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