One common theme that all the research organizations focused on was the need to partner and collaborate earlier in the design cycle — designing the next generation of complex ICs often requires earlier access to process and device models since the design complexity continues to increase for each next-smaller process node. Each new generation of ICs depends on advanced transistor structures, advanced patterning, advanced interconnects, and wafer-level/multichip packaging. The diverse range of technologies covered by these areas requires that designers/companies partner to leverage each organization’s expertise.
In addition to the physical design, low power consumption and high-speed operation are also putting the squeeze on designers to leverage the latest process nodes, transistor structures and circuit design tricks to deliver highly-integrated low-power solutions at ever-decreasing price points. For example, Dr Aaron Thean, director of logic programs at IMEC, sees the general trend as designers move from node to node, of achieving a 25% performance increase, a 20% power reduction, a 50% area reduction, and a 15% cost reduction every two to three years, but with changing application contexts as the end-application drivers change with each generation. Today, the diverse targets include applications such as sensor networks, smart mobile devices, and large data centers employing high-performance servers.
In addition to pushing single-chip integration to the limits, still higher complexities can be achieved by leveraging packing techniques to create a “super chip” that consists of multiple chips stacked one on top of another, interconnected by through-silicon vias and both wired and high-speed optical interconnects on an interposer substrate and entire multichip structure mounted in a high-contact density package such as a ball-grid array (See diagram). To achieve such solutions advanced patterning for ever-smaller structure at 14 nm and beyond will have to leverage extreme ultraviolet lithography with dual- and even triple-patterning to draw the fine features. That will require careful co-optimization of imaging, layout, processes and design.
To keep the power at bay while delivering higher performance, Thean also sees advanced transistor structures based on FinFET devices and fully-depleted silicon-on-insulator substrates at the 20 and 14 nm process nodes. Beyond that, band-engineered channels are expected to deliver higher switching speeds by employing III/V materials and silicon-germanium structures to implement compound devices and quantum well structures in the 10 and 7 nm regimes. However, implementing these complex structures will also require further advances in processing and device design.
Chip Design Magazine