Archive for June, 2012

Notable Analog Tool Advances Boost Designer Productivity

Monday, June 18th, 2012

This year’s Design Automation Conference, recently held in San Francisco, CA, highlighted many advances in analog and digital circuit design tools, but in the analog and mixed-signal world many designers are hesitant to give up tried and true manual design techniques to implement their circuits. They feel analog design is still more of an art than a science and that most of the available tools can’t really come close to what a good analog designer can do. However, after hearing the pitches from several new and existing vendors of analog and mixed-signal design tools at this year’s DAC, I suspect many analog designers will be tempted to adopt some of the new tools to improve their productivity.

Although the major EDA tool suppliers–Cadence, Mentor and Synopsys—all have strong suites of analog and mixed signal design tools, smaller, highly-innovative companies are also crafting both suites of tools that cover the entire design flow, and vertical tools that solve specific problems. For those of you who didn’t make it to this years, DAC, here is a sampling of some of the new tools that support analog design.

Taking a “correct-by-construction” approach to analog IP delivery, newcomer Analog Rails from Chandler, AZ ( offers an automated, parasitic-aware tool that they claim will significantly reduce support costs and schedule creep, and can deliver high-yield analog and mixed signal IP in hours rather than days, weeks, or months. The tools include a synchronized schematic and layout editor that allows designers to capture the complete design intent, including constraints, capacitance, and voltage back-annotation. The Analog Rails tool is also simulator agnostic, and includes the TSMC-approved MSIM simulator, infinite GnuCapplus Licenses, and can easily integrate any HSPICE compatible simulator into the flow.

Another fairly new face at DAC, Symica of San Jose, CA ( offers a suite of EDA tools for analog and mixed-signal IC design – from schematic capture to circuit simulation and layout. The tool suite handles analog, and analog behavioral and digital mixed-mode simulation in a flexible simulation environment. The tools also accept inputs from HSPICE- and Spectre-compatible netlists, and incorporate a powerful waveform viewer and analog-simulation result analyzer. This waveform tool offers all the functions designers expect (viewing results for TRAN, DC, AC, Sweep, Monte Carlo; customizable views of multiple plots; and may other features) and employs a simple-to-use graphical interface. A free version of the tool, Symica FE, allows users to try out most of the features on circuits with fewer than 500 transistors; however the free version does not support mixed-signal and Fast-SPICE simulation.

One of the trickiest aspects of analog circuit design is the placement of the devices and the routing to interconnect them. Taking aim at that aspect of design, Pulsic Inc. of San Jose (, offers a place-and-route solution for analog and custom digital design. The Pulsic Planning Solution builds on the work of last year’s planning tool released by the company, and offers easy-to-use guided flows to automatically implement precise, hand-crafted quality design layouts. The company’s Unity Analog Router delivers DRC-correct routing and completes routing patterns and topologies that an experienced analog designer would create when routing the layout by hand.

Adding analog prototyping to their tool suite, SpringSoft Inc. from Hsinchu, Taiwan ( showed off the Laker Analog Prototyping tool . The tool provides early feedback on the impact of layout parasitic and other layout-dependent effects, which can be particularly challenging to manage at the 20 nm process node. Key features include “smart” placement techniques that automatically generate multiple DRC-correct and routable options, hierarchical structure to handle thousands of transistors, and full support for a complete range of industry-standard parameterized device formatted, including MCells, PyCells, C++ PCells, and Tcl PCells.

Additionally, the tool enables automated constraint generation, layout exploration, and rapid implementation in a single flow. Built into the company’s Laker SDL flow, the analog prototyping tool automates the process of analyzing advanced process effects and generating constraints to guide circuit layout. The company claims that it results in a more-predictable design cycle and improves productivity with less time wasted on post-layout design adjustments when compared to convention design methods.

Another analog floorplanning tool demonstrated by JEDAT (Japan EDA Technologies) of Tokyo, Japan ( enables analog layout designers to automatically build accurate analog floorplans. The software includes constraint extraction and management, layout netlist with tuning from the circuit netlist, and analog block placement. The company claims the tool can deliver a fivefold improvement in layout efficiency while the layouts are high-quality and accurate thanks to multiconstraint-driven flexible layout hierarchy and flexible block boundaries. Additionally, the company has achieved a three to five time improvement in design time, as reported by over ten customers.

Design verification for analog circuits is the goal of the Analog+ suite of tools from Solido Design ( ). The tool provide rapid interactive device sizing with MonteCarlo accuracy, three-sigma statistical corners that truly bound analog performance, and final verification across all corners with a 2 to 10X speedup. Using adaptive machine-learning techniques the Analog+ Suite can complete tasks with fewer simulations compared to the hundreds of thousands of simulations typically required. The Monte Carlo+ tool in the suite is claimed by Solido to be the only EDA tool that can actually extract 3σ statistical corners. The patent-pending algorithm is fast, accurate, and scales up to tens of thousands of devices and beyond.

Dave Bursky
Technology Editor
Chip Design Magazine

The Need For Speed

Wednesday, June 6th, 2012

Today’s SAS and SATA drives transfer data at rates of 6 Gbits/s, but as microprocessor and dynamic RAM subsystems get faster, still higher-speed interfaces will be needed to ensure the memory systems don’t get starved for data. SAS drives that can transfer data at double the rate – 12 Gbits/s – are already being sampled, and there is already some exploratory work looking at a 24 Gbit/s interface. However, just doubling the data rate is not enough – designers need faster interfaces and tiered storage solutions to get the best system-level throughput. Thus, designers have started to show the next-generation storage interface – SCSI Express.

Able to operate at data transfer rates of 13.1 Gbits/s SCSI Express runs the SCSI protocol over a single-lane PCI Express (PCIe) hardware interface (SOP – SCSI over PCIe). Multiple PCIe lanes can also aggregated to achieve still higher data transfer rates (See the diagram). SCSI Express is an industry initiative that leverages the popular PCIe hardware interface and the PCIe architecture queuing interface (PQI) model that the T10 technical committee in the SCSI Trade Association is defining.

At a recent meeting of the SCSI Trade Association in Santa Clara, association members demonstrated the upcoming next-generation storage interface that will leverage PCI Express version 3.0, which will permit data transfers at 13.1 Gbits/s, and drives that support the new 12-Gbit/s serial-attached SCSI interface. Drives from Seagate Technology and Western Digital were demonstrated, as well as an FPGA implementation of prototype storage controller chip from SanDisk, and a protocol analyzer from LeCroy that can do full SCSI Express decoding. And, to support the box-to-box connections, cable vendors demonstrated passive and active copper cables, as well as optical cables.

By combining the SAS-based drives with the robust SCSI protocol and PCIe 3.0 , the SCSI Trade Association has defined a backplane dubbed Express Bay that can accept SATA, SAS, MultiLink SAS and SCSI Express storage devices. The backplane employs a multi-protocol connector that can accept SAS or SCSI Express drives and provide power of up to 25 W for high-performance solid-state drives (SSDs), thus permitting system integrators to craft tiered storage systems that combine hard-disk drives and SSDs to accelerate system performance.

Additionally the combination of the high-speed PCIe interface and 12 Gbit/s serial-attached SCSI on a common backplane system will allow architects to combine the best performance aspects of both storage interfaces to deliver high-performance storage arrays that can feed data to the high-speed computational systems. The 12 Gbit/s SAS interface better utilizes the bandwidth of the PCIe 3.0 bus, and even the older 6 Gbit/s drives can leverage the higher bandwidth of PCIe 3.0 by using a feature known as “Store and Forward” in which the data streams from two slower drives are aggregated to form a 12 Gbit/s data stream.

Dave Bursky
Technology Editor,
Chip Design Magazine

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