In his plenary presentation that opened this year’s International Solid State Circuits Conference, Eli Harari, the now retired CEO and Founder of SanDisk Corp., called flash memory the great disruptor. He bases this view on the fact that the technology has greatly impacted every market that it has entered – In the photography/video industry it has almost entirely replaced film and video tapes, in the music industry it has almost entirely replaced vinyl, cassettes, and even CDs as the preferred media for carrying your tunes, and in the electronic systems market it has replaced almost all hardwired ROM storage in microcontroller systems. And most recently, it is started to impact the hard-disk-drive industry by replacing the electromechanical drives with an all-flash equivalent that runs faster and consumes less power.
The density and performance advances presented in Session 25 at last month’s ISSCC re-enforce the view espoused by Eli – the memories are getting denser and faster as evidenced by presentations that describe a 128 Gbit monolithic device jointly developed by SanDisk and Toshiba (paper 25.8), as well as a pair of 64 Gbit devices—one of them is also a joint development by SanDisk and Toshiba (paper 25.1), and the other from Samsung (paper 25.5).
The highest-capacity flash device to date, the 128 Gbit chip uses a 3-bit-per-cell design (multilevel cell) and 19-nm lithography to achieve the capacity in a chip area just over 170 mm2. In its program mode, the chip can achieve a throughput of 18 Mbytes/s, but during read operations, a toggle mode allows the data transfer rate to hit 400 Mbits/s. The high-density memory array means that the floating-gate (FG) storage cells are packed closer and smaller than ever before and thus the FG-to-FG coupling is at its worst. Smaller memory cells are also vulnerable to more cell-to-cell variations. These factors combine to negatively impact write performance.
Designers addressed the increased FG-to-FG coupling by using an air gap rather than an oxide dielectric between two adjacent word lines (WL) to reduce capacitance between two FGs, resulting in lower FG-to-FG coupling and lower WL capacitance. Additional circuit “tricks” include monitoring the on-chip temperature to stabilize the WL voltage level; the use of multiple voltage pumps, rather than one large high-voltage pump to reduce the area required for the pump; and a quad data-bus multiplex scheme to quickly move the data from the storage array to the I/O pins at 400 Mbits/s.
Flash endurance and reliability are also key issues that designers have to address as the flash storage devices are incorporated into enterprise systems that demand 24/7 operation, and automotive systems where high-speed embedded flash storage is key to next-generation automotive powertrain applications. To address some of these issues, a presentation by researchers from the University of Tokyo focused on techniques to extend the lifetime of flash-based solid state drives (SSDs) and also reduce errors though a new error recovery scheme (paper 25.2).
Focusing on data integrity, a high-performance multi-threaded BCH encoder/decoder developed by KAIST in Korea (paper 25.3) can perform error checks at rates of up to 6.4 Gbits/s, thus eliminating a critical performance bottleneck that often limited the data transfer speed on a SSD’s host interface. And, targeting automotive applications, a presentation by researchers from Infineon and the Technical University of Munich, both in Germany, discussed a new bitline capacitance-cancellation sensing scheme that eliminates bit-line capacitive loading, allowing an embedded flash storage array, fabricated in a 65 nm process to deliver a maximum read throughput of 2.9 Gbytes/s.
Additional papers in the session detailed developments of 4- and 8-Mbit Resistive RAMs (ReRAM) (papers 25.7 and 25.6). The 4 Mbit ReRAM macrocell was a joint development between the National Tsing Hua University and TSMC, both in Taiwan, and can operate from a 0.5 V supply. The 8 Mbit ReRAM developed by Panasonic in Japan is also a macrocell designed for embedding into an SoC and has a read access time of 25 ns and a peak write throughput of 443 Mbytes/s. The ReRAM gets part of its high performance thanks to a new bidirectional diode used as a memory-cell select element to reduce the “sneak” current and a multibit write architecture that achieves fast write operations while suppressing the sneak current.
To get full details on these papers or other presentations from ISSCC, go to www.isscc.org and click on “Shop ISSCC” to order a print or DVD version of the conference presentations, tutorials, or short courses.
Semiconductor Technology Editor
Chip Design Magazine