Archive for February, 2012

The State of Solid State

Thursday, February 16th, 2012

The annual International Solid-State Circuits Conference is just around the corner and it promises to be one of the best iterations of the conference to date. Four plenary talks set the tone of the conference on Monday, February 20 – Eli Harari, the cofounder of SanDisk will examine how flash memory has disrupted the industry, Carmelo Papa, a senior executive at ST Microelectronics will discuss the role of semiconductors in the energy landscape, Yoichi Yano, an executive vice president at Renesas Electronics will discuss approaches to designing greener systems, and David Perlmutter, an executive vice president at Intel will examine sustainability in silicon and how it affects system development.

Following these plenary talks, the conference jumps into high gear with sessions over the next 2-1/2 days describing the latest developments in memories, processors, RF subsystems, audio and power converters, sensors and MEMS, wireless transceivers, image sensors, multimedia and communication SoCs, multi-gigabit transceivers, data converters, and many other subjects. Some of the highlights from a few sessions include details of the first DDR4 DRAMs from Samsung and Hynix in Session 2, with Samsung taking the density crown with a 4 Gbit chip with dual-error detection that was fabricated on a 30 nm process node, and the first multi-core processor with graphics processing unit fabricated with 22 nm tri-gate transistors will be unveiled by Intel in Session 3.

In Session 25, both SanDisk and Samsung will detail 64-Gbit multi-level flash memories , both fabricated with sub-20-nm features. However a joint paper by SanDisk and Toshiba takes the density crown in this session with a 128 Gbit, 3-bit-per-cell NAND flash memory that has an 18 Mbyte/s write speed and a 400 Mbit/s toggle mode. Sessions 7, 19, and 24 focus on high-speed transceivers and other high-speed I/O techniques. The top speed serial link receiver in Session 7, weighing in at 19 Gbits/s, will be described by IBM. The circuit, implemented in a 45 nm SOI CMOS process includes both 4-tap FFE and 5-tap DFE functions. In Session 19, the design of 28 Gbit/s serial link transceivers will be detailed by both IBM and Inphi, while ClariPhy and the National University of Cordoba collaborated to develop a 50 Gbit/s transceiver, and Broadcom will detail a dual 23 Gbit/s CMOS transmitter/receiver chip set for 40 Gbit/s RZ-DQPSK and CS-RZ-DQPSK optical transmission. Presentations in Session 24 focus on 10-Gbit Ethernet and optical front-ends, with a 16-port 10GBase-T transmitter and Hybrid discussed by Aquantia, and a 25 Gbit/s, 3.6 picojoule/bit VCSEL-based optical link detailed by IBM.

This short blog barely scratches the surface of all the outstanding developments that will be presented at the conference. For full program information go to The conference is located at the San Francisco Marriott Marquis Hotel and includes tutorials on Sunday, February 19, papers and evening panel sessions on February 20-22, and multiple design forums and short course on February 23.

Dave Bursky

Technology Editor

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