Archive for September, 2011

Advanced Processes Provide Benefits as well as Challenges

Wednesday, September 21st, 2011

At its recent Global Technology Conference, Global Foundries unveiled the roadmap for advancing its process technologies from the current 28-nm process node to future 20-nm features and still-smaller dimensions. As other companies have also acknowledged, the challenges—both in processing and device structures—are formidable. To serve the current and emerging markets, Gregg Bartlett, the company’s senior vice president of technology and R&D, has mapped out a strategy that breaks the target markets into three categories. Each category has a set of characteristics that line up with various process options.

The basic divisions outlined by Bartlett consist of the High-Performance Computing (HPC) market; the Wired Applications and Networking segment; and the Wireless, Mobile, and Consumer market. In the HPC sector, for instance, the company currently offers its 32-nm super-high-performance (SHP) high-k metal-gate process (HKMG) and a 28-nm HP process. Coming in 2012 will be an SHP version of its 28-nm process. By 2014, Bartlett expects Global Foundries to offer a 20-nm SHP process node.

In the Wired Applications and Network sector, the company has just started to offer a 28-nm, high-performance-plus process option. In 2013, it expects to have a 20-nm, low-power process that will be its workhorse across multiple market segments—from portable devices to high-performance computing. Slightly further down the road, Bartlett expects a higher-performance option to the 20-nm process that will meet the needs of the most demanding digital systems.

The forthcoming 20-nm node will allow designers to double the gate density of chips that were previously fabricated on the 28-nm process node. At the same time, it will deliver a 35% performance improvement. Interestingly, the company is bucking the trend to switch to a gate-first process flow. It has determined that its production-proven, gate-last HKMG process would be better, as the density and scaling benefits of the gate-first HKMG no longer apply due to lithographic restrictions.

Looking beyond the 20-nm process node, the company has its sights set on the 16/14-nm node. At that node, however, the game changes. Non-planar transistor structures, such as the Fin-FET, will be required to reduce device leakage by providing better turn-off characteristics. In the process flow, immersion or double-patterning lithography will give way to extreme-ultraviolet (EUV) lithography, which hopefully will be ready for production use by the time the 16/14-nm process is locked in.

Dave Bursky
Consultant
PRN Engineering Services


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