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Next-generation Snapdragon processors take center stage at Qualcomm’s Tech Summit

By Dave Bursky,  Semiconductor Technology Editor Putting the “snap” into its Snapdragon family of processors, Qualcomm Corp. is hosting its annual Snapdragon Tech Summit in Maui , Hawaii on December 4, 5, and 6. At the summit company executives and partners will detail new processors and supporting technologies as well as sample applications employing its [...]

5G Systems Gain Compact MM-Wave Front Ends

By Dave Bursky, Semiconductor Technology Editor The use of mm-wave frequencies for 5G radios in cellular handsets and other mobile devices brings the benefit of high-bandwidth multi-Gbit data transfers. However, the high mm-wave frequencies present many design challenges due to the propagation characteristics of mm-wave signals at frequencies of 26 GHz and higher. When used [...]

High-Performance Graphics, CPUs, FPGA Systems and More at the Hot Chips Conference

Although the weather in northern California has cooled down in mid-August, the upcoming Hot Chips Conference, held at the Flint Center at DeAnza College in Cupertino, Calif., Aug. 20-22, promises to heat things up. Presentations will cover the latest high-performance graphics engines, compute engines, field-programmable gate array accelerators, and other application processors, including one presentation [...]

Transitioning the Internet of Things to the Internet of Everything

By Dave Bursky, Semiconductor Technology Editor, Chip Design Voice biometrics to ubiquitous connectivity, this year’s IoT smorgasbord covered a lot of ground. The huge growth predicted for the Internet of things (IoT) so that every electronic device will be interconnected can only happen if the system and device suppliers can overcome the many challenges and [...]

EDA Community Honors Lucio Lanza with Phil Kaufman Award

Over the many years I have spent as an editor, there are a few people that stand out for their creativity and impact on the semiconductor industry. One such person, Dr. Lucio Lanza, more than qualifies as one of those standouts. He was just honored by the Electronic Design Automation community with the 2014 Phil [...]

Server system-on-chips pack up to 48 64-bit ARM cores

Targeting secure cloud servers, storage servers, compute servers, and data-plane applications, the ThunderX series of multicore SoCs deliver power-efficient computing solutions Dave Bursky Semiconductor Technology Editor Multicore processors based on x86 cores are a very common choice for servers and for handling packets in data-networking applications. Although x86-based servers command most of the IT market, [...]

Interesting product developments at DAC

Dave Bursky Many interesting IP and design verification announcements were one of the key topics running through this year’s Design Automation Conference. Several IP announcements from CAST Inc., for example, offer solutions in video decoding, graphics acceleration, and image decoding. Although developed by the Fraunhofer Henrich Hertz Institute, a H.265 HVEC decoder core is now [...]

From 3-D transistors to 2.5D or 3D systems

From the ultra-small 3D transistors described in papers at this month’s International Electron Devices Meeting (IEDM) in Washington, D.C., to the 2.5D and 3D multichip structures described at the 3D Architectures for Semiconductor Integration and Packaging (ASIP) conference held in Burlingame, Calif., designers are finding more ways to pack more transistors on a chip and [...]

Advances in CPUs, System Architecture, Heat Up the Performance Race at Hot Chips

Celebrating its 25th year, the annual Hot Chips Conference held at Stanford University last month lived up to its reputation for highlighting high-performance processor solutions as well as advances in low-power designs for mobile applications. One of the highest performance processors unveiled at the conference was the Power 8 – the next generation Power series [...]

Advances in DRAM and non-volatile memories keep upping system performance

In the drive to improve system performance, faster processors often end up spotlighting system bottlenecks, especially in the memory subsystem. To reduce those bottlenecks, designers are developing faster-accessing memories, faster interfaces with reduced overheads, and even new memory architectures and technologies. At this month’s MemCon conference in Santa Clara, Calif., presentations highlighted many of the [...]

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