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How can the Chip Community Improve the Industry for IOT Designers?

Monday, March 13th, 2017

Meeting the 20 billion IOT devices prediction by 2020 will require the semiconductor industry to streamline its processes for up and coming chip designers.

By John Blyler, Editorial Director, IOT Embedded Systems

Part I of this article covered the difficulties in designing System-on-Chip (SOC) devices for the Internet-of-Things (IOT) market, as explained by Jim Bruister, CEO of SOC Solutions, during his talk at the inaugural REUSE event. In Part II, we will examine ways for the semiconductor and electronics industries to improve the development process for the next generation of IOT designers. — JB

Quotable  Quotes:

  • … the semiconductor community needs to market outside of its traditional channels, for example, to the “Field and Stream” or perhaps the “Sports Illustrated” communities.”
  • … licensing agreements represent a real problem for buyers especially those that must buy IP from multiple vendors.
  • … a general contractor type of person is needed for the emerging IOT design industry.
  • … (could) open source be used to get IOT designers started especially with FPGAs? 

How, then, do we improve as an industry to ensure success for IOT chip designers? Bruister believes there are 5 pieces that need to be in place. First among those is a proactive ecosystem, one that consists of more than just a few companies getting together and sharing their names on websites.

Secondly, the ecosystem must consist of IP providers, design houses and even the foundries whose goal is to offer real SOC reference designs for the IOT community.

Information marketing focused on the IoT business channels is the third needed item. Bruister emphasized that the semiconductor community needs to market outside of its traditional channels, for example, to the “Field and Stream” or perhaps the “Sports Illustrated” communities. The semiconductor world needs to reach out to those places where the next generation of SOC designers will live.

Fourthly, a general contractor type of position is needed in the IOT SOC ecosystem. By analogy, a general contractor is the person that helps you build a house. The general contractor has the experience and connections to bring in and coordinate the activities of the framer, electrician, plumber and others needed to build a house. The same type of person is need for IOT designers.

At this point in the presentation, an attendee from the audience noted the general contractor should probably own all of the tools for the “building of a house” analogy to work. Bruister looked at the problem differently, explaining that the general contractor for a house doesn’t typically own all the tools.

“I see the general contractor (for IOT design) more like a consultant that selects the design house and helps you pick the IP,” explained Bruister. There are design houses that play that role, but it’s not a smooth flow of activities from start to finish for doing an IOT design. That’s where I think a general contractor or coordinator could help.”

The last thing needed for improvement in the IOT design process was one stop shopping with a common licensing model. Today, there is no standard licensing model and there will probably never be one, said Bruister. But the licensing agreements represent a real problem for buyers especially those that must buy IP from multiple vendors. Current models take way too long to license the IP, get it in-house and evaluate the IP. There needs to be a consolidation on how IP is licensed. Bruister suggested a boiler plate IP license that could contain 90% of the common elements required in a license.

Bruister concluded by saying that the semiconductor industry needs to figure out a way to simplify the whole IOT design process. This statement prompted a question about the use of open source tools and IP as a possible solution. The questioner noted that open source could be used to get IOT designers started especially with FPGAs.

Bruister wondered if there were enough open source folks that would significantly help with the 20 billion predicted IOT devices by 2020. Nikos Zervas, CEO of CAST, who was in the audience, noted that relying on open source may be problematic with the millions of dollars involved in chip design. He question who would stand behind the open source tools in such a case.

But the questioner was persistent, saying that even major chip IP providers like ARM don’t pay for the blunders of the chip designer. He cited software as another example were nothing is really warranted, in his opinion.

Bruister tried to address the question by looking at the big picture. For the coming IOT design challenges, there will be one camp of providers who believe that one hundred different designs types will be good for all devices. The opposing camp will believe that each design situation will require some customization, e.g., to include energy harvesting capabilities, etc. Both groups will be large and vocal. The IOT device market will be so big that it will have lots variability.

“But the common thread is that it takes way too long to design IOT devices,” said Bruister. “There is no way we can reach that many devices with such a long design and long IP licensing processes. Expensive tools are always going to be an issue. I don’t think you can get away from that unless the big EDA vendors decide to go with a “pay as you design” model. They have resisted that for years.”

It may be difficult to simplify the process for less SOC experienced IOT designers, but we must try if the IOT market is to realize it’s potential.

Why is Chip Design for IOT so Hard?

Tuesday, February 28th, 2017

Internet-of-Things (IOT) designers face a different set of challenges from their traditional ASIC and SOC brethren. Will the market be ready?

By John Blyler, Editorial Director, IOT Embedded Systems

Quotable Quotes:

  • … we’ll need 10,000 plus IOT designers. Where will they come from?
  • …a majority of IOT designers will have little experienced in traditional SOC design.
  • … SOC industry newcomers will suffer from “new IOT designer anxiety disorder or “New IDeA Disorder”
  • … need modular architectures that are specific to IOT devices.

It’s a daunting task for a non-experienced company to create a custom chip, ASIC or SOC to implement their new “bright idea” IoT product. The company’s engineers face equal challenges in developing, manufacturing, and getting the chip delivered on time. With this introduction, Jim Bruister, President of SoC Solutions, began his talk at the inaugural REUSE show about the overwhelming number of tools, skill sets, costs, IP acquisition and industry associations needed to navigate the chip design and delivery process. He examined how the industry presently supports new chip development and where it needs to go in the future to streamline the process for the non-experienced companies that will no doubt fuel the coming IoT boom.

Bruister started his talk by considering the drivers of IOT in a market predicted to include 20 billion devices by the year 2020. On the business side, IOT will be driven by data and subscription models. But while IOT devices will be enablers for data businesses, the devices won’t be the real money makers. Instead, revenues will flow from data and related analysis. Most of the IOT devices will compete under strong price pressures resulting in cheaper products with tight profit margins.

Further challenging the revenues from physical IOT devices will be the lack of high-end users. For example, many IOT devices will not be fashionable wearables for fitness as most of the world’s population are struggling with basic needs such as indoor plumbing. They have neither the money nor interest in wearable devices. Still, IOT technology will represent a huge electronic market.

“There will be tens of thousands of new IOT businesses in my opinion,” explained Bruister. “This implies at least as many IOT device designers will be needed, or about 10,000 plus. Where will these designers come from?”

It’s reasonable to assume that IOT designers will come from existing system, software, field programmable gate array (FPGA), Printed Circuit Board (PCB) and semiconductor industries. A larger portion will probably come from the FPGA markets while a much smaller amount will come from the semiconductor space.

A majority of IOT companies will be startups, incubated from universities. Naturally, companies will recruit college graduates and interns to do a lot of the work. This means that a majority of designers will have little experienced in traditional SOC design.

“What is the likely approach that these college graduates will take to IOT design,” asked Bruister? His view was that these designers would first turn to Google searches on terms like SOC, chip or ASIC. They will look in trade magazines like EETimes, EDN, Sports Illustrated, Field & Stream and others. They will probably look for SOC experts and semiconductor consultants but there won’t be enough of such gurus to go around.

IP portals like Chipestimate.com, Design & Reuse (D&R) and others will be consulted only if the college graduate IOT designers know about them. Similarly, these designers might even contact a few design houses if they are aware of them.

One of the big challenges will be the difficulty in maneuvering a typical SOC flow with its many critical steps (see Figure 1). Also, there are over 1,200 IP cores from over 400 IP vendors from which the IOT designer must choose, (see Figure 2). He or she will quickly realize that the front-end design tools are quite expensive, e.g., for synthesis, timing, etc. The back-end tools for place and route and packaging are even more expensive and require tools experts just to run them.

Figure 1: Vendor complexity and cost that IOT designers will face for their SOCs. (Courtesy SOC Solutions)

 

Figure 2: Snapshot of current semiconductor IP vendors.

The challenges of SOC design complexity, numerous IP vendors, varying licensing agreements and expensive front-end and back-end tools will result in a “new IOT designer anxiety disorder or “New IDeA Disorder,” Bruister noted humorously. The IOT designer will be overwhelmed with too much information (TMI). Where can the designer get help?

Bruister believes that practical education is an important missing piece of the IOT design puzzle. The new inductee will need many “How do” guides, e.g., an IOT SOC Design for Dummies book. He or she will need a better place to find information than performing a Google search. Unfortunately, there are just not enough SOC consultants to go around for the 10,000+ designers that will be needed for devices to go into 20 billion products. Instead, IOT designers will need an easy, fast inexpensive way to design a chip from concept to first silicon. This process will require both easy-to-use development platforms and many reference designs to get things started.

Let’s consider a typical SOC architecture containing a CPU, bus structure, peripherals, and interfaces for radios, baseband processing and sensors (see Figure 3). This architecture probably represents about 80% to 90% of those to be used in most small IOT devices.

What is the 10%-20% difference between the different IOT devices? The type of communication to be used will be one difference, for example, Bluetooth, Wi-Fi, proprietary radios or optical methods. Also, IOT devices will probably have different types of sensors such as accelerometers, MEMs, strain gauges, etc. But Bruister believes that the most important differentiator may lie with the power management unit. IOT devices will have a wide range of power duty cycles requiring the devices to turn on every millisecond, minute, hour or even day and then go back to sleep. Thus, power management will have to be customized for each different type of operational requirement.

Figure 3: A typical System-on-Chip (SOC) architecture. (Courtesy SOC Solutions)

All of these challenges mean that the bar on design abstraction must be raised. Modular architectures will need to be specific to IOT devices. This may result in class libraries for hardware.

“I think we need to raise the bar on design abstraction, noted Bruister. “We need modular architectures that are specific to IOT devices. And we need what I call a set of class libraries for hardware for both analog and digital subsystems. These subsystems will be abstracted away to make it easier for IOT designers to plug play amongst these different models. Also, there will need to be complementary software abstractions, e.g., APIs, HAL layers and such. Design abstractions are common in Arduino and Raspberry Pi platforms.”

The good news is that many of the pieces to create a successful IOT ecosystem are in place. There is a large selection of quality IP suppliers, many of which attended REUSE 2016. Complementing the IP vendors are a number of design houses with a lot of good experience and solutions, noted Bruister. Silicon aggregators like eSilicon and the foundries necessary to actually build the 20 billion IOT devices round out the existing ecosystem.

Part II of this article will examine ways for the semiconductor and electronics industries to improve the design process for the next generation of IOT designers.

Has The Time Come for SOC Embedded FPGAs?

Tuesday, August 30th, 2016

Shrinking technology nodes at lower product costs plus the rise of compute-intensive IOT applications help Menta’s e-FPGA outlook.

By John Blyler, IP Systems

 

The following are edited portions of my video interview the Design Automation Conference (DAC) 2016 with Menta’s business development director, Yoan Dupret. – JB

John Blyler's interview with Yoan Dupret from Menta

Blyler: You’re technology enables designers to include an FPGA almost anywhere on a System-on-Chip (SOC). How is your approach unique from others that purport to do the same thing?

Dupret: Our technology enables placement of an Field Programmable Gate Array (FPGA) onto a silicon ASIC, which is why we call it an embedded FPGA (e-FPGA). How are we different from others? First, let me explain why others have failed in the past while we are succeeding now.

In the past, the time just wasn’t right. Further, the cost of developing the SOC was still too high. Today, all of those challenges are changing. This has been confirmed by our customers and from GSA studies that explain the importance of having some programmable logic inside an ASIC.

Now, the time is right. We have spent the last few years focusing on research and development (R&D) to strengthen our tools, architectures and to build out competencies. Toolwise, we have a more robust and easier to use GUI and our architecture has gone through several changes from the first generation.

Our approach uses standard cell-based ASICs so we are not disruptive to the EDA too flow of our customers. Our hard IP just plugs into the regular chip design flow using all of the classical techniques for CMOS design. Naturally, we support testing with standard scan chain tests and impressive test coverage. We believe our FPGA performance is better than the competitions in terms of numbers of lookup tables per of area, of frequencies, and low power consumption.

Blyler:  Are you targeting a specific area for these embedded FPGAs, e.g., IOT?

Dupret: IOT is one of the markets we are looking at but it is not the only one. Why? That’s because the embedded FPGA fabric can actually go anywhere you have RTL, which is intensively parallel programming based (see Figure 1). For example, we are working on a cryptographic algorithms inside the e-FPGA for IOT applications. We have tractions on the filters for digital radios (IIR and FLIR filters), which is another IOT application. Further, we have customers in the industrial and automotive audio and image processing space

Figure 1: SOC architecture with e-FPGA core, which is programmed after the tape-out. (Courtesy of Menta)

Do you remember when Intel bought Altera, a large FPGA company? This acquisition was, in part, for Intel’s High Performance Computing (HPC) applications. Now they have several big FPGAs from Altera just next to very high frequency processing cores. But there is another way to do achieve this level of HPC. For example, a design could consists of a very big parallel intensive HPC architecture with a lot of lower frequency CPUs and next to each of these CPUs you could have an e-FPGa.

Blyler: At DAC this year, there are a number of companies from France. Is there something going on there? Will it become the next Silicon Valley?

Dupret: Yes, that is true. There are quite some companies doing EDA. Others are doing IP, some of which are well known. For example, Dolphin, is based in Grenoble and it is also part of the ecosystem there.

Blyler: That’s great to see. Thank you, Yoan.

To learn more about Menta’s latest technology: “Menta Delivers Industry’s Highest Performing Embedded Programmable Logic IP for SoCs.”

Autonomous Car Patches, SoC Rebirth, IP IoT Platforms and Systems Engineering

Wednesday, December 9th, 2015

Highlights include autonomous car technology, patches, IoT Platforms, SoC hardware revitalization, IP trends and a new edition of a systems engineering classic.

By John Blyler, Editorial Director, IP and IoT Systems

In this month’s travelogue, publisher John Blyler talks with Chipestimate.TV director Sean O’Kane about the recent Renesas DevCon and trends in software security patches, hardware-software platforms, small to medium businesses creating System-on-Chips, intellectual property (IP) in the Internet-of-Things (IoT) and systems engineering management. Please note that what follows is not a verbatim transcription of the interview. Instead, it has been edited and expanded for readability. I hope you find it informative. Cheers — JB

 

ChipEstimate.TV — John Blyler Travelogue, November 2015

Read the transcribed, complete post on the “IP Insider” blog.

 

 

STMicroelectronics Pushes SOI While Leaving the Mobile Space

Thursday, December 20th, 2012

Why is one of Europe’s leading semiconductor IDMs pushing into leading-edge, 28-nm FD-SOI technology while leaving a market where such technology might be useful?

It was a chance meeting that made me wonder about two recent announcements from one of the world’s largest semiconductor companies.

Last week, I attended an IEDM briefing in which STMicroelectronics presented silicon-verified data to further confirm the manufacturability of its 28-nm Fully Depleted Silicon-on-Insulator (FD-SOI) technology (see “FinFETs or FD-SOI?“). Ed Sperling, Editor-in-Chief for SemiMD, summed it up this way:

“What’s particularly attractive about FD-SOI is that it can be implemented at the 28-nm node for a boost in performance and a reduction in power. The mainstream process node right now is 40 nm. And while Intel introduced its version of a finFET transistor called Tri-Gate at 22 nm, TSMC and GlobalFoundries plan to introduce it at the next node—whether that’s 16 nm or 14 nm. That leaves companies facing a big decision about whether to move all the way to 16/14 nm to reap the lower leakage of finFETs, whether to move to 20 nm on bulk, or whether to stay longer at 28 nm with FD-SOI.”

Joel Hartmann, Executive VP Front-End Manufacturing & Process R&D, STMicroelectronics, presents SoC-level, 28-nm Planar Fully Depleted silicon results at IEDM 2012.

I didn’t realize until later that week, but – on the same day as its 28-nm FD-SOI technology announcement – STMicroelectronics stated that it would curtail its presence in the mobile-handset space via the Ericsson partnership. As Chris Ciufo noted in his “All Things Embedded” blog, Ericsson will remain in only two market domains: Sense and Power and Automotive as well as Embedded Processing. “For the former, device categories include MEMS, sensors, power discretes, advanced analog, automotive powertrain, automotive safety (such as Advanced Driver Assistance Systems [ADASs]), automotive body, and the red-hot In-Vehicle Infotainment (IVI) category,” wrote Ciufo.

In the embedded processing market, the company will “focus on the core of the electronics systems” and ditch wireless broadband. Target areas include microcontrollers, imaging, digital consumer, application processors, and digital ASICs.

Considered together, these two announcements beg the following question: If STMicroelectronics is only interested in the sensor, automotive, and “embedded” markets, why does the company need to work at leading-edge process nodes – like 28 nm on FD-SOI? This question arose during a recent chance meeting with Juergen Jaeger, Sr. Product Manager at Cadence Design Systems.

Jaeger suggested a possible answer by noting that Moore’s Law generally provides a cost savings with power and performance benefits at lower processing nodes. “This makes sense for both automotive infotainment and networking technologies,” explained Juergen. “But it doesn’t make too much sense for gearbox, engine, anti-lock brakes, or steering systems, since they need high reliability and tolerance.” Those requirements tend to restrict devices to fully tested, high-node geometries.

Jaeger reminded me that infotainment systems-on-a-chip (SoCs) are very complex devices requiring integrated network and wireless systems – in addition to an array of audio/video codecs that must drive multiple LCD screens within today’s cars.

Additionally, STMicroelectronics’ move to FD-SOI is one way to mitigate the risk facing leading-edge bulk CMOS processes. As Sperling observed, “At 28 nm and beyond, however, bulk has run out of steam, which is why Intel has opted for finFETs.” Meanwhile, FD-SOI offers power and performance benefits while staying on today’s planar-transistor manufacturing processes.

In the end, the push toward FD-SOI technology at exiting 28-nm nodes may play well into a number of low-power and high-performance chip markets. This is not a path without risk. But it does highlight the accelerating convergence of SOI and bulk CMOS at leading-edge nodes. And it should strengthen STMicroelectronics’ strong position in the automotive infotainment space.

Originally posted on “IP Insider.”

SoC Costs Cut by Multi-Platform Design

Friday, June 1st, 2012

Upward SoC cost trend blunted as designers reused software, verified IP and fewer blocks, reports long-time EDA analyst Gary Smith.

During last year’s Design Automation Conference (DAC), EDA-veteran analyst Gary Smith predicted that it cost slightly over $75 million to design the average high-end System-on-Chip (SoC). This was way over the $50 million targeted by IDM-fabless companies and even further from the $25 million start-up level preferred by funding institutions.

Shortly after that prediction, several companies reported building SoCs around the $40million level. How did they beat the expectation? First, they used previously developed software. Second they used IP that came with verification suites. Lastly, these companies significantly decreased the number of SoC blocks – below the preferred five core blocks. Taken together, these three factors constituted a methodology nicknamed the Multi-Platform Based Design approach.

In essence, this approach was based on the integration of existing platforms enhanced with a new application level to add competitive advantage. The greatest cost savings was realized from the reduction of new core designs.

The multi-platform based design platform has three levels: functional, foundation and application. The functional level represents the core of the SoC design, the broadest of the three platforms. Typically, it often comes from a third party, e.g., ARM Cortex A9 processing system, that is not geared to specific industry or product. If it comes from an in-house design, then it consists of all reused cores. This level provides no competitive advantage since it uses third party cores or IP.

The Foundation platform, also usually from a third party vendor, provides only a slight industry or market differentiation. Most foundation cores are focused on the mobile and consumer electronic markets, e.g., Nvidia’sTegra 3, TI’s OMAP and Qualcomm’s Snapdragon platforms. While enabling differentiation for a particular market segment – often the mobile or consumer electronic markets – foundation cores still provide only a small competitive advantage. Together, the functional and foundation platforms make up between 75 to 90 percent of the total gates in the SoC design.

At the top of the multi-platform based design is the application level, which provides the most market differentiation. This level consists of in-house or proprietary designs, e.g. IP or software from car-maker Audi’s navigation and infotainment systems. The drawback is that this level has the shortest product life cycle.

Applications that are popular can move from the application-level to the foundation level, as in the case of GPS and GPU SoCs. Foundation suppliers then begin to include these popular IPs in their regular offerings. If the application involves processing – like a GPU – then it may even evolve into the functional-level.

Those companies that create a popular application offering have a sustainable advantage, which becomes very hard for competitors to surpass. Smith cited the example of the PC- market. IBM developed the original PC, but within a decade Intel had taken over the market thanks to their platform approach. Now, as the processing has shifted to low-power mobile devices, Intel’s platform has been surpassed by ARMs.

Smith suggested that the good news for DAC is that the platform companies will find a welcomed business for their IP in the evolving system-level EDA market.