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Posts Tagged ‘simulation’

Increasing Power Density of Electric Motors Challenges IGBT Makers

Tuesday, August 23rd, 2016

Mentor Graphics answers questions about failure modes and simulation-testing for IGBT and MOSFET power electronics in electronic and hybrid-electronic vehicles (EV/HEV).

By John Blyler, Editorial Director

Most news about electric and hybrid vehicles (EV/HEV) electronics focuses on the processor-based engine control and the passenger infotainment systems.  Of equal importance is the power electronics that support and control the actual vehicle motors. On-road EVs and HEVs operate on either AC induction or permanent magnet (PM) motors. These high-torque motors must operate over a wide range of temperatures and in often electrically noisy environments. The motors are driven by converters that generally contain a main IGBT or power MOSFET inverter.

The constant power cycling that occurs during the operation of the vehicle significantly affects the reliability of these inverters. Design and reliability engineers must simulate and test the power electronics for thermal reliability and lifecycle performance.

To understand more about the causes of inverter failures and the test that reveal these failures, I presented the following questions to Andras Vass-Varnai, Senior Product Manager for the MicReD Power Tester 600A , Mentor Graphic’s Mechanical Analysis Division. What follows is a portion of his responses. – JB

 

Blyler: What are some of the root causes of failures for power devices in EV/HEV devices today, namely, for insulated gate bipolar transistors (IGBTs), MOSFETs, transistors, and chargers?

Vass-Varnai: As the chip and module sizes of power devices show a shrinking tendency, while the required power dissipation stays the same or even increases, the power density in power devices increases, too. The increasing power densities require careful thermal design and management. The majority of failures is thermal related, the temperature difference between the material layers within an IGBT or MOSFET structure, plus the differences in the coefficient of thermal expansion of the same layers lead to thermo-mechanical stress.

The failure will develop ultimately at these layer boundaries or interconnects, such as the bond wires, die attach, base plate solder, etc. (see Figure 1). Our technology can induce the failure mechanisms using active power cycling and can track the failure while it develops using high resolution electric tests, from which we derive thermal and structural information.

Figure 1: Cross-section of an IGBT module.

Blyler: Reliability testing during power cycling improves the reliability of these devices. How was this testing done in the past? What new technology is Mentor bringing to the testing approach?

Vass-Varnai: The way we see it, traditionally the tests were done in a very simplified way, companies used tools to stress the devices by power cycles, however these technologies were not combined with in-progress characterization. They started the tests, then stopped to see if any failure happened (using X-ray microscopy, ultrasonic microscopy, sometimes dissection), then continued the power cycling. Testing this way took much more time and more user interaction, and there was a chance that the device fails before one had the chance to take a closer look at the failure. In some more sophisticated cases companies tried to combine the tests with some basic electrical characterization, however none of these were as sophisticated and complete as offered by today’s power testers. One major advantage of today’s technology is the high resolution (about 0.01C) temperature measurement and the structure function technology, which helps users to precisely identify in which structural layer the failure develops and what is its effect on the thermal resistance, all of these embedded in the power cycling process.

The combination with simulation is also unique. In order to calculate the lifetime of the car, one needs to simulate very precisely the temperature changes in an IGBT for a given mission profile. In order to do this, the simulation model has to behave exactly as the real device both for steady state and transient excitations. The thermal simulation and testing system must be capable of taking real measurement data and calibrating the simulation model for precise behavior.

Blyler: Can this tester be used for both (non-destructive) power-cycle stress screening as well as (destructive) testing the device all the way to failure? I assume the former is the wider application in EV/HEV reliability testing.

Vass-Varnai: The system can be used for non-destructive thermal metrics measurements (junction temperature, thermal resistance) and also for active power cycling (which is a stress test), and can track automatically the development of the failure (see Figure 2).

Figure 2: Device voltage change during power cycling for three tested devices in Mentor Graphics MicReD Power Tester 1500A

Blyler: How do you make IGBT thermal lifetime failure estimations?

Vass-Varnai: We use a combination of thermal software simulation and hardware testing solution specifically for the EV/HEV market. Thermal models are created using computational fluid dynamics based on the material properties of the IGBT under test. These models accurately simulate the real temperature response of the EV/HEV’s dynamic power input.

Blyler: Thank you.

For more information, see the following: “Mentor Graphics Launches Unique MicReD Power Tester 600A Solution for Electric and Hybrid Vehicle IGBT Thermal Reliability

Bio: Andras Vass-Varnai obtained his MSc degree in electrical engineering in 2007 at the Budapest University of Technology and Economics. He started his professional career at the MicReD group of Mentor Graphics as an application engineer. Currently, he works as a product manager responsible for the Mentor Graphics thermal transient testing hardware solutions, including the T3Ster product. His main topics of interest include thermal management of electric systems, advanced applications of thermal transient testing, characterization of TIM materials, and reliability testing of high power semiconductor devices.

 

Virtual Reality for Chip Design?

Friday, October 12th, 2012

As chip design moves into the realm of three-dimensional transistor structures and even MEMS, virtual-reality simulators may prove a necessity for both architects and educators.

They say that travel broadens the mind. That has certainly been the case with my recent visits to some of the leading semiconductor and electronics tool companies and research organizations in Europe, including ASMLDassault Systemes, and Imec. Each of these entities offers technologies that are pertinent to the IP community, which I’ll cover in the coming weeks.

For now, let me whet your interest with a short video clip from Dassault Systemes’s virtual-reality development and deployment system, which is called 3DVIA. Think of it as a super-fast and detailed simulation program expanded into three dimensions.

John Blyler explores the large-scale visualization of an industrial chemical facility, which was developed using Dassault Systemes’s 3DVIA Virtools technology. A handheld control enables the user to travel throughout the virtual world.

Such a system might seem like overkill for the world of chip design. After all, EDA-IP tool providers already offer sophisticated modeling and simulation tools for every aspect of chip design – especially in virtual software through hardware-based prototyping. Still, as the chip community moves into an era of 3D structures, through-silicon vias (TSVs), stacked dye, and microelectromechanical (MEMS) devices, the potential benefits of virtual-reality (VR) simulation become more tangible. Such VR simulations could be used to visualize the effects of evolving transistor structures, such as fin-Fetts, or to enhance the accuracy of thermal flows around stacked die. Plus, 3D and virtual-reality models have proven invaluable as teaching aids to both novice and seasoned designers across a wide range of engineering disciplines.

Translating the complex interactions of today’s systems-on-a-chip (SoCs) into a virtual-reality program would require serious processing and graphics hardware. Each dimensional display in the 3DVIA system requires at least one server and GPU cluster. Fortunately, advances in server and GPU technology make these systems available on the commercial market.

Like the EDA industry, chip design must become part of a larger system-design process – both in terms of disciplines (EE-CS-ME) and domains (chips-boards-modules). The move toward a system view necessitates additional simulation and modeling tools. Virtual reality may have a strong play in this evolving world.