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SEMI Pacific NW Breakfast Forum: The Future of Communication

Thursday, April 20th, 2017

Attention – Semiconductor professionals in the Pacific Northwest! SEMI 2017 is having another half-day breakfast forum:

The Future of Communication: from Smart & Connected Devices to Artificial Intelligence and Beyond — Thanks in large part to recent advances in semiconductor technology, the world is on the verge of an unprecedented volume of information exchange that promises to reshape our future.  From Smart Cars to Smart cities, to Artificial Intelligence and Beyond, the so-called 4th industrial revolution will provide us with the means to create new methods of communication with unprecedented capability.

Please join the SEMI breakfast forum to hear their distinguished guest speakers explore both the technology breakthroughs required to realize this future and the potential changes that it portends.  It is also a great event to network with leaders in the local community.

Time: Friday, April 21, 2017  7:30 to 11:30am

Location: Qorvo, 2300 NE Brookwood Pkwy, Hillsboro, Oregon, United States – 97124

Visit the Semi site for details. See you there!

Here are the list of speakers:

  • Leading Technology RF Solutions for 5G and the IoT — Glen Riley, General Manager Filter Solutions Business Unit, Qorvo
  • RF Front End Modules and Components for Cellphones: A Market and Technology Perspective — Claire Troadec, Activity Leader for RF Devices and Technologies, Yole Développement
  • 5G Technologies: Enabling the Next Generation Devices and Networks — Geng Wu, Ph.D., Intel Fellow, Communication and Devices Group, Chief Technologist, Wireless Standards, Intel
  • Jon Maroney — Partner, Oregon Angel Fund
  • ​​​Mounir Shita — Entrepreneur, CEO & Founder, Kimera Systems
  • Eimar Boesjes — CEO, Moonshadow Mobile
  • Stephen A. Ridley — CEO/CTO, Founder,  Senrio

New Event Focuses on Semiconductor IP Reuse

Monday, November 28th, 2016

Unique exhibition and trade show levels the playing field for customers and vendors as semiconductor intellectual property (IP) reuse grows beyond EDA tools.

By John Blyler, Editorial Director, JB Systems

The sale of semiconductor intellectual property (IP) has outpaced that of Electronic Design Automation (EDA) chip design tools for the first time, according to a report of Q3 2015 sales by the Electronic System Design Alliance’s MSS report. Despite this growth, there is no industry event dedicated solely to semiconductor IP – until now.

The IP community in Silicon Valley will witness an inaugural event this week, one that will enable IP practitioners to exchange ideas and network while providing IP buyers with access to a diverse group of suppliers. REUSE 2016 will debut on December 1, 2016 at the Computer History Museum in Mountain View, CA.

I talked with one of the main visionaries of the event, Warren Savage, General Manager of IP at Silvaco, Inc. Most professionals in the IP industry will remember Savage as the former CEO of IPextreme, plus the organizer of the Constellations group and the “Stars of IP” social event held annually at the Design Automation Conference (DAC).

IPextreme’s Constellations group is a collection of independent semiconductor IP companies and industry partners that collaborate at both the marketing and engineering levels for mutual benefit. The idea was for IP companies to pool resources and energy to do more than they could do on their own.

This idea has been extended to the REUSE event, which Savage has humorously described as the steroid-enhanced version of the former Constellations sponsored “Silicon Valley IP User Group” event.

“REUSE 2016 includes the entire world of semiconductor IP,” explains Savage. “This is a much bigger event that includes not just the Constellation companies but everybody in the IP ecosystem. Our goal is to reach about 350 attendees for this inaugural event.”

The primary goal for REUSE 2016 is to create a yearly venue that brings both IP vendors and customers together. Customers will be able to meet with vendors not normally seen at the larger but less IP-focused conferences. To best serve the IP community, the founding members decided that the event’s venue should be a combination of exhibition and trade show, where exhibitors present technical content during the trade show portion of the event.

Perhaps the most distinguishing aspect of REUSE is that the exhibition hall will only be open to companies who were licensing semiconductor design and verification IP or related embedded software.

“Those were the guiding rules about the exhibition,” noted Savage. “EDA (chip design) companies, design services or somebody in an IP support role would be allowed to sponsor activities like lunch. But we didn’t want them taking attention away from the main focus of the event, namely, semiconductor IP.”

The other unique characteristic of this event is its sensitivity to the often unfair advantages that bigger companies have over smaller ones in the IP space. Larger companies can use their financial advantage to appear more prominent and even superior to smaller but well established firms. In an effort to level the playing field, REUSE has limited all booth spaces in the exhibition hall to a table. Both large and small companies will have the same size area to highlight their technology.

This year’s event is drawing from the global semiconductor IP community with participating companies from the US, Europe, Asia and even Serbia.

The breadth of IP related topics covers system-on-chip (SOC) IP design and verification for both hardware and software developers. Jim Feldham, President and CEO, of Semico Research will provide the event’s inaugural keynote address on trends driving IP reuse. In addition to the exhibition hall with over 30 exhibitors, there will be three tracks of presentations held throughout the day at REUSE 2016 on December 1, 2016 at the Computer Science Museum in San Jose, CA. See you there!

Originally posted on Chipestimate.com “IP Insider”

One EDA Company Embraces IP in an Extreme Way

Tuesday, June 7th, 2016

Silvaco’s acquisition of IPextreme points to the increasing importance of IP in EDA.

By John Blyler, Editorial Director

One of the most promising directions for future electronic design automation (EDA) growth lies in semiconductor intellectual property (IP) technologies, noted Laurie Balch in her pre-DAC (previously Gary Smith) analysis of the EDA market. As if to confirm this observation, EDA tool provider Silvaco just announced the acquisition of IPextreme.

At first glance, this merger may seems like an odd match. Why would an EDA tool vendor who specializes in the highly technical analog and mixed signal chip design space want to acquire an IP discovery, management and security company? The answer lies in the past.

According to Warren Savage, former CEO of IPextreme, the first inklings of a foundation for the future merger began at DAC 2015.  The company had a suite of tools and an ecosystem that enabled IP discovery, commercialization and management. What they lacked was a strong sale channel and supporting infrastructure.

Conversely, Silvaco’s EDA tools were used by other companies to create customized analog chip IP.  This has been the business model for most of the EDA industry where EDA companies engineer and market their own IP. Only a small portion of the IP created by this model have been made commercially available to all.

According to David Dutton, the CEO of Silvaco, the acquisition of IPextreme’s tools and technology will allow them to unlock their IP assets and deliver this underused IP to the market. Further, this strategic acquisition is part of Silvaco’s 3-year plan to double its revenues by focusing – in part – on strengthening it’s IP offerings in the IOT and automotive vertical markets.

Savage will now lead the IP business for Silvaco. The primary assets from IPextreme will now be part of Silvaco, including:

  • Xena – A platform for managing both the business and technical aspects of semiconductor IP.
  • Constellations – A collective of independent, likeminded IP companies and industry partners that collaborate at both the marketing and engineering levels.
  • Coldfire processor IP and various interface cores.
  • “IP Fingerprinting” – A package, which allows IP owners to “fingerprint” their IP so that their customers can easily discover it in their chip designs and others using ”DNA analysis” software without the need for GDSII tags.

The merger should be mutually beneficial for both companies. For example, IPextreme and its Constellation partners will now have access to a worldwide sales force and associated infrastructure resources.

On the other hand, Silvaco will gain the tools and expertise to commercialize their untapped IP cores. Additionally, this will complement the existing efforts of customers who use Silvaco tools to make their own IP.

As the use of IP grows, so will the need for security. To date, it has been difficult for companies to tell the brand and type of IP in their chip designs. This problem can arise when engineers unknowingly “copy and paste” IP from one project to another. The “IP fingerprinting” technology developed by IPextreme creates a digital representation of all the files in a particular IP package. This representation is entered into a Core store that can then be used by other semiconductor companies to discover what internal and third-party IP is contained in their chip designs.  This provides a way for companies to protect against the accidental reuse of their IP.

According to Savage, there is no way to reverse engineer a chip design from the fingerprinted digital representation.

Many companies seem to have a disconnect between the engineering, legal and business side of their company. This disconnect causes a problem when engineers use IP without any idea of the licensing agreements attached to that IP.

“The problem is gaining the attention of big IP providers who are worried about the accidental reuse of third-party IP,” notes Savage. “Specifically, it represents a liability exposure problem.”

For smaller IP providers, having their IP fingerprint in the CORE store could potentially mean increased revenue as more instances of their IP become discoverable.

In the past, IP security measures have been implemented with limited success with hard and soft tags. (see, “Long Standards, Twinkie IP, Macro Trends, and Patent Trolls”) But tagging chip designs in this way was never really implemented in the major EDA place and route tools, like Synopsys’s IC Compiler. According to Savage, even fabs like TSMC don’t follow the Accellera tagging system, but have instead created their on security mechanisms.

For added security, IPextreme’s IP Fingerprinting technology does support the tagging information, notes Savage.

Trends in Hyper-Spectral Imaging, Cyber-Security and Auto Safety

Monday, April 25th, 2016

Highlights from SPIE Photonics, Accellera’s DVCon and Automotive panels focus on semiconductor’s changing role in emerging markets.

By John Blyler, Editorial Director

Publisher John Blyler talks with Chipestimate.TV executive director Sean O’Kane during the monthly travelogue of the semiconductor and embedded systems industries. In this episode, Blyler shares his coverage to two major conferences: SPIE Photonics and Accellera’s Design-Verification Conference (DVCon). He concludes with the risk emphasis in automotive electronics from a recent market panel. Please note that what follows is not a verbatim transcription of the interview. Instead, it has been edited and expanded for readability. Cheers — JB

O’Kane: Earlier this year, you were at the SPIE Photonic show in San Francisco. Did you see any cool tech?

Blyler: As always, there was a lot to see at the show covering photonic and optical semiconductor-related technologies. One thing that caught my attention was the continuing development of hyperspectral cameras.  For example, start-up SCiO prototypes a pocket-sized molecular scanner based on spectral imaging that tells you everything about your food.

Figure 1: SCiO Molecular scanner based on spectral imaging technology.

O’Kane: That sounds like the Star Trek Tricorder. Mr. Spock would be proud.

Blyler: It’s very much so. I talked with Imec’s Andy Lambrechts at the Photonics show.  They have developed a process that allows them to deposit spectral filter banks in both the visible and near infra-red range on the same CMOS sensor. That’s the key innovation for shrinking the size and – in some cases – the power consumption. It’s very useful for quickly determining the health of agricultural crops. And all thanks to semiconductor technology.

 

Figure 2: Imec Hyperspectral imaging technology for agricultural crop markets.

O’Kane: Recently, you attended the Design and Verification Conference (DVCon). This year, it was Mentor Graphic’s turn to give the keynote. What did the CEO Wally Rhines talk about?

Blyler: His presentations are always rich in data and trends slides. What caught my eye were his comments about cyber security.

Figure 3: Wally Rhines, CEO of Mentor Graphics, giving the DVCon2016 keynote.

O’Kane: Did he mention Beckstrom’s law?

Blyler: You’re right! Soon, the Internet of Things (IoT) will expand the security need to almost everything we do, which is why Beckstrom’s law is important:

Beckstrom’s Laws of Cyber Security:

  1. Everything that is connected to the Internet can be hacked.
  2. Everything is being connected to the Internet
  3. Everything else follows from the first two laws.

Naturally, the semiconductor supply chain want some assurance the chips are resistant to hacking. That’s why chip designers need to pay attention to three levels of security breaches: Side-Channel Attacks (On-Chip Countermeasures); Counterfeit Chips (Supply-chain security); and Malicious Logic Inside Chip (Trojan detection)

EDA tools will become the core of the security framework, but not without changes. For example, verification will move from its traditional role to an emerging one:

  • Traditional role: Verifying that a chip does what it is supposed to do
  • Emerging role: Verifying that a chip does nothing it is not supposed to do

This is a nice lead into safety-critical design and verification systems. Safety critical design requires that both the product development process and related software tools introduce no potentially harmful effects into the system, product or the operators and users. One example of this is the emerging certification standards in the automotive electronics space, namely, ISO 26262.

O’Kane: How does this safety standard impact engineers developing electronics in this space?

Blyler: Recently, I put that question to a panel of experts from the automotive, semiconductor and systems companies (see Figure 4). During our discussion, I noted that the focus on functional safety seems like yet another “Design-for-X” methodology, where “X” is the activity that you did poorly during the last product iteration, like requirements, testing, etc. But ISO 26262 is a compliant, risk-based safety standard for future automobile systems – not a passing fad.

 

Figure 4: Panel on design of automotive electronics hosted by Jama Software – including experts from Daimler, Mentor Graphics, Jama and Synopsys.

Mike Bucala from Daimler put it this way: “The ISO standard is different than other risk standards because it focuses on hazards to persons that result from the malfunctioning behavior of EE systems – as opposed to the risk of failure of a product. For purposes of liability and due care, reducing that risk implies a certain rigor in documentation that has never been there before.”

O’Kane: Connected cars are getting closer to becoming a reality.  Safety will be critical issues for regulatory approval.

Blyler: Indeed. Achieving that approval will encompass everything all aspects of connectivity, for example, from connected system within the automobile to other drivers, roadway infrastructures and the cloud. I think many consumers tend to focus on only the self-driving and parking aspects of the evolving autonomous vehicles.

Figure 5: CES2016 BMW self-parking connected car.

It’s interesting to note that connected car technology is nothing new. It’s been used in the racing industry for years at places like the Sonoma Raceway near San Francisco, CA. The high performance race cars are constantly collecting, conditioning and sending data throughout different parts of the car, to the driver and finally to the telemetry-based control centers where the pit crews reside. This is quite a bit different from the self-driving and parking aspects of consumer autonomous vehicles.

Figure 6: Indy car race at Sonoma Raceway.

 

 

 

Review of Jama, ARM Techcon and TSMC OIP Shows

Friday, November 14th, 2014

October issues of the “Silicon Valley High-Tech Traveler Log” – with Sean O’Kane and John Blyler

Three events from TSMC, ARM and JAMA Software highlight the breadth and depth of IP development that (hopefully) results in manual-less consumer apps.

A few week’s ago, I attended three shows -  Jama’s Software Product Delivery SummitTSMC’s Open Innovation Platform (OIP) and ARM’s Techcon. While each event was markedly different there was an unintentional common thread, i.e., all three dealt with the interplay between hardware and software IP systems – albeit on different levels of the supply chain.

Each of these shows characterized that interplay in different ways. For TSMC, it was a focus on deep semiconductor manufacturing-related IP. Conversely, Jama Software dealt with product delivery issues for which embedded hardware and application software played a major role. Embedded software on boards running the company’s flagship processors and ecosystem IP hardware peripherals was the focus at the ARM Techcon. Why are these various instantiations of IP important?

Read the rest of the story at: IP-Based Technology without Manuals?

 

 

 

 

 

 

Target Breach Highlights IP Indifference

Wednesday, January 29th, 2014

The good news is that large amounts of IP go into the design of smart-card chips and RFID tags. The bad news is that the general public isn’t really interested.

Read the story on the “IP Insider.”

9 Issues Face Today’s Semiconductor Supply Chain

Friday, January 25th, 2013

While the Global Semiconductor Alliance (GSA) report focuses on China, the challenges discussed apply to the global IC-supply-chain market.

The GSA recently released its “State of China IC Design Industry 2012” report. While primarily focused on China, the report characterizes global challenges facing the semiconductor industry.

To understand these challenges, it’s important to understand today’s IC-supply-chain ecosystem, from EDA design tools and IP reuse to manufacturing and packaging processes. The report notes that fabless companies, which comprise most of the IC design space, rely on IP cores, libraries, design services, software, and embedded operating systems (OSs).

Once produced, most ICs (e.g., ASICs, FPGAs, etc.) are sold to system manufacturers to become part of a larger electronic system before entering the end market as a complete product.

Source: Dr. Wei’s presentation at GSA SLFT 2012

The GSA report lists nine major changes facing the supply-chain process:

  1. Planar CMOS Comes to an End
  2. Application-Driven Innovation
  3. Innovative Business Model
  4. Software Becomes a Must
  5. Knowledge about Process Technology
  6. Few Foundry Resources
  7. Foundry’s Support Capability Lowers
  8. Intention of Investment
  9. A New Relationship between Fabless and Foundry

I’ve covered most of these changes in past stories. But the cumulative impact of all nine warrants a fresh look at each. We’ll start with the first one next time.


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Semiconductor’s Sustainability Promise

Tuesday, July 10th, 2012

The Imec-Semi keynote highlighted how the semiconductor collaboration model and technical advances are addressing critical world issues.

Luc Van Den Hove, CEO and president of Imec, opened the ITF keynote at Semicon West with both humor and caution about our technology-based world. A short BBC One film clip parody of fruit confused for personal computing devices was followed by a collage of grim images depicting the worlds problems, from natural disasters to an aging population, global pollution and even social unrest.

Luc Van Den Hove, IMEC CEO and President.

The common thread in both visuals was the effect of change wrought by technology upon our world. Is this rate of change sustainable by our planet? According to Van Den Hove, the answer lies in our ability to connect, collaborate and innovate.

Technology has contributed to unsustainable changes in our environment, healthcare and social life. Making these changes sustainable in the future is the goal and the promise of the business model and technical advances created by the semiconductor community.

Focusing first on the environment, Van Den Hove observed that the world continues to consume more and more energy. In 2010, consumption had increased by 5 percent. This unsustainable energy rate shows no evidence of slowing down. It has prompted calls for energy reduction, renewable energy sources and a smarter energy grid.

“Semiconductor technology can contribute to implementing more sustainable changes,” noted Van Den Hove. For example, energy generating photovoltaic (PV) solar cells are predicted to reach 1 Terra-Watt of power output by 2020. They will meet 5 percent of the world’s electric energy production. But PV solar cells still face the challenges of efficiency (less than 21 percent) and cost. They must be made more efficient and at consumer-level costs. He noted that materials are a big driver in the cost of PV.

Today, silver is used in 7 percent of PVs. But silver is very expensive and scarce. Once solution would be to replace silver with copper (Cu). In addition to be cheaper and providing greater energy efficiencies, the semiconductor industry is well versed in the use of Cu materials.

Other avenues of exploration by Imec and their partner are organic solar cells, which could be integrated in very flexible form factors.

This is an ongoing report … – JB


Wearable electronics; Semiconductor expertise destroys bacteria; Top IP scorer; Trolls don’t help inventors

Friday, July 6th, 2012

So much came to light this week that I can only offer a sampling from each topic.

You’d expect the July 4th holiday week to be a bit slow on the technology announcement side. That wasn’t the case this year for the world of semiconductor intellectual property (IP). Here are a few of the stories that caught my eye:

1. Simple Process Turns T- Shirt into a Super-capacitor: The clever researchers at the University of South Carolina (USC), led by mechanical engineering professor Xiaodong Li, have developed an easy way to turn a cotton t-shirt into a super-capacitor. Such a device (shirt?) makes the textile itself into a battery for mobile electronics.

Concept model for wearable electronics circa 2005.

A shirt can act as the battery. We already know how to create low-power nano-technology processor andmemory devices from organic materials. Perhaps wearable electronics will now go mainstream. Such consumer products would open up a whole new market for semiconductor IP – especially since the main drivers remain low cost, high volume and short time-to-market.

2. Many EDA-IP tool companies are banking on the idea that the methodologies and techniques created in the semiconductor industry can be applied to other markets, such as medical. I’ve covered some examples of this approach in the past. But here’s a more direct example!

IBM researchers have produced Staphylococcus-killing polymers that leave healthy cells alone. Staph bacteria are especially troublesome since it is not killed by ordinary antibiotics. IBM chemists have drawn from,  “years of expertise in semiconductor technology and material discovery to crack the code for safely destroying the bacteria.”

3. An Ocean Tomo market study confirms that the U.S. has transitioned to an innovation based economy founded upon intellectual property (IP). The report states that eighty percent (80%) of company value is comprised of intangible assets.

A related study – using an Ocean Tomo index – list the top inventor in the semiconductor community as Charles W.C.Lin, chairman and founder of Bridge Semiconductor. One of Lin’s many patents deals with a method for making a semiconductor chip assembly with a press-fit ground plan.

At first glance, it appears that a better path for inventors is through the corporate, rather than university, patent process. To see what I mean, contrast Lin’s standing with one of the discoverers of Graphene (see earlier blog).

4. Another study shows that patent trolls cost the economy $29 billion yearly!

A while back, I wrote how patent enforcers (trolls) argue that they, “help ensure that inventors get paid for their creations, whether through the direct application of their inventions, by lawsuits to collect unpaid royalties or by licensing agreements.”

This report demonstrates the opposite, namely, that patent trolls don’t help inventors. The report examined financial results from 12 publicly traded NPE firms, and found that, “the payments they make to inventors whose patents they acquire are far smaller than the costs they have on defendant companies.”

I encourage everyone to read this excellent, if not rather depressing, write-up. Money that could have been used for innovation is being redistributed to patent trolls and other “unknowns” at a staggering cost.

 

Originally posted on “IP Insider.”

Does Innovation Lie Beyond Software?

Tuesday, May 22nd, 2012

The romance between hardware and software sours, then sweetens after a “three-some”. But no divorce is planned. – Review by Chris Ciufo

Today, it is fashionable to suggest that innovation lies beyond what is common. But perhaps innovation lies in seeing the familiar in a new way.

John von Neumann (1903-57)

In the beginning, there was hardware. But hardware soon tired of its single purpose flip-flops, NAND gates and 555-timers. It longed for a playmate, something to give its existence greater meaning. In desperation, hardware called upon the great architect Von Neumann for help. Being a compassionate yet playful deity, Von Neumann created software.

For a while, all was good. But in time, software grew beyond hardware. Basic firmware evolved into operating systems and eventually application programs which were completely detached from the hardware. For its part, hardware was happy because it could do so many more things than before. But the two wares seemed to be growing apart.

Pleased with its detachment, software soon found that it could model hardware. This capability created an entirely new industry called electronic design automation (EDA). Modeling enabled an architectural idea known as reuse which led to the business of intellectual property (IP).

Software enjoyed its new life until something terrible happened. Hardware became commoditized – cheap, standardized and very reliable. Once that happened, software began to feel lonely and bored. In despair, it called upon the old architect for a new playmate. But Von Neumann had been replaced with a polymorphic-being known as the Consumer. This rather vague and easily confused architect didn’t care about hardware or software. It only cared about the experience provided by its interaction with both hardware and software.

It seemed as if neither software nor hardware were as important as before. Software sighed, wondering if there was something beyond it. Would software – and maybe even hardware – have to serve a different purpose?

Software decided to model this problem. How could the wares provide the experience sought by the Consumer? According to the model, familiar concepts such as power, performance, size and cost would be critical factors in achieving this experience. This, in turn, meant that software and hardware would have to work together in ways that they had never done before.

Finally, software understood. To achieve the experience desired by the Consumer, software and hardware would have to innovate, i.e., to play together in new and different ways. This realization pleased software very much. But before telling hardware the good news, software thanked the Consumer for making its life more interesting again. Unfortunately, the Consumer had already become bored and was busy inventing blended reality. But that’s another story.

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Originally published on Chipestimate.com “IP Insider”



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