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How can the Chip Community Improve the Industry for IOT Designers?

Monday, March 13th, 2017

Meeting the 20 billion IOT devices prediction by 2020 will require the semiconductor industry to streamline its processes for up and coming chip designers.

By John Blyler, Editorial Director, IOT Embedded Systems

Part I of this article covered the difficulties in designing System-on-Chip (SOC) devices for the Internet-of-Things (IOT) market, as explained by Jim Bruister, CEO of SOC Solutions, during his talk at the inaugural REUSE event. In Part II, we will examine ways for the semiconductor and electronics industries to improve the development process for the next generation of IOT designers. — JB

Quotable  Quotes:

  • … the semiconductor community needs to market outside of its traditional channels, for example, to the “Field and Stream” or perhaps the “Sports Illustrated” communities.”
  • … licensing agreements represent a real problem for buyers especially those that must buy IP from multiple vendors.
  • … a general contractor type of person is needed for the emerging IOT design industry.
  • … (could) open source be used to get IOT designers started especially with FPGAs? 

How, then, do we improve as an industry to ensure success for IOT chip designers? Bruister believes there are 5 pieces that need to be in place. First among those is a proactive ecosystem, one that consists of more than just a few companies getting together and sharing their names on websites.

Secondly, the ecosystem must consist of IP providers, design houses and even the foundries whose goal is to offer real SOC reference designs for the IOT community.

Information marketing focused on the IoT business channels is the third needed item. Bruister emphasized that the semiconductor community needs to market outside of its traditional channels, for example, to the “Field and Stream” or perhaps the “Sports Illustrated” communities. The semiconductor world needs to reach out to those places where the next generation of SOC designers will live.

Fourthly, a general contractor type of position is needed in the IOT SOC ecosystem. By analogy, a general contractor is the person that helps you build a house. The general contractor has the experience and connections to bring in and coordinate the activities of the framer, electrician, plumber and others needed to build a house. The same type of person is need for IOT designers.

At this point in the presentation, an attendee from the audience noted the general contractor should probably own all of the tools for the “building of a house” analogy to work. Bruister looked at the problem differently, explaining that the general contractor for a house doesn’t typically own all the tools.

“I see the general contractor (for IOT design) more like a consultant that selects the design house and helps you pick the IP,” explained Bruister. There are design houses that play that role, but it’s not a smooth flow of activities from start to finish for doing an IOT design. That’s where I think a general contractor or coordinator could help.”

The last thing needed for improvement in the IOT design process was one stop shopping with a common licensing model. Today, there is no standard licensing model and there will probably never be one, said Bruister. But the licensing agreements represent a real problem for buyers especially those that must buy IP from multiple vendors. Current models take way too long to license the IP, get it in-house and evaluate the IP. There needs to be a consolidation on how IP is licensed. Bruister suggested a boiler plate IP license that could contain 90% of the common elements required in a license.

Bruister concluded by saying that the semiconductor industry needs to figure out a way to simplify the whole IOT design process. This statement prompted a question about the use of open source tools and IP as a possible solution. The questioner noted that open source could be used to get IOT designers started especially with FPGAs.

Bruister wondered if there were enough open source folks that would significantly help with the 20 billion predicted IOT devices by 2020. Nikos Zervas, CEO of CAST, who was in the audience, noted that relying on open source may be problematic with the millions of dollars involved in chip design. He question who would stand behind the open source tools in such a case.

But the questioner was persistent, saying that even major chip IP providers like ARM don’t pay for the blunders of the chip designer. He cited software as another example were nothing is really warranted, in his opinion.

Bruister tried to address the question by looking at the big picture. For the coming IOT design challenges, there will be one camp of providers who believe that one hundred different designs types will be good for all devices. The opposing camp will believe that each design situation will require some customization, e.g., to include energy harvesting capabilities, etc. Both groups will be large and vocal. The IOT device market will be so big that it will have lots variability.

“But the common thread is that it takes way too long to design IOT devices,” said Bruister. “There is no way we can reach that many devices with such a long design and long IP licensing processes. Expensive tools are always going to be an issue. I don’t think you can get away from that unless the big EDA vendors decide to go with a “pay as you design” model. They have resisted that for years.”

It may be difficult to simplify the process for less SOC experienced IOT designers, but we must try if the IOT market is to realize it’s potential.

Why is Chip Design for IOT so Hard?

Tuesday, February 28th, 2017

Internet-of-Things (IOT) designers face a different set of challenges from their traditional ASIC and SOC brethren. Will the market be ready?

By John Blyler, Editorial Director, IOT Embedded Systems

Quotable Quotes:

  • … we’ll need 10,000 plus IOT designers. Where will they come from?
  • …a majority of IOT designers will have little experienced in traditional SOC design.
  • … SOC industry newcomers will suffer from “new IOT designer anxiety disorder or “New IDeA Disorder”
  • … need modular architectures that are specific to IOT devices.

It’s a daunting task for a non-experienced company to create a custom chip, ASIC or SOC to implement their new “bright idea” IoT product. The company’s engineers face equal challenges in developing, manufacturing, and getting the chip delivered on time. With this introduction, Jim Bruister, President of SoC Solutions, began his talk at the inaugural REUSE show about the overwhelming number of tools, skill sets, costs, IP acquisition and industry associations needed to navigate the chip design and delivery process. He examined how the industry presently supports new chip development and where it needs to go in the future to streamline the process for the non-experienced companies that will no doubt fuel the coming IoT boom.

Bruister started his talk by considering the drivers of IOT in a market predicted to include 20 billion devices by the year 2020. On the business side, IOT will be driven by data and subscription models. But while IOT devices will be enablers for data businesses, the devices won’t be the real money makers. Instead, revenues will flow from data and related analysis. Most of the IOT devices will compete under strong price pressures resulting in cheaper products with tight profit margins.

Further challenging the revenues from physical IOT devices will be the lack of high-end users. For example, many IOT devices will not be fashionable wearables for fitness as most of the world’s population are struggling with basic needs such as indoor plumbing. They have neither the money nor interest in wearable devices. Still, IOT technology will represent a huge electronic market.

“There will be tens of thousands of new IOT businesses in my opinion,” explained Bruister. “This implies at least as many IOT device designers will be needed, or about 10,000 plus. Where will these designers come from?”

It’s reasonable to assume that IOT designers will come from existing system, software, field programmable gate array (FPGA), Printed Circuit Board (PCB) and semiconductor industries. A larger portion will probably come from the FPGA markets while a much smaller amount will come from the semiconductor space.

A majority of IOT companies will be startups, incubated from universities. Naturally, companies will recruit college graduates and interns to do a lot of the work. This means that a majority of designers will have little experienced in traditional SOC design.

“What is the likely approach that these college graduates will take to IOT design,” asked Bruister? His view was that these designers would first turn to Google searches on terms like SOC, chip or ASIC. They will look in trade magazines like EETimes, EDN, Sports Illustrated, Field & Stream and others. They will probably look for SOC experts and semiconductor consultants but there won’t be enough of such gurus to go around.

IP portals like, Design & Reuse (D&R) and others will be consulted only if the college graduate IOT designers know about them. Similarly, these designers might even contact a few design houses if they are aware of them.

One of the big challenges will be the difficulty in maneuvering a typical SOC flow with its many critical steps (see Figure 1). Also, there are over 1,200 IP cores from over 400 IP vendors from which the IOT designer must choose, (see Figure 2). He or she will quickly realize that the front-end design tools are quite expensive, e.g., for synthesis, timing, etc. The back-end tools for place and route and packaging are even more expensive and require tools experts just to run them.

Figure 1: Vendor complexity and cost that IOT designers will face for their SOCs. (Courtesy SOC Solutions)


Figure 2: Snapshot of current semiconductor IP vendors.

The challenges of SOC design complexity, numerous IP vendors, varying licensing agreements and expensive front-end and back-end tools will result in a “new IOT designer anxiety disorder or “New IDeA Disorder,” Bruister noted humorously. The IOT designer will be overwhelmed with too much information (TMI). Where can the designer get help?

Bruister believes that practical education is an important missing piece of the IOT design puzzle. The new inductee will need many “How do” guides, e.g., an IOT SOC Design for Dummies book. He or she will need a better place to find information than performing a Google search. Unfortunately, there are just not enough SOC consultants to go around for the 10,000+ designers that will be needed for devices to go into 20 billion products. Instead, IOT designers will need an easy, fast inexpensive way to design a chip from concept to first silicon. This process will require both easy-to-use development platforms and many reference designs to get things started.

Let’s consider a typical SOC architecture containing a CPU, bus structure, peripherals, and interfaces for radios, baseband processing and sensors (see Figure 3). This architecture probably represents about 80% to 90% of those to be used in most small IOT devices.

What is the 10%-20% difference between the different IOT devices? The type of communication to be used will be one difference, for example, Bluetooth, Wi-Fi, proprietary radios or optical methods. Also, IOT devices will probably have different types of sensors such as accelerometers, MEMs, strain gauges, etc. But Bruister believes that the most important differentiator may lie with the power management unit. IOT devices will have a wide range of power duty cycles requiring the devices to turn on every millisecond, minute, hour or even day and then go back to sleep. Thus, power management will have to be customized for each different type of operational requirement.

Figure 3: A typical System-on-Chip (SOC) architecture. (Courtesy SOC Solutions)

All of these challenges mean that the bar on design abstraction must be raised. Modular architectures will need to be specific to IOT devices. This may result in class libraries for hardware.

“I think we need to raise the bar on design abstraction, noted Bruister. “We need modular architectures that are specific to IOT devices. And we need what I call a set of class libraries for hardware for both analog and digital subsystems. These subsystems will be abstracted away to make it easier for IOT designers to plug play amongst these different models. Also, there will need to be complementary software abstractions, e.g., APIs, HAL layers and such. Design abstractions are common in Arduino and Raspberry Pi platforms.”

The good news is that many of the pieces to create a successful IOT ecosystem are in place. There is a large selection of quality IP suppliers, many of which attended REUSE 2016. Complementing the IP vendors are a number of design houses with a lot of good experience and solutions, noted Bruister. Silicon aggregators like eSilicon and the foundries necessary to actually build the 20 billion IOT devices round out the existing ecosystem.

Part II of this article will examine ways for the semiconductor and electronics industries to improve the design process for the next generation of IOT designers.

Scalable Architectures Expand into FPGAs

Thursday, June 24th, 2010

Moore’s Law assures us that the transistor count of IC devices like FPGAs, ASICs and ASSPs will double every two years – with each successive process node. This means that chip density or capacity will increase and power consumption per transistor will go down.

Still, the numbers for Xilinx’s upcoming 28nm Virtex-7 family of FPGAs are impressive: 50 percent power reduction and more than doubling of the logic cell density (now at 2 million) over its 40 nm Virtex 6 devices.

Aside from improved power, performance and device capacity, the new 7 Series FPGAs offers scalability across the full family of devices. In previous generation of FPGAs, scalability was limited to within a family of devices, such as within the 40nm Spartan or 45nm Virtex-6 families.

This scalability is the result of the company’s unified FPGA architecture in which all of the 7 series devices use the same building blocks (logic fabric, Block RAM, clocking technology, DSP slices, and SelectIO™ technology). These blocks are combined in different proportions to create three new FPGA families at 28 nm:

> Artix-7: Low power, low cost, high volume Spartan replacement.

> Kintex-7: Mid-range for less cost and greater performance-power than the Virtex-6

> Virtex®-7: High-end performance that challenges ASIC and ASSP markets.

Scalability is essential in a world where design reuse is one of the best ways to manage chip costs and shrinking time-to-market windows.

“In an intellectual property (IP) centric world, most customer designs come from somewhere else – a previous design, the partners or us,” notes Patrick Dorsey, Sr. Director, Product Management for Xilinx. “The capability to scale and reuse IP across multiple devices and families is critical.” Such scalability and reuse minimizes the need to re-code, re-simulate, and fix bugs when retargeting an existing design or IP block to a smaller or larger device.

In addition to a scalable architecture, the 28nm FPGAs are implemented on high-k metal gate (HKMG) technology which is optimized for lower power. This results in a 50% decrease in static power and 30% lower total power compared to FPGAs built on the alternative 28nm high-performance process, explains Mustafa Veziroglu, Vice President – Product Solutions and Management for Xilinx.

“In terms of power, most applications consume one third static, one third dynamic and one third input-output power. As we move to 28nm, we’re reducing the total power by about one half,” notes Verziroglu. This means that customers can simply run the device at the lower power level or they can use the power reduction to increase the capacity or feature set of the end-product.

Another benefit of the ever decrease power envelope of next generation FPGAs – coupled with increasing cell capacity – is that these devices may now be capable of breaking into new applications and markets currently dominated by ASICs and ASSPs. The numbers support this assertion as Xilinx claims that – in addition to low power – the 28nm FPGA families provide “2.37TMACs in DSP performance, increase capacity up to 2 million logic cells that run at up to 600MHz, and 1.9Tbps high-speed connectivity.”
In addition to offering a significant challenge to the high performance, high volume ASIC and ASSP markets, this new family of FPGAs also offers improvements into the analog component market. Specifically, the Artix 7 (unlike the equivalent low-end Spartan) can be used to replace a large number of discrete devices with a single FPGA chip. This replacement not only saves on board space and reduces overall power, but can significantly reduce the Bill of Material (BoM) costs.

Although the first 28nm FPGA devices from Xilinx won’t be available until the first quarter of next year, designer can now start using the ISE Design suites that support the 7 series family.

Going Beyond and Returning to Reusability

Friday, February 5th, 2010

Design for the Consumer Era is seen as the next iteration of the infamous Design-for-X paradigm shift by keynote presenter at DesignCon 2010.

One seldom hears anything new or earthshaking at keynote presentations. Instead, good keynote addresses are like filters and amplifiers that simplify complex messages while refreshing their meaning. This is how I would characterize the message delivered by Dr Alex Shubat – CEO and Co-founder of Virage Logic - at Wednesday’s lunchtime keynote at DesignCon 2010.

His keynote focused on the technology and business trends that are pushing SoC designers and companies alike to move beyond the theme of reusability. Design reuse (DFR-Design for Reusability) was a big driver in the ’90s and ’00s. Reuse was part of the productivity era that started with the creation of design automation in the ’80s.

Design Paradigm Progression

Shubat reminded his audience this productivity push was overlapped by today’s ongoing focus on manufacturability which is highlighted by such well-used acronyms as DFM, DFT and DFY, all of which led to the latest Design-for-X terminology for this new decade, namely, Design for Consumer Era (DFC). Interestingly, this seems very similar to the Department of Defense’s Design-to-Cost (DTC) realization during the military cost cutting era of the ’80s and ’90s – without the emphasis on consumerism.

Still, many would argue that the Design-for-Consumer approach is very similar to the Design-to-Cost method in the recognition that cost or rather shrinking profit margins are a key driver in design architectures.

Adding a slight spin to this latest “design” iteration came from a quick chat after the keynote with Brani Buric, executive VP of marketing and sales at Virage Logic. Buric suggested that Design-for-Profitability (DFP) might be an even better phrase to capture the latest reality adjustment for EDA design tool vendors and semiconductor companies.

Regardless of the “D-word” terminology, the SoC design challenges remain frustratingly the same, summed up by increasing complexity, shrinking Time-to-Market and (now) lower profit margins. Shubat concluded his presentation by noting the trend of shrinking size in electronics. Yesterday’s printed-circuit boards are now today’s complex chips that will become tomorrow’s reusable IP.

Some will note that ending suggests a return to reusability, in contrast to the keynote title of “Going beyond Reusability.” But as Shubat explained during his talk, reusability in the ’90s was intended to handle complexity. Today, reusability is seen as the best way to handle complexity as well as cost. In the growing world of electronic consumerism, volumes are high, profit margins are low, and cost (or profitability?) becomes the next “X” for which we need to design.

Reference on DFX:
EDA Could Learn a Lot from Systems Engineering