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A Holistic Approach to Automotive Memory Qualification

Tuesday, January 3rd, 2017


The Robustness Validation approach in design of automotive memory components addresses reliability and safety margins between design and actual application.

By John Blyler, Editorial Director, JB Systems

Improved reliability is just one of the benefits claimed in using the supply-chain sensitive Robustness Validation (RV) approach to qualifying non-volatile memory (NVM) components for automotive electronic application. The following is a summarized and paraphrased coverage of a paper presented by the author, Valentin Kottler, Robert Bosch GmbH, at the IEEE IEDM 2016. — JB

Today’s cars have many electronic systems to control motor, transmission, and infotainment systems. Future vehicles will include more telematics to monitor performance as well as car-to-car communication. As the number of electronic applications in the car increases so does the need for non-volatile memories to store program code, application data and more.

Automotive applications place special requirements on electronic components, most noticeably regarding the temperature range in which the components must operate. Automotive temperature ranges can vary -40 to 165 C degrees. Further, harsh environmental influences like humidity and long vehicle lifetimes are significantly additional requirements not typically found in most industrial and consumer products. Finally, automotive standards place high requirements on electronic component, system and subsystem quality and reliability. For example, it’s not uncommon to demand a 1part per million (ppm) failure rate requirement for infotainment system and a zero defect rate over the lifetime of the car for safety systems, e.g., braking and steering systems. PPM (Parts per million) is a common measurement of performance quality.

These expectations place an additional challenge on components that will wear out during the lifetime of the car, namely, non-volatile memories. Accordingly, such components need to be thoroughly qualified and validated to meet reliability and safety requirements. Adding to this challenge are both the function of the electronic component and its location in the car, all of which creates a wide spectrum of requirements and mission profiles for electronic memory components.

Non-Volatile Memory (NVM) Components

One of the key components in automotive electronics is non-volatile memory, from which program code, application data or configuration bits can be retrieved even after power has been turned off and back on. It is typically used for the task of secondary storage and long-term storage. The size of the NVM in automotive systems can range from a few bytes to many giga-bytes for infotainment video systems.

The various types of NVM adds to the range of available components. For example, a form of NVM known as Flash Memory can have NOR and NAND architectures. Further, there can be single and multi-level cell (SLC and MLC) flash memory technologies. A qualification and validation approach that works for all of these types is needed.

Valentin Kottler, Robert Bosch GmbH

Automotive application requirements can be very different from one application to another. Application requirements will affect the basic performance of memory device characteristics such as speed, write endurance, data retention time, temperature performance and cost effectiveness, noted Valentin Kottler, Robert Bosch GmbH. One particular application may require only a few write cycles of the entire memory. Another application may require the same component to write continuously for over one-half million cycles. Still, another application might require 30 years of data retention, which happens to be the typical 20 year life time of the car plus up to 10 years of shelf time if the supplier has to pre-produce the electronics that support that application.

The simultaneous fulfillment of all these requirements may not be possible in any cost effective way. What is needed is an approach to validation that is application specific. The trade-off is that application specific validation may need to be repeated for each new application that uses a given component. This can mean significant effort in validation and qualification.

Standard approaches using fixed stress tests – like the “3 lots x 77parts/lot approach – will not be able to cover this wide spread of mission profile and the high variety just described. The Automotive Electronics Council (AEC) AEC-Q100 is a failure mechanism based stress test qualification for packaged integrated circuits (1). The 3 lots x 77 parts/lot failure tests aims at a 1% failure rate with 90% confidence.

More importantly, this type of approach does not provide information margins (discussed shortly), which are very important for determining the PPM fail rates in the field.

For these reasons, the standard approach needs to be complemented with a flexible qualification methodology like the robustness validation approach as described on the ZVEI pages (2):

“A RV Process demonstrates that a product performs its intended function(s) with sufficient margin under a defined Mission Profile for its specified lifetime. It requires specification of requirements based on a Mission Profile, FMEA to identify the potential risks associated with significant failure mechanisms, and testing to failure, “end-of-life” or acceptable degradation to determine Robustness Margins. The process is based on measuring and maximizing the difference between known application requirements and product capability within timing and economic constraints. It encompasses the activities of verification, legal validation, and producer risk margin validation.”

Wikipedia defines robustness validation as follows:
“Robustness Validation is used to assess the reliability of electronic components by comparing the specific requirements of the product with the actual “real life values”. With the introduction of this methodology, a specific list of requirements (usually based on the OEM) is required. The requirements for the product can be defined in the environmental requirements (mission profiles) and the functional requirements (use cases).”

The Robustness Validation (RV) technique characterizes the intrinsic capability and limitations of the component and of its technology. It is a failure mechanism and technology based approach using test-to-fail trials instead of test-to-pass and employing drift analysis. Further, it does allow for an assessment of the robustness margin of the component in the application.

For clarification, the test-to-pass approach refers to an application where a test is conducted using a specific user-flow instructions. Conversely, a test-to-fail approach refers testing a feature in every conceivable way possible. Test-to-pass is an adequate approach for proof of concept designs but for end-product systems the test-to-fail is necessary to ensure reliability, quality and safety concerns.

The benefit of the robustness validation approach is that the characterization of the device capability would only need to be done once, explained Kottler. Subsequent activities would allow for the deduction of the behavior of the memory under the various mission profiles without repeating the qualification exercise.

Robustness Margin

Robustness Validation (RV) can be used as a holistic approach to NVM qualification. One way to visualize RV is to consider two memory parameters, i.e., endurance and temperature. The intrinsic capability of the NVM may be described as an area between these two parameters (see Figure 1). Within that area are the hard requirements for the memory (NVM spec) and the application (application spec). The distance between the application spec, the remaining portion of memory and the NVM capability limit is called the “robustness margin.”

In other words, the robustness margin is a measure of the distance of the requirements to the actual test results. It is the margin between the outer limits of the customer specification and the actual performance of the component.

The importance of the robustness margin is that it determines the actual safety margin of the component as used in the application verses its failure mode.

The overall capability of the device including its quality and reliability is that its properties are determined and eventually designed throughout the product development life-cycle phrases:

  • Product & technology planning
  • Development and design
  • Manufacturing and test
  • –In order to prove whether the device is suitable for automotive usage, data is gathered from the early design phases in
  • –addition to qualification trial data.

Then, investigations are held of the performance of the device on a specific application conditions.

Robustness Validation Applied to Memory Qualification

How then do you specifically apply the robustness validation approach to a memory qualification? Kottler listed four basic steps in his presentation (see in Figure 1). One should note that Steps 2 and 3 require input from the NVM suppliers. Further, the NVM supplier can run these exercises without input from Step 1 or output to Step 4. We’ll now consider each of these steps more closely.

Figure 1: Steps to apply the Robustness Validation approach to memory devices.

The first step is to identify the mission profile, which is used to describe the loads and stresses acting on the product in actual use. These are typically changes in temperature, temperature profile, vibration and working of electrical and mechanical fields, or other environmental factors. In order to qualify a non-volatile memory for a specific automotive application, an automotive Tier 1 supplier must therefore identify the sum of application requirements to the NVM and must assess whether and to which extent a given NVM component will fulfil them.

To specifically determine the mission profile, all NVM component application requirements must be collected, from electronic control unit (ECU) design, manufacturing and operation in the vehicle. This is usually done within the Tier 1 organization based on requirements from the vehicle manufacturer.

The second step requires identification of all relevant failure mechanisms. Specifically, it means mapping application requirements to the intrinsic properties and failure modes of the NVM component. This requires the competence of the component supplier to share their understanding of the NVM physics and design to identify all relevant failure mechanisms. Intensive cooperation of the NVM technology and product experts with the quality and reliability team on NVM supplier and Tier 1 sides are necessary to accomplish this step.

As an example, consider the typical requirements to an NVM component. These requirements include data retention, re-programmability and unaltered performance as specified over the vehicle lifetime and under various conditions in the harsh environment of a vehicle. According to Kottler’s paper, some of the corresponding failure mechanisms in a flash memory include the various charge loss mechanisms through dielectrics, charge de-trapping, read, program and erase disturbs, tunnel oxide degradation due to programming and erasing, as well as radiation-induced errors. These mechanisms are already predefined by choices made at design of the NVM technology, memory cell and array architecture, as well as of the conditions and algorithms for programming, erasing and reading.

The third step focuses on trial planning and execution with the goal of characterizing NVM capabilities and limits with respect to the previously identified failure mechanism. As in the previous step, the competence and participation of the component supplier to provide insight into the physics of the NVM, as well as NVM quality and reliability. Acceleration life cycle testing models, parameters and model limitations need to be identified for each failure mechanism. The health of the NVM component related to the failure mechanism must be observable and allow for drift analysis, e.g., by measuring the memory cell’s threshold voltage variations.

How might the drift analysis be performed and by whom, i.e., the supplier or the Tier 1 customer? For example, will the flash memory provider be asked to give the customer more component data?

According to Kottler, the drift analysis will depend upon the flash memory manufacturer to measure data that is not accessible to the customer/end user. Generally, the latter doesn’t have access to test modes to get this data. Only the manufacturer has the product characterization and test technologies related to their components.

The manufacturer and customer should work together to jointly define the parameters that need to be tracked. It is a validation task. The measurements are definitely done by the manufacturer but the manufacturer and customer should jointly interpret the details. What the customer doesn’t need is a blank statement that the components have simply passed qualification. This “test to pass” approach is no longer sufficient, according to Kottler.

The trials and experiments for drift analysis need to be planned and jointly agreed upon. Their execution usually falls to the NVM supplier, being the only party with full access to the design, necessary sample structures, test modes, programs and equipment.

According to Kottler, the identification of an appropriate electrical observable is of utmost importance for applying Robustness Validation (RV) to NVM. Such observables may be for memory cell threshold voltage Vth for NOR flash and EEPROM, or corrected bit count for managed NAND flash memories. Both observables provide sensitive early indication on the memory health status and must therefore be accessible for qualification, production testing and failure analysis in automotive.

The fourth and final step in the Robustness Validation approach involves the assessment of the reliability and robustness margin of the NVM component against the mission profile of the automotive application. The basis for this assessment is the technology reliability data and consideration of the initial design features and limitations, such as error correction code (ECC), adaptive read algorithms (e.g. read retry) and firmware housekeeping (e.g. block refresh and wear leveling), noted Kottler in his paper.

Reliability characterization on technology and component level do not necessarily have to be separated. Combined trials may even be recommended, e.g. for managed NAND flash, due to the complex interaction between firmware, controller and NAND flash memory.

Benefits of the Robustness Validation Approach

The Robustness Validation (RV) approach provides a straight-forward way in which a semiconductor company might design and validate an NVM component that is acceptable in the automotive electronics market. Using RV, the supplier will enable its customers to assess the suitability of the component for their applications in the necessary detail.

The resulting NVM qualification and characterization report that results from the NVM approach should list the memory failure mechanisms considered and characterized. Further, the report should describe the acceleration models applied, and showing drift analysis data supporting a quantitative prediction of failure rate vs. stress or lifetime for each failure mode. According to Kottler, combinations of stresses are to be included according to previous agreements, e.g. data retention capability after write/erase endurance pre-stress, temperature dependent.

To some, the Robustness Validation approach may appear to cause significant additional qualification work. However, most or all of these reliability investigations are part of the typical NVM product and technology characterization during the development phase. For new designs, the optimized top-down RV approach may be applied directly. For existing NVM designs, this approach must be tailored to the agreement of both the NVM supplier and tier 1 company, potentially re-running trials to complete the RV approach. Even so, some existing NVM components may not meet automotive qualification. It is therefore important to jointly assess the feasibility of the automotive NVM qualification by RV prior to the design-in decision.

The end result of the RV approach is an efficient solution to cope with the high requirements of the automotive market, requiring a close cooperation along the value creation chain,” noted Kottler.


The automotive expectations to non-volatile memory (NVM) components continues to grow due to market evolution, increasingly complex data structures and the demand for performance and endurance. Tier 1 and NVM suppliers must cope with this challenge jointly. By considering these expectations from the beginning of product and technology development, and by providing comprehensive data, the NVM supplier can enable the automotive Tier 1 to assess the NVM suitability for the application under a Robustness Validation (RV) approach.


  1. AEC-Q100: Stress Test Qualification for Integrated Circuits – Rev. H, Spe. 2014, pp. 36-30
  2. ZVEI “Handbook for Robustness Validation of Semiconductor Devices in Automotive Applications,” 3rd edition, May 2015, pp. 4-20


Read the complete story and original post on “IP Insider”

Mobile Markets Bode Well for OTP Memory

Friday, June 24th, 2011

Analyst reports from IHS iSuppli suggest a strong market for NAND and DRAM memories, which will be good news to related non-volatile memory devices such as one-time programmable technologies.

If the latest reports are accurate, the mobile memory market will be worth $16.4 billion in 2011. IHS iSuppli researchers report that NAND memory will be the largest product segment this year, followed closely by mobile DRAM. NAND and mobile DRAM are used increasingly in high-end smart phones and tablets. In third place will be NOR memory devices, which are used mainly in lower-end mobile handsets in steadily decreasing amounts.

Before I go further, let’s have a short refresher on the alphabet soup that is the world of memory acronyms. The two main types of memory used today are Random-Access Memory (RAM) and Read-Only Memory (ROM). RAM has very fast access times but burns a lot of power. ROM has much slower access rates but burns less power. The main difference between the two is that RAM needs a constant supply of power to retain its data. ROM retains its data even when power is removed. ROM is an example of non-volatile memory (NVM).

Both NAND and NOR devices are the two main types of nonvolatile ROM. NAND Flash is used in just about every consumer product you can imagine.

An interesting variation to standard types of embedded non-volatile memory is the use of One-Time Programmable (OTP) memory cores. Several fabless semiconductor intellectual property (IP) companies provide OTP memory, including Sidense, Kilopass and NSCore. Most of these companies use an anti-fuse memory approach that is implemented in standard-logic CMOS and requires no additional or post-processing mask steps. One advantage of Sidense’s macrocell IP is that it uses very low power for memory applications in consumer markets.

One more memory refresher for those of us using RAM in our brains:  macrocells refer to hard IP blocks that must be placed manually in the SoC floorplan, whereas standard cells are typically provided by the semiconductor foundry.

One relatively easy way to improve memory performance and lower power consumption is to follow Moore’s law, which leads automatically to reduced die size, faster performance and higher memory densities. A related benefit of Moore’s law is a decrease in the voltage needed to power the transistors. Sidense has taken these benefits to heart by being the first to offer OTP antifuse-based memory cores at the leading-edge process node of 28nm (due in 2012) that also support 1.8V input/output interfaces.

Both low power and smaller die size are prerequisites for mobile applications, such as smart phones and tablets. Technology companies that meet these prerequisites should do well as the market for memory-related products continues to grow.

Originally published in June 2011 issue of, “The NVM Insider,” by Sidence.

Balancing Act Also Extends to Memory

Friday, September 4th, 2009

Intel’s re-entrance with Nokia into the embedded mobile phone business will be a delicate balancing act, as Ed Sperling points out (see main article). But this is nothing new for Intel, as they are making a similar incursion into the memory industry.


Recently, Intel demonstrated Braidwood – a flash memory-based accelerator that caches I/O directly from the processor to enable much faster boot-up times. It will be part of Intel’s upcoming “5 Series” chipset family.


Braidwood is seen by some as a technology that will compete with current board-level Solid State Drive (SSD) devices – another market in which Intel is a player. Talk about a balancing act.


Many industry observers see Braidwood as the successor to Intel’s past Turbo Memory initiative which was less than successful in the commercial market. Why re-enter the memory market again? If Braidwood is as fast as advertised, then it might offer a cheaper alternative to SSD which is still relatively expensive compared to traditional DRAM motherboard memory. Naturally, other performance characteristics must also be considered like power consumption, operational conditions, and the like.


Why should this technology be of interest to embedded designers?  Granted, Braidwood is squarely aimed at the leading edge processor PC market. However, if successful, it may find ready acceptance in the ever shrinking process nodes of Intel’s embedded ATOM processors, for which fast boot-up times are even more critical than in the PC world.