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Posts Tagged ‘IPExtreme’

New Event Focuses on Semiconductor IP Reuse

Monday, November 28th, 2016

Unique exhibition and trade show levels the playing field for customers and vendors as semiconductor intellectual property (IP) reuse grows beyond EDA tools.

By John Blyler, Editorial Director, JB Systems

The sale of semiconductor intellectual property (IP) has outpaced that of Electronic Design Automation (EDA) chip design tools for the first time, according to a report of Q3 2015 sales by the Electronic System Design Alliance’s MSS report. Despite this growth, there is no industry event dedicated solely to semiconductor IP – until now.

The IP community in Silicon Valley will witness an inaugural event this week, one that will enable IP practitioners to exchange ideas and network while providing IP buyers with access to a diverse group of suppliers. REUSE 2016 will debut on December 1, 2016 at the Computer History Museum in Mountain View, CA.

I talked with one of the main visionaries of the event, Warren Savage, General Manager of IP at Silvaco, Inc. Most professionals in the IP industry will remember Savage as the former CEO of IPextreme, plus the organizer of the Constellations group and the “Stars of IP” social event held annually at the Design Automation Conference (DAC).

IPextreme’s Constellations group is a collection of independent semiconductor IP companies and industry partners that collaborate at both the marketing and engineering levels for mutual benefit. The idea was for IP companies to pool resources and energy to do more than they could do on their own.

This idea has been extended to the REUSE event, which Savage has humorously described as the steroid-enhanced version of the former Constellations sponsored “Silicon Valley IP User Group” event.

“REUSE 2016 includes the entire world of semiconductor IP,” explains Savage. “This is a much bigger event that includes not just the Constellation companies but everybody in the IP ecosystem. Our goal is to reach about 350 attendees for this inaugural event.”

The primary goal for REUSE 2016 is to create a yearly venue that brings both IP vendors and customers together. Customers will be able to meet with vendors not normally seen at the larger but less IP-focused conferences. To best serve the IP community, the founding members decided that the event’s venue should be a combination of exhibition and trade show, where exhibitors present technical content during the trade show portion of the event.

Perhaps the most distinguishing aspect of REUSE is that the exhibition hall will only be open to companies who were licensing semiconductor design and verification IP or related embedded software.

“Those were the guiding rules about the exhibition,” noted Savage. “EDA (chip design) companies, design services or somebody in an IP support role would be allowed to sponsor activities like lunch. But we didn’t want them taking attention away from the main focus of the event, namely, semiconductor IP.”

The other unique characteristic of this event is its sensitivity to the often unfair advantages that bigger companies have over smaller ones in the IP space. Larger companies can use their financial advantage to appear more prominent and even superior to smaller but well established firms. In an effort to level the playing field, REUSE has limited all booth spaces in the exhibition hall to a table. Both large and small companies will have the same size area to highlight their technology.

This year’s event is drawing from the global semiconductor IP community with participating companies from the US, Europe, Asia and even Serbia.

The breadth of IP related topics covers system-on-chip (SOC) IP design and verification for both hardware and software developers. Jim Feldham, President and CEO, of Semico Research will provide the event’s inaugural keynote address on trends driving IP reuse. In addition to the exhibition hall with over 30 exhibitors, there will be three tracks of presentations held throughout the day at REUSE 2016 on December 1, 2016 at the Computer Science Museum in San Jose, CA. See you there!

Originally posted on Chipestimate.com “IP Insider”

One EDA Company Embraces IP in an Extreme Way

Tuesday, June 7th, 2016

Silvaco’s acquisition of IPextreme points to the increasing importance of IP in EDA.

By John Blyler, Editorial Director

One of the most promising directions for future electronic design automation (EDA) growth lies in semiconductor intellectual property (IP) technologies, noted Laurie Balch in her pre-DAC (previously Gary Smith) analysis of the EDA market. As if to confirm this observation, EDA tool provider Silvaco just announced the acquisition of IPextreme.

At first glance, this merger may seems like an odd match. Why would an EDA tool vendor who specializes in the highly technical analog and mixed signal chip design space want to acquire an IP discovery, management and security company? The answer lies in the past.

According to Warren Savage, former CEO of IPextreme, the first inklings of a foundation for the future merger began at DAC 2015.  The company had a suite of tools and an ecosystem that enabled IP discovery, commercialization and management. What they lacked was a strong sale channel and supporting infrastructure.

Conversely, Silvaco’s EDA tools were used by other companies to create customized analog chip IP.  This has been the business model for most of the EDA industry where EDA companies engineer and market their own IP. Only a small portion of the IP created by this model have been made commercially available to all.

According to David Dutton, the CEO of Silvaco, the acquisition of IPextreme’s tools and technology will allow them to unlock their IP assets and deliver this underused IP to the market. Further, this strategic acquisition is part of Silvaco’s 3-year plan to double its revenues by focusing – in part – on strengthening it’s IP offerings in the IOT and automotive vertical markets.

Savage will now lead the IP business for Silvaco. The primary assets from IPextreme will now be part of Silvaco, including:

  • Xena – A platform for managing both the business and technical aspects of semiconductor IP.
  • Constellations – A collective of independent, likeminded IP companies and industry partners that collaborate at both the marketing and engineering levels.
  • Coldfire processor IP and various interface cores.
  • “IP Fingerprinting” – A package, which allows IP owners to “fingerprint” their IP so that their customers can easily discover it in their chip designs and others using ”DNA analysis” software without the need for GDSII tags.

The merger should be mutually beneficial for both companies. For example, IPextreme and its Constellation partners will now have access to a worldwide sales force and associated infrastructure resources.

On the other hand, Silvaco will gain the tools and expertise to commercialize their untapped IP cores. Additionally, this will complement the existing efforts of customers who use Silvaco tools to make their own IP.

As the use of IP grows, so will the need for security. To date, it has been difficult for companies to tell the brand and type of IP in their chip designs. This problem can arise when engineers unknowingly “copy and paste” IP from one project to another. The “IP fingerprinting” technology developed by IPextreme creates a digital representation of all the files in a particular IP package. This representation is entered into a Core store that can then be used by other semiconductor companies to discover what internal and third-party IP is contained in their chip designs.  This provides a way for companies to protect against the accidental reuse of their IP.

According to Savage, there is no way to reverse engineer a chip design from the fingerprinted digital representation.

Many companies seem to have a disconnect between the engineering, legal and business side of their company. This disconnect causes a problem when engineers use IP without any idea of the licensing agreements attached to that IP.

“The problem is gaining the attention of big IP providers who are worried about the accidental reuse of third-party IP,” notes Savage. “Specifically, it represents a liability exposure problem.”

For smaller IP providers, having their IP fingerprint in the CORE store could potentially mean increased revenue as more instances of their IP become discoverable.

In the past, IP security measures have been implemented with limited success with hard and soft tags. (see, “Long Standards, Twinkie IP, Macro Trends, and Patent Trolls”) But tagging chip designs in this way was never really implemented in the major EDA place and route tools, like Synopsys’s IC Compiler. According to Savage, even fabs like TSMC don’t follow the Accellera tagging system, but have instead created their on security mechanisms.

For added security, IPextreme’s IP Fingerprinting technology does support the tagging information, notes Savage.

Soft (Hardware) and Software IP Rule the IoT

Tuesday, September 2nd, 2014

By John Blyler, JB Systems

Both soft (hardware) and software IP should dominate in the IoT market. But for which segments will that growth occur? See what the experts from IPExtreme, Atmel, GarySmithEDA, Semico Research and Jama Software are thinking.

The Internet-of-Things will significantly increase the diversity and amount of semiconductor IP. But what will be the specific trends among the hardware and software IP communities? Experts from both domains shared there perceptions including,  Warren Savage, President and CEO of IPExtreme; Patrick Sullivan, VP of Marketing, MCU Business Unit for Atmel; Gary Smith, Founder and Chief Analyst for Gary Smith EDA; Richard Wawrzyniak, Senior Market Analyst for ASIC & SoC at Semico Research, and; Eric Nguyen, Director of Business Intelligence at Jama Software. What follows is a portion of their responses. — JB

Blyler: Do you expect an accelerated growth of both hardware and software IP (maybe subsystem IP) due to the growth of the IoT? What are the growth trends for electronic hardware and software IP?

Savage: I don’t think that there is anything special about the Internet-of-Things (IoT) from an intellectual property (IP) perspective.   The prospect of IoT simply means there is going to be a lot more silicon in the world as we start attaching networking to things that previously were not connected. As a natural evolution of the semiconductor market, hardware and software IP is going to keep growing and will outpace everything else for the foreseeable future. Subsystems are a natural artifact of that maturing as well as customers wanting to do more and more with less people, outsourcing whole functions of chips to be delivered from their IP supplier who is likely an expert in that subject matter.

Sullivan: The largest growth will be in software IP for hardware IPs that already exists in order to connect devices to the Internet. Developers that are not familiar with wireless applications will find themselves making connected devices, and for suppliers to have context aware stacks and other IP tailored for the different IoT usage models will be crucial. i.e.; just having a ZigBee stack is not sufficient. You need a version for healthcare, a version for lighting, and so on.

Security is also going to be an important factor for both securing communication between IoT devices and the cloud (SSL/TLS technologies), and also to authenticate that firmware images running on connected devices have not been tampered with. Addressing these needs may require additional software development of IoT devices, and potentially specialized hardware components as well.

On the hardware side, the main focus will continue to be power consumption reduction as well as range and quality improvements.

Smith: Yes, growth in hardware and software IP will increase with the IoT expansion. However, the IoT market comprise multiple segments. To get accurate growth figures you would need to explore them all (see Table).

Table: Markets for the Internet-of-Things. (Courtesy of GarySmithEDA.com)

Wawrzyniak: I do expect some acceleration of revenues derived from IP going into IoT applications. At this point it is hard to determine just how much acceleration there will be since we are just at the very beginning of this trend. It also will depend upon which types of IP are chosen as the ones most favored by SoC designers. For example, if designers select of one of the wireless IP types as the preeminent solution, then this might be more expensive (generate more IP revenue over time) than say ZigBee.

Given the sheer volume of IoT applications and silicon being projected, it is possible that once a specific process geometry is decided on as the optimum type to use, the IP characterized for that geometry might actually be less expensive than the same IP at another geometry. Volume will drive cost in this case. All these factors will go into figuring out how much additional IP revenue will be generated. I would say a safe estimate today would be on the order of 10%.Wawrzyniak: I do expect some acceleration of revenues derived from IP going into IoT applications. At this point it is hard to determine just how much acceleration there will be since we are just at the very beginning of this trend. It also will depend upon which types of IP are chosen as the ones most favored by SoC designers. For example, if designers select of one of the wireless IP types as the preeminent solution, then this might be more expensive (generate more IP revenue over time) than say ZigBee.

I also think it’s likely that IP Subsystems will be created for IoT applications. Again, this depends on how complex the silicon solution will need to be. If we are talking lightbulbs, then it is hard to imagine that an IP Subsystem will be needed. On the other hand, a relatively complex chip might require an IP subsystem, e.g., a Sensor Fusion Hub subsystem. Sensors will certainly be everywhere in the IoT, so why not create a subsystem that deals with this part of the solution and ties it all together from the designer

Hard IP will probably be more expensive than Soft IP. I would say that Soft IP will be used more in these types of SoCs. I would estimate that it could be as high as a 70 – 30 split in favor of Soft IP.

Nguyen: Absolutely, the growth of IoT will not only open new markets such as wearable technologies and home automation but will also cause disruption in existing due to software based services being delivered through connected devices. Technology products are evolving from electro-mechanical based IP competitive differentiation to customer experience differentiation powered by software applications running on optimized hardware.

The trends in hardware and software IP are accelerating the rate of innovation for customer facing products, which in turn will have a direct impact throughout the supply chain. Software producers must mange the interdependencies not only across their product lines but also across the various technologies they’ll be deployed on (i.e. iOS, Android, Web, integrated into 3rd party technology) or various subsystems. The connected aspect of these technologies allows vendors to continually update the offerings and therefore evolve the customer experience throughout the life of the physical technology.

The performance demands of continuously evolving software heavy products is also driving accelerated innovations throughout the supply chain, specifically hardware components such as Systems on Chip, Systems in a Package, sensor technology, and battery/power management.

Final product producers are also accelerating release cycles and therefore driving the need to more easily integrate sub-components. This demand is driving the demand for Systems in a Package (SiP) technologies, which incorporate the chips, drivers, and software within a physical sub-component package that can easily integrated into the overall system. Semiconductor companies must now coordinate the growing complexity of silicon, software, and documentation development while accelerating their ability to incorporate market feedback into product roadmaps, R&D, and ultimate manufacturing and delivery to customers; all the while ensuring they can meet per unit cost targets.

Blyler: Thank you.

Our Day at DAC – Day 1 (Monday)

Monday, June 2nd, 2014

Here are the brief observations on noteworthy presentations, cool demonstrations and hall-way chats from the editorial staff covering “Day 1″ at DAC 2014 – John Blyler, Gabe Moretti and Hamilton Carter.

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DAC Report from Hamilton Carter:

Puuurrrple, so much purple!  The stage at the packed Synopsys, Samsung, ARM briefing this morning was backed by ceiling to floor Synopsys-purple curtains.  The Samsung vision video played on the two large screens on either side of the stage.  To steal a phrase from “Love Actually”, Samsung’s vision is that “touch-screens are… everywhere” .  Among the envisioned apps were a touch screen floor for your kids’ room, complete with planetarium app; a touchscreen window for your Town-Car so you can adjust the thermostat in the car as your driver taxis you to your destintion; and finally a touchscreen gadget for the kitchen that when laid flat weighs the food and registers the number of calories in the amount you’ve sliced off on its cutting board tough screen, displays the recipe you’re using when upright, and finally, get ready for it… checks the ‘safety’ of your food displaying an all clear icon complete with a rad safe emblem.  Apparently the future isn’t completely utopian!

Phil Dworsky, director of strategic alliances, for Synopsys introduced the three featured speakers, Kelvin Low, of Samsung, Glenn Dukes of Synopsys, and Rob Aitken from ARM, and things got under way.  The key impetus of the presentation was that the Samsung/Synopsys/ARM collaboration on 14 nm 3D finfet technology is ready to go.  The technology has been rolled out on 30 test chips and 5 customer chips that are going into production.

Most of the emphasis was on the 14 nm process nodes, but the speakers were also quick to point out that the 28 nm node wasn’t going away anytime soon  With its single patterning, and reduced power consumption, it’s seen as a perfect fit for mobile devices that don’t need the cutting edge of performance yet.

Interesting bits:

  • It was nice to visit with Sanjay Gupta, previously of IBM Austin, who is now at Qualcomm, San Diego.
  • While smart phones have been outshipping PCs for a while, tablets are now predicted to outship PCs starting in 2015.
  • Bryan Bailey of verification fame was one of the raffle winners.  He’s now a part of the IoT!
  • IoT predictions are still in the Carl Sagan range, there will be ‘billions and billions’.
  • Samsung GLOBALFOUNDRIES has a fab, Fab8, in Saratoga, NY.
  • Last year’s buzzword was ‘metric driven’, this year’s is ‘ecosystem’ so far.  The vision being plugged is collaborations of companies and/or tools that work as a ‘seamless, [goes without saying], ecosystem’.

Catching up with Amiq

I got to catch up with Christian from Amiq this morning.  Since they’re planted squarely in the IDE business, Amiq gets the fun job of working directly with silicon design and verification engineers.  There products on display this year include their Eclipse based work environment, with support for e, and SystemVerilog built in, their verification-code-centric linting tool Verissimo, and their documentation generation system Specador.

IC Manage

I’m always drawn in by a good ‘wrap a measurable, or at least documentable flow around your design process story’, so I dropped by the IC Manage booth this morning.

Their product encapsulates many of the vagaries of the IC development flow into a configuration management tool.  The backbone of the tool can be customized to the customer’s specific flow via scripts, and it provides a real-time updated HTML based view of what engineers are up to as project development unfolds.

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DAC Report from Gabe Moretti:

Power Management and IP

Moscone South is all about IP and low power.  This is the 51st DAC and my 34th.  Time flies.  The most intimidating thing is that the Apple Developers Forum is going on at the same time, and they have TV trucks and live interview on the street.  We of course do not.  It was nice to hear Antun Domic as one of the two keynote speakers this morning  His discussion on how the latest EDA tools are used to produce designs fabricated with processes as old as 180 nanometers was refreshing.  In general people equate the latest EDA tools with the latest semiconductor process.  Yet one needs to manage power even at 180 nanometers.

Chip Estimate runs a series of talks from IP developers in its booth.  I listened to Peter Mc Guiness of Imagination Technologies talk about advances in image processing.  it was interesting to hear him talk about lane departure warning as an automotive feature employing such technology.  Now I know how it works in one of my cars.  On the other hand to hear how the retail industry is planning to use facial recognition to choose for me what I should be interested in purchasing is not so reassuring.  But, on the other hand, its use in robotics applications is fashinating.

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DAC Report from John Blyler:

I. IP Panel: The founders for several successful private IP companies shared their experiences with an audience of near 50 attendees. The panelist included CAST, IPExtreme, Methods2Business, and Recore Systems. The main takeaways were that starting an IP company takes passion and a plan.  But neither will work if you don’t have some product to offer and a few key relationships in the industry. (Warren said you need 3 key customers to start.) I’ll write more about this panel later. Here’s a link to a pre-DAC position statements from the panelist.

II. NI and Cadence – The Best of Both Worlds

George Zafiropoulos, VP, Solutions Marketing at National Instruments (NI)-AWR, has brought his many years of chip design and verification experience from the EDA industry to NI. He spoke at the DAC Cadence Theater about post- and pre-silicon verification being the best of both worlds. Those worlds consist of NI, which has traditionally been used for post-silicon verification testing, and Cadence, which is known for pre-silicon design and verification. George has proposed the use of NI test hardware and software to do pre-silicon verification in combination with Cadence’s emulation tools, i.e, Palladium. This proposed combination of tools elicited many questions from the audience who were more familiar with the pre-silicon tools than the post-silicon testers. Verification languages were an issue for those who had never used the Mindstorm or other NI graphic tools suits. I’m sure we’ll learn more on this potential partnership between NI and Cadence tool suites.

III. Visionary Talk by Wally Rhines, CEO, Mentor Graphics (prior to the afternoon keynote):

The title described it all; “EDA Grows by Solving New Problems.” Wally’s vision focused on how EDA industry will grow even with the constraints on its relatively flat revenue. As he noted back in the 2004 DAC keynote, the largest growth with EDA tools is associated with the adoption of new methodologies, e.g., ESL, DFM, and FPGAs. Further, tools that support new methodologies have been the main drives of growth in the PCB and semiconductor worlds.

“EDA need to tap into new budgets … for emulation, embedded software … and in new markets,” explained Rhines. “The automotive industry is at the same stage of development as was the chip design industry in the 1970s. Their development process will have to be automated and with new tools.”

Another growth market will be hardware cyber security.

DDM and PLM Tools Challenge Semiconductor IP Reuse

Tuesday, May 15th, 2012

Recent data suggests the value and shortcomings of design data management (DDM) and project lifecycle management (PLM) tools to improve IP reuse.

Last time, I focused on the potential long revenue tail of chip design afforded by the extraction, packaging and selling of semiconductor IP. IPextreme is one example of a company that enables the extraction, package and creation of licensable IP products. Websites like the GSA portal, IPestimate’s Constellation platform and Chipestimate.com can help with the distribution and potential sales – among other things.

Yet all of these companies with the exception of Chipestimate.com live outside the realm of the chip development process. Chipestimate.com provides estimation tools like InCyte Chip Estimator and Cadence Chip Planning System (CCPS) that allow designers to make IP tradeoffs in terms of power, performance and even cost. But who can help manage the actual process of chip design?

The answer lays in the world of design data management (DMM) tools, a broad category that encompasses such companies as ICManage, Cliosoft, Methodics, Numertrics, Satin Technology and others. Reaching to even higher levels of design abstraction is software-hardware tools aimed at complete system-level development. (That’s a discussion for another day – or perhaps a month of days.)

Let’s return to our level of abstraction of the chip design and semiconductor IP creation. A recent study found that one of the top factors driving the use of chip-level design management systems is “IP Reuse/Logistics Management (43%).” This data comes from the annual Global Design Management report sponsored by ICManage. Further, the year-over-year data suggests that improved IP reuse and logistics management continue to be illusive goals for most SoC developers.

The report also found shortcomings in existing tool offerings by noting that the most critical feature for IP reuse/logistics management is bug notification and tracing (50 %), followed closely by integrating and assembling the IP in the design (48%) and efficiently making internal IP available for reuse (47%).

Regardless of the shortcomings, any tools that can help manage the growing complexity of the chip design and IP reuse processes are welcomed in our industry.

References:

  • Collaboration Penalty Is Steep For Engineers - System-Level Design sat down to discuss chip-design productivity and quality issues with Srinath Anantharaman, president and founder of Cliosoft; Ronald Collett, president and CEO of Numetrics Management Systems; and Michel Tabusse, CEO and co-founder of Satin Technologies.
  •  The IP Blame Game - The topic of IP quality in the SoC era is difficult to define, and solutions to problems relating to IP quality, verification, and use are hard to find. Debates rage between IP users, suppliers, and EDA vendors about where the responsibility lies for making quality IP available for use and re-use in an efficient, predictable, and scalable manner.
  • EDA Extends Board Design into Manufacturing - A recent EDA and PCB acquisition represents a significant merger between the worlds of electronic and mechanical manufacturing.
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Originally published on Chipestimate.com “IP Insider”

Google’s Software Process Challenges Semiconductor IP

Friday, May 4th, 2012

A recent FCC report blames Google’s software development process for its WiFi privacy breach. How stable is the process for semiconductor IP creation?

The findings were shocking! An FCC report concluded that a lone engineer was to blame for Google’s most controversial breach of online privacy. The report highlighted “apparently serious shortcomings in Google’s software development process.”

“These include claims from Google engineers that they were free to add code to a project without supervision if they thought they “could improve it”, a failure to follow through on a recommendation to have the privacy matter screened by one of the company’s in-house lawyers, and the pre-approval by a senior manager of a document before it was even written.” – Financial Times

This is simply shocking! How could these horrendous missteps have happened? Perhaps to meet deadlines, improve product performances or the morale of the developers?

Certainly these shortcomings never happen at other software development companies! After all, what manager would approve changing the code to improve performance? (Answer: Almost any.) Or what engineer or manager wouldn’t enjoy meeting with legal beagles to explain any technical issue? (Answer: Almost all.)  And what manager hasn’t pre-approved some paperwork to get a project going or back on track? (Answer: The great majority.) In case of documentation, the FCC report doesn’t indicate if the document was a software specification, user guide or product brochure.

My somewhat sarcastic point is that all of these shortcomings in Google’s software development process are common practices – sometimes even best practices. Anyone who has led a team of software developers in the real world – as I have – can attest to the occasional transgression to meet deadlines, stay on budget, improve the product or just get the job done.

Even the most serious allegation in the FCC report seems inconclusive. The search company originally blamed the privacy breach on a lone engineer who intended to write software to collect WiFi network data, not personal information. The validity of that claim should be easy enough to discern by looking at the code. A peer review of the software would quickly confirm the developer’s guilt or innocence.

Blaming the software development process is a tried-and-true way to divert responsibility from management. Neither the FCC report nor Google’s responses provide much insight. One is tempted to ask how Google measures the maturity of their internal software process. Do they use a standard Capability Maturity Model Integration (CMMI) approach or something similar? Searching Google for the answer is frustrating at best. Try it.

Characteristics of the Capability Maturity Model "best practices" for software development.

Some readers may wonder what all of this has to do with semiconductor IP development. Software development challenges are headaches faced by all engineers, programmers and managers – from applications and middleware down through firmware and even – gasp! – chip specific RTL. Have you ever wonder if a method exists to evaluate the software development process of semiconductor IP? Not the verification of IP functionality, but the validation of the development process itself?

Warren Savage, CEO of IP-Extreme, shared insights into this question and others during an interview at the recent GlobalPress eSummit. Look for Savage’s comments in my next blog.

 

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Originally posted on “IP Insider”