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Posts Tagged ‘IEEE’

IEEE Governance in Division

Tuesday, September 20th, 2016

Will a proposed amendment modernize the governance of one of the oldest technical societies or transfer power to a small grouper of officials?

By John Blyler, Editorial Director

As a member of the IEEEE, I recently received an email concerning a proposed change to the society’s constitution that might fundamentally impact the governance of the entire organization. Since that initial email, there have been several messages from various societies within the IEEE that either oppose or support this amendment.

To gain a broader perspective on the issue, I asked the current IEEE President-Elect and well-known EDA colleague, Karen Bartleson, for her viewpoint concerning the opposition’s main points of contention. Ms. Bartleson supports the proposed changes. What follows is a portion of her response. – JB

Opposition: The amendment could enable:

  • a small group to take control of IEEE

Support: Not at all. There is no conspiracy going on – the Boards of Directors from 2015 and 2016 are not sinister. They want the best for the IEEE.

  • transferring of power from over 300,000 members to a small group of insiders,

Support: Not at all. Currently the Board of Directors is not elected by the full membership of IEEE. Allowing all members to elect their Board is more fair than it is today.

  • removing regional representation from the Board of Directors thereby making it possible that, e.g., no Asian or European representatives will be on the Board of Directors – thus breaking the link between our sections and the decisions the Board will make,

Support: No. The slate for the Board of Directors will better ensure geographic diversity. Today, Region 10 – which is 25% of membership – gets only 1 seat on the Board of Directors. Today, there are 7 seats reserved exclusively for the USA.

  • removing technical activities representation from the Board of Directors thereby diminishing the voices of technology in steering IEEE’s future,

Support: No. There will be plenty of opportunity for technical activities to be represented on the Board of Directors.

  • moving vital parts of the constitution to the bylaws – which could be subject to change by a small group, on short notice.

Support: This is not a new situation. Today, the bylaws can be changed by the Board on short notice. For instance, the Board could decide to eliminate every Region except one. But the Board is not irresponsible and wouldn’t do this without buy-in from the broader IEEE.

The society has create a public page concerning this proposed amendment.

It is the responsibility of all IEEE members to develop an informed opinion and vote by October 3, 2016, in the annual election.

 

 

General Chair Shares Insights on DVCon 2016

Monday, February 22nd, 2016

Chair Yatin Trivedi highlights the upcoming US chip design-verification show and differences with European and Asian DVCon events.

By John Blyler, Editorial Director

What’s new at this year’s annual semiconductor chip design and verification conference (DVCon), held between Feb. 29 through Mar. 3, 2016, at the Doubletree Hotel in San Jose, CA? How has the globalization of this event affected the primary show? “JB Systems” sat down with Yatin Trivedi, DVCon General Chair, to answer these questions. What follows is a portion of that interview. – JB

Blyler: How is DVCon doing?

Trivedi: For 2016, we expect attendance to be around 1,000 attendees, about 800 attendees and about 300 exhibitors, which will be greater than last year. The number of exhibit booths should be about 40. People are still signing up. As usual, there will be lots of networking events with qualified engineers. I like to think of DVCon as “Facebook” live for engineers. The value of the show remains the same: attendees are able to learn from their peers.

There will be two panel sessions: one moderated by Jim Hogan on where the industry goes from here and the other moderated by Brain Bailey on ESL. Other opportunities exist in the poster sessions, where people talk with the authors and other engineers. Everyone exchanges good pieces of information about what does and doesn’t work and under what conditions.

The exhibit floor provides a place to show attendees that vendor claims about solutions can actually be demonstrated.

There will be 37 papers at this year’s show plus a couple of invited talks. The CEO of Mentor Graphics, Wally Rhines, will present the invited keynote on Tuesday. Tutorials start on Monday with courses on Accellera standards given by Accellera committee members. Vendors will provide tutorials on Thursday to solve specific problems. Topics range from debug methodologies to the Universal Verification Methodology (UVM), SystemC, formal verification and more.

Blyler: Recently, DVCon has expanded into Europe and Asia. What is the latest information on those activities?

Trivedi: DVCon US is the flagship of the show. A few years back we had the first DVCon Europe and India. We started events in these countries as a way to serve specific centers of excellence. For example, a lot of automotive work is done in Europe because of the presence of BMW, Mercedes and other automotive manufactures. Naturally, a large community of electronic designers has developed to support these companies.

Another motivating factor is that not everybody has the opportunity to travel to the US for DVCon. European Accellera board members like ST, NXP, Infineon, ARM and others convinced us of the need for a DVCon in Europe. So we put together the first conference in 2014, which had about 200 people. At last year’s event in 2015, we had over 300 attendees. The reason for the growth was pent-up interest from local communities that could not travel. The other benefit of a local DVCon was that people who could attend would be more willing to submit technical papers.

Blyler: Did the show in India grow from the same motivation as in Europe?

Trivedi: No, it happened a little bit differently. In India, there was already an event called India SystemC User Group or ISCUG. This event had about 300 people. At the same time, there existed a chip design-verification (DV) community that wasn’t exactly served by ISCUG. The merging of the Open SystemC Initiative (OSCI) with Accellera presented the opportunity for DVCon to open in India with two tracks: One for ESL or SystemC and another track on design and verification (DV). The later track provided a new platform where DV engineers could get together. At the first show in 2014, we had about 450 attendees. Last year in 2015, we topped 600 attendees. As a two year track record, that’s about 30 to 40% growth year-over-year.

Initially, we were worried that these new conferences might cannibalize the original US conference. That fear never came true because the paper submissions for the new shows came from local communities as did the volunteer organizations in terms of program and steering committees, exhibitors, etc. And the attendance came locally. It was probably something we should have done earlier.

This means that DVCON globally has grown to a 2000+ worldwide community.

Blyler: Thank you.

Dr. Stan Krolikoski’s Words and Award

Friday, May 31st, 2013

A look back at Stan’s blogs and a look forward to his award.

At this year’s Design Automation Conference, Dr. Stan Krolikoski was honored with the 2013 Accellera Systems Initiative Leadership Award for his vision and contributions to EDA and IP standards.

Dr. Krolikoski has a long list of technical and business achievements. He has held vice president positions at EDA giant Cadence and start-ups like ChipVision, where he was the CEO. He has been a welcome presence in various standard communities throughout his career. (Here’s just one example: “Interview with Stan Krolikoski at DVCon 2011 –  SystemC Day” – Discussion on Verification IP (VIP), SystemC, IEEE 1666 Standard).

Chipestimate.TV's Sean O'Kane interviews Stan Krolikoski at DVCon 2011 - SystemC Day.

On a more personal basis, I was proud to have Stan as a blogger on Chip Design magazine, where he covered standards and the people behind them for many years. What follows is a brief listing of those blogs:

Looking at DVCon 2012

DVCon 2012 ended yesterday, March 1.  Rather than recap the entire conference, I’d like to focus on the “high energy” surrounding the event, starting with the vendor exhibitions.

John Aynsley and the IEEE SystemC LRM

The Accellera Systems Initiative has announced that John Aynsley, the CTO of Doulos, will be awarded that organization’s Technical Achievement Award for his “contributions to SystemC”…How, then, was any technical process managed, when there was only one technical meeting?  Simply put, almost all progress was made as the result of discussions held via the group’s email reflector.

Get Ready ‘Cause Here It Comes: Accellera Systems Initiative Day @ DVCon

Lots of ink has been spilt (in a good cause) in reporting on the new Accellera Systems Initiative organization.  However, many of you may still wonder how you can get an in-depth view of what is happening in this new organization, which resulted from the merger of Accellera and the Open SystemC Initiative (OSCI).

Why the OSCI-Accellera Merger?

By now, most of you will have heard and read about the merger of Accellera and OSCI into the Accellera Systems Initiative. A question that may linger after reading various press accounts is, “Why a merger?”

Larry, Larry, Larry!

On Sunday, December 4, Larry Saunders received the Ron Waxman award from the IEEE Design Automation Standards Committee (DASC) for extraordinary service to the DASC.

Ada-C redux

In a recent post on the DeepChip website, Gary Smith states that Fortran and Ada are superior to C and its variants, but notes that “…unless there is a major revolt among Embedded Programmers, we are stuck with C and SystemC.”

The Deaths of Two Tech Giants

All of you undoubtedly noted the passing of Steve Jobs on October 5.  What you might have missed is the passing of another high-technology giant, viz., Dennis Ritchie a few days later.  Ritchie was the father of the C language and one of the main forces behind the development of UNIX®.

OSCI-Accellera: Cue Mr. Peabody’s WABAC Machine

As most of you will have seen by now, Accellera and OSCI have announced their intention to form a new EDA standards organization, which will cover the design flow roughly from gate-level up through the system-level.  This may seem to be a natural move to most people, and one that could easily have happened years ago.

DVCON & DATE 2011: A Retrospective

The last two months since my last post have been extremely busy for me—several weeks out of the office and new responsibilities at work.  In this post, I’d like to briefly look at the two conferences, DVCon and DATE, that I attended during this period.

Reflections on UVM 1.0

As you may have already seen in the blogosphere and in the tweetdom, the Accellera Board today approved the release of UVM 1.0.  This release is a major accomplishment from a technical standpoint, but it also represents a triumph of the collective will of the electronics/EDA industry.

Thoughts On SystemC Users’ Groups

I ate breakfast a few weeks ago with Gabe Moretti of GabeOnEDA fame—always a pleasant event.  During our discussion, Gabe opined that the Open SystemC Initiative (OSCI) was superior to other front-end standards organization because of its SystemC Users’ Groups like NASCUG, ESCUG, the Taiwan SystemC users’ Group, SystemC Japan, and so forth.

SystemVerilog in Japan

During the EDSF show held in Yokohama in late January, there were several meetings between members of JEITA and members of the IEEE Design Automation Standards Committee (DASC): Hamaguchi-san (SystemVerilog WG Chair, Panasonic), Kojima-san (JEITA Fellow, NECST), Imai-san (SystemC WG Chair, Toshiba).

Standards– This Time It’s Personal

On Sunday evening, December 6, I came face-to-face with part of my past.  The window to my past was opened by meeting (after a very long hiatus) with two of the “founding fathers” of the EDA standards world, Hal Carter and Ron Waxman, at the IEEE Standards Association Awards Banquet in New Brunswick, NJ.

Another Standard Forthcoming in 2011

In my most recent post, I highlighted two standards that are scheduled to be released in 2011, viz., UVM from Accellera and SystemC from the IEEE P1666 Working Group (WG).  In this post, I’ll focus on another standard that will be put to a vote (and presumably approved) in 2011.  This standard is the “e” language standard developed by the IEEE P1647 WG, chaired by Darren Galpin.

New & Updated EDA Standards Coming In 2011

I have not posted in a few weeks, but not because things have been quiet in the standards world.  Rather, too much has been happening, and it has been hard to find time to sit down and summarize for those who might not be intently following such things.

Planning For IEEE Standards Association Corporate Membership

With the 2011 corporate budget planning cycle about to begin in many companies, I thought it appropriate to review the IEEE Standards Association (SA) corporate membership plan, including both its costs and benefits. 

Standards & Reference Implementations

In a previous blog entry, I spoke about the relationship between standards and open-source software, concluding that “open-source standard” was an oxymoron.

DVCon 2011 Is Open For Business

DVCon 2011, sponsored by Accellera, is now open for paper abstracts and proposals for panels/sponsored tutorials.

The Importance of Front-End Standards

It was recently announced that Shishpal Rawat has been elected Chair of Accellera, a key “Front End” (i.e., RTL and above) EDA standards organization.  This by itself is a fine development, since I have absolutely no doubt that Accellera will prosper under Shishpal’s leadership.

The “Open Source Standard” Oxymoron

Recently, I explained why the forthcoming Accellera UVM Standard will not be released under an open-source license. UVM will have an open-source reference implementation associated with it, but the actual UVM Standard will not be open source.

Model-Driven Development Is Key to Low Power

Thursday, December 6th, 2012

Mentor Graphics explains why the model is the design at a system engineering forum hosted by Portland State University (PSU), INCOSE, and the IEEE.

Panelists from industry, national laboratories, and the Portland State University’s System Engineering graduate program recently gathered for an open forum on model-driven engineering. The event was hosted in collaboration with PSU, the International Council on Systems Engineering (INCOSE), and the IEEE.

Among those invited to speak was Bill Chown, Product and Marketing Manager from Mentor Graphics’ System Design group. He spoke about Model-Driven Development (MDD), a contemporary approach in which the model is the design and implementation is directly derived from the model.

“At first glance, Model-Driven Development might seem a long way from low-power design, where typical approaches focus on execution speeds, power regions, and switching efficiency,” explained Chown in a follow-up conversation. “But major gains in conserving power will only be made from optimization at the architectural level, when whole functions can be reassigned, implemented efficiently, or even eliminated completely.”

How does an MDD approach work within the typical life-cycle development of a product or system? What follows is a partial explanation, provided by Chown.

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Most systems (or products) start out with an idea – one that is initially ill-formed, incomplete. How can we refine that idea, develop the thoughts, and arrive at something that others will appreciate – and that can be implemented most effectively within the system design constraints?

First, we need to insert some clarity and start to define what is required – and what a “requirement” really is. Once we can describe the requirements, we can pass them on to the ever-broader team that it takes to implement today’s products. And it is their interpretation of those requirements that will actually shape the product that eventually emerges from the process.

By building a concept “model,” designers can explore the problem as described and start to elaborate it.

As we look at the idea, we ask questions, challenge concepts, and build on the initial premise. A concept model helps by setting out those concepts and enabling the queries.

As we do this, we begin to extract actual requirements – “the system shall weigh less than 300 gm,” “power in operation cannot exceed 3000 mWhours,” etc. – and generate the initial requirements “specification.” We will not model the implementation of these requirements initially, but will factor them into the system design as constraints to track through to implementation.

From the initial concept model can be derived a potential solution – or, more probably, several potential solution choices. These models may be minor variants on the concept or radically different approaches. But we can consider the same requirements, interchange the approaches of the potential solutions with the starting idea source (typically a person), and start to ask the next set of questions.

The goal here is to start to evolve a solution specification that can be shared with stakeholders, can be acted upon in the downstream design flow, and will satisfy the constraints once we are in a position to validate them.

Executable Specification

The term “executable specification” is often raised as an approach to addressing the disconnect between textual customer-facing initial needs and an actionable, concrete, and deliverable design specification. However, there can be – and usually needs to be – several steps to build up an executable specification that is useful and can support those goals.

An executable specification needs to deliver on the two key topics introduced previously: show what we have and enable initial questions to be asked. Answering questions and responding – with possible changes to the concept or early design or significant features of the eventual product that should be highlighted – are essential capabilities to be sought in a good executable specification. A well-understood specification can lead to a successful design and an effective design process that can be reused time and again on the path to implementation. This, in turn, permits consideration of those key design constraints at a stage where changes can be made – and with a true model-driven flow, be rapidly developed into measurable implementations.

Partition

Assignment of functionality to an implementation path is often performed very early in the design process. It is therefore performed without sufficient information to make an informed decision. Furthermore, once selected, that tends to become the only choice. Later learning is very hard to incorporate, leaving the design architecture prematurely frozen.

Typically, we do not know enough to make the optimum partitioning choices. Design decisions are thus frozen into less than optimal configurations, and constraints will be hard to meet by trying to adjust final implementations. To improve this step and enable a more effective and flexible flow, more information is essential – as is an architecture of the process that will enable change.

Here, the use of models – the fundamental premise of MDD, and in fact already in many of our current processes – can make the crucial difference. Models allow us to exercise the proposed partitioning and ask the next set of questions. Models can grow and evolve to add key information, and thus develop to enable the design validation needed.

Functional Virtual Platform

The next questions relate to overall system functionality and behavior – initially at a high abstraction level, but extending to recognize implementation characteristics. To find out if we have assembled the full set of design elements required and to see if they interact with each other as expected, we should use a virtual platform. At the initial stage, the virtual platform does not need great detail, timing, or similar constraints. But it does need to enable rapid execution to exercise all of the functionality. What the virtual platform does enable – and at a significant and important stage in the process – is the checkpoint between these partitioned disciplines to ensure continuing consistency.

SystemC has become a popular basis for an executable virtual platform that can incorporate the artifacts of hardware behavior, such as bus cycles and timing, without having to go into the detail and execution performance burden of fully elaborated RTL design. Performance can be estimated, system conflicts identified, and resources planned. In an effective MDD flow, the necessary building blocks of the virtual platform can be generated from the higher-level models used in the executable specification, linked together with standard library models like processor instruction-set simulators, and run.

This virtual platform can then be augmented with wrappers that add more comprehensive timing, execution speed, and power knowledge – while enabling that validation of constraints identified in the initial requirements and executable specification.

Should the architecture be found to miss key needs, a Model-Driven Development flow enables revisiting those prior partitioning choices, adjustment of the architecture to provide alternative potential implementation solutions, and the rapid regeneration of a new virtual-platform configuration. Multiple architectures can be assessed and required functionality delivered for validation – enabling the consideration of power-sensitive design areas and the deployment of more efficient techniques before committing to a fixed target platform.

Tweets from Hot Chips

Friday, August 31st, 2012

Here are my Tweets from the Wednesday session – August 29, 2012 – at the Hot Chips forum. I’ll have more editorial next week on this event.

Beauty in Chip Failures

Thursday, July 17th, 2008

“Beauty is in the eye of the beholder” — Greek, 3rd century BC

The pictures of the impurities that cause chip failures can be amazing. Below is a sample of an AL-based flower like crystalline impurity. For more, visit the IEEE Online – The Art of Failure.