Part of the  

Chip Design Magazine


About  |  Contact

Posts Tagged ‘IEDM’

Modular FinFET Increases Planar-to-Non-Planar IP Reuse

Friday, January 11th, 2013

At IEDM, Globalfoundries explained why its 14-nm-class Fin with a 20-nm back-end combination would increase planar IP portability to non-planar FinFETs.

Often, the best questions are asked and answered after the main event. A case in point was the press roundtable that convened after Globalfoundries CEO Ajit Manocha’s luncheon keynote during the 2012 International Electron Devices Meeting (IEDM). Manocha (center seat) was joined by the following senior executives: Suresh Venkatesan (left seat), Senior Vice President of Technology Development, and Subramani Kengeri (right seat), Vice President of Advanced Technology Architecture (see Figure 1). What follows is an edited version of that question-and-answer session. – JB


Figure 1: Pictured are the Globalfoundries CEO and senior executives at the IEDM press roundtable. Jason Goross, Communications Manager, is shown standing.

Question: What about new technologies, like Extreme-Ultra-Violet (EUV) lithography and directed self-assembly?

Manocha: We’re working on EUV technology as well as immersion scanners for double patterning (see Figure 2). The jury is still out on commercial EUV, especially since suppliers remain 9 months or so out.

We are not working on directed self-assembly (DSA; a manufacturing process to improve both optical and EUV). Thus far, it is not a prime consideration for 7-nm-node technology. However, we have been talking with KLA-Tencore as part of our open collaboration approach to deciding the right thing to do.

As I mentioned in my keynote, at least one big company (IDM/foundry) is under 50% utilization capacity. We need a way to keep it going by living on 28-nm with silicon-on-insulator (SOI) and other technologies.

Figure 2: In his IEDM 2012 keynote, Globalfoundries CEO Ajit Manocha talked about the challenges facing the semiconductor manufacturing industry.

Question: Is Globalfoundries FinFET-friendly?

Manocha: We are mitigating the risk of mobile systems-on-a-chip (SoCs) by incorporating a 20-nm back end with a 14-nm front end.

Kengeri: Globalfoundries wants to leverage all of its 20-nm investment. That includes reusing models on the technical side. For example, there are 7000 ground rules. We want to carry those rules over, only changing the device. On the design side, people are used to 20-nm design rules. We want to keep that design infrastructure.

Editor’s Note: As announced in Sept. 2012, GlobalFoundries is taking a “modular Fin” approach with its bulk FinFET offering, dubbed 14nm-XM (see Figure 3). This approach combines a 14-nm-class Fin with its 20-nm back-end-of-line (BEOL) interconnect flow. It includes  ‘Fin-Friendly Migration’ (FFM) rules to allow the fast porting of planar intellectual- property (IP) designs to FinFET. The company predicts 40% to 60% improved battery life and 20% to 55% higher performance (depending on operating voltage) vs. other 20-nm, 2D planar transistors. (See “GlobalFoundries Rolls Out 14nm finFET Process.”)

Figure 3: Shown is Globalfoundries' 14nm-XM FinFET structure.

Question: Regarding the IP side, won’t changing the device cause changes in the IP?

Kengeri: Yes, we do need to redo the IP (for 14nm-XM), but not as much as before.  We don’t need the 2x change that is traditionally needed between major node jumps. There is where the ecosystem engagement comes in. The IP is being designed because the 14nm-XM design kit (PDK) is already complete.

In addition, there is concurrent IP development within our ecosystem (e.g., ARM), since the physical design rules are already there.

Venkatesan: Let me add a quick comment. We have done the physical design, electrical characterization, and optimizing of the IP.  The physical design rules for 20 nm are complete, so the IP development has started. IP developers can be assured that no big changes will happen. There may be changes in the electrical characteristics, but that just needs retiming, etc. – not the same level of pain and suffering as the PDK development. [Note: The PDK contains descriptions of the basic building blocks of the process including FinFET (Spice) models, advanced extraction,  double patterning, DFM, FFM, Ref flows, P&R…]

Editor’s Note: In this short video, Sean O’Kane from Chipestimate.TV and I talk with ARM’s John Heinlein about the coming challenges faced by IP designers using FinFET structures.

TSMC OIP 2012: ARM’s John Heinlein is interviewed about IP and FinFETs.

Originally published on “IP Insider.”

Free counter and web stats

STMicroelectronics Pushes SOI While Leaving the Mobile Space

Thursday, December 20th, 2012

Why is one of Europe’s leading semiconductor IDMs pushing into leading-edge, 28-nm FD-SOI technology while leaving a market where such technology might be useful?

It was a chance meeting that made me wonder about two recent announcements from one of the world’s largest semiconductor companies.

Last week, I attended an IEDM briefing in which STMicroelectronics presented silicon-verified data to further confirm the manufacturability of its 28-nm Fully Depleted Silicon-on-Insulator (FD-SOI) technology (see “FinFETs or FD-SOI?“). Ed Sperling, Editor-in-Chief for SemiMD, summed it up this way:

“What’s particularly attractive about FD-SOI is that it can be implemented at the 28-nm node for a boost in performance and a reduction in power. The mainstream process node right now is 40 nm. And while Intel introduced its version of a finFET transistor called Tri-Gate at 22 nm, TSMC and GlobalFoundries plan to introduce it at the next node—whether that’s 16 nm or 14 nm. That leaves companies facing a big decision about whether to move all the way to 16/14 nm to reap the lower leakage of finFETs, whether to move to 20 nm on bulk, or whether to stay longer at 28 nm with FD-SOI.”

Joel Hartmann, Executive VP Front-End Manufacturing & Process R&D, STMicroelectronics, presents SoC-level, 28-nm Planar Fully Depleted silicon results at IEDM 2012.

I didn’t realize until later that week, but – on the same day as its 28-nm FD-SOI technology announcement – STMicroelectronics stated that it would curtail its presence in the mobile-handset space via the Ericsson partnership. As Chris Ciufo noted in his “All Things Embedded” blog, Ericsson will remain in only two market domains: Sense and Power and Automotive as well as Embedded Processing. “For the former, device categories include MEMS, sensors, power discretes, advanced analog, automotive powertrain, automotive safety (such as Advanced Driver Assistance Systems [ADASs]), automotive body, and the red-hot In-Vehicle Infotainment (IVI) category,” wrote Ciufo.

In the embedded processing market, the company will “focus on the core of the electronics systems” and ditch wireless broadband. Target areas include microcontrollers, imaging, digital consumer, application processors, and digital ASICs.

Considered together, these two announcements beg the following question: If STMicroelectronics is only interested in the sensor, automotive, and “embedded” markets, why does the company need to work at leading-edge process nodes – like 28 nm on FD-SOI? This question arose during a recent chance meeting with Juergen Jaeger, Sr. Product Manager at Cadence Design Systems.

Jaeger suggested a possible answer by noting that Moore’s Law generally provides a cost savings with power and performance benefits at lower processing nodes. “This makes sense for both automotive infotainment and networking technologies,” explained Juergen. “But it doesn’t make too much sense for gearbox, engine, anti-lock brakes, or steering systems, since they need high reliability and tolerance.” Those requirements tend to restrict devices to fully tested, high-node geometries.

Jaeger reminded me that infotainment systems-on-a-chip (SoCs) are very complex devices requiring integrated network and wireless systems – in addition to an array of audio/video codecs that must drive multiple LCD screens within today’s cars.

Additionally, STMicroelectronics’ move to FD-SOI is one way to mitigate the risk facing leading-edge bulk CMOS processes. As Sperling observed, “At 28 nm and beyond, however, bulk has run out of steam, which is why Intel has opted for finFETs.” Meanwhile, FD-SOI offers power and performance benefits while staying on today’s planar-transistor manufacturing processes.

In the end, the push toward FD-SOI technology at exiting 28-nm nodes may play well into a number of low-power and high-performance chip markets. This is not a path without risk. But it does highlight the accelerating convergence of SOI and bulk CMOS at leading-edge nodes. And it should strengthen STMicroelectronics’ strong position in the automotive infotainment space.

Originally posted on “IP Insider.”