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Posts Tagged ‘Globalfoundries’

Our Day at DAC – Day 1 (Monday)

Monday, June 2nd, 2014

Here are the brief observations on noteworthy presentations, cool demonstrations and hall-way chats from the editorial staff covering “Day 1″ at DAC 2014 – John Blyler, Gabe Moretti and Hamilton Carter.

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DAC Report from Hamilton Carter:

Puuurrrple, so much purple!  The stage at the packed Synopsys, Samsung, ARM briefing this morning was backed by ceiling to floor Synopsys-purple curtains.  The Samsung vision video played on the two large screens on either side of the stage.  To steal a phrase from “Love Actually”, Samsung’s vision is that “touch-screens are… everywhere” .  Among the envisioned apps were a touch screen floor for your kids’ room, complete with planetarium app; a touchscreen window for your Town-Car so you can adjust the thermostat in the car as your driver taxis you to your destintion; and finally a touchscreen gadget for the kitchen that when laid flat weighs the food and registers the number of calories in the amount you’ve sliced off on its cutting board tough screen, displays the recipe you’re using when upright, and finally, get ready for it… checks the ‘safety’ of your food displaying an all clear icon complete with a rad safe emblem.  Apparently the future isn’t completely utopian!

Phil Dworsky, director of strategic alliances, for Synopsys introduced the three featured speakers, Kelvin Low, of Samsung, Glenn Dukes of Synopsys, and Rob Aitken from ARM, and things got under way.  The key impetus of the presentation was that the Samsung/Synopsys/ARM collaboration on 14 nm 3D finfet technology is ready to go.  The technology has been rolled out on 30 test chips and 5 customer chips that are going into production.

Most of the emphasis was on the 14 nm process nodes, but the speakers were also quick to point out that the 28 nm node wasn’t going away anytime soon  With its single patterning, and reduced power consumption, it’s seen as a perfect fit for mobile devices that don’t need the cutting edge of performance yet.

Interesting bits:

  • It was nice to visit with Sanjay Gupta, previously of IBM Austin, who is now at Qualcomm, San Diego.
  • While smart phones have been outshipping PCs for a while, tablets are now predicted to outship PCs starting in 2015.
  • Bryan Bailey of verification fame was one of the raffle winners.  He’s now a part of the IoT!
  • IoT predictions are still in the Carl Sagan range, there will be ‘billions and billions’.
  • Samsung GLOBALFOUNDRIES has a fab, Fab8, in Saratoga, NY.
  • Last year’s buzzword was ‘metric driven’, this year’s is ‘ecosystem’ so far.  The vision being plugged is collaborations of companies and/or tools that work as a ‘seamless, [goes without saying], ecosystem’.

Catching up with Amiq

I got to catch up with Christian from Amiq this morning.  Since they’re planted squarely in the IDE business, Amiq gets the fun job of working directly with silicon design and verification engineers.  There products on display this year include their Eclipse based work environment, with support for e, and SystemVerilog built in, their verification-code-centric linting tool Verissimo, and their documentation generation system Specador.

IC Manage

I’m always drawn in by a good ‘wrap a measurable, or at least documentable flow around your design process story’, so I dropped by the IC Manage booth this morning.

Their product encapsulates many of the vagaries of the IC development flow into a configuration management tool.  The backbone of the tool can be customized to the customer’s specific flow via scripts, and it provides a real-time updated HTML based view of what engineers are up to as project development unfolds.

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DAC Report from Gabe Moretti:

Power Management and IP

Moscone South is all about IP and low power.  This is the 51st DAC and my 34th.  Time flies.  The most intimidating thing is that the Apple Developers Forum is going on at the same time, and they have TV trucks and live interview on the street.  We of course do not.  It was nice to hear Antun Domic as one of the two keynote speakers this morning  His discussion on how the latest EDA tools are used to produce designs fabricated with processes as old as 180 nanometers was refreshing.  In general people equate the latest EDA tools with the latest semiconductor process.  Yet one needs to manage power even at 180 nanometers.

Chip Estimate runs a series of talks from IP developers in its booth.  I listened to Peter Mc Guiness of Imagination Technologies talk about advances in image processing.  it was interesting to hear him talk about lane departure warning as an automotive feature employing such technology.  Now I know how it works in one of my cars.  On the other hand to hear how the retail industry is planning to use facial recognition to choose for me what I should be interested in purchasing is not so reassuring.  But, on the other hand, its use in robotics applications is fashinating.

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DAC Report from John Blyler:

I. IP Panel: The founders for several successful private IP companies shared their experiences with an audience of near 50 attendees. The panelist included CAST, IPExtreme, Methods2Business, and Recore Systems. The main takeaways were that starting an IP company takes passion and a plan.  But neither will work if you don’t have some product to offer and a few key relationships in the industry. (Warren said you need 3 key customers to start.) I’ll write more about this panel later. Here’s a link to a pre-DAC position statements from the panelist.

II. NI and Cadence – The Best of Both Worlds

George Zafiropoulos, VP, Solutions Marketing at National Instruments (NI)-AWR, has brought his many years of chip design and verification experience from the EDA industry to NI. He spoke at the DAC Cadence Theater about post- and pre-silicon verification being the best of both worlds. Those worlds consist of NI, which has traditionally been used for post-silicon verification testing, and Cadence, which is known for pre-silicon design and verification. George has proposed the use of NI test hardware and software to do pre-silicon verification in combination with Cadence’s emulation tools, i.e, Palladium. This proposed combination of tools elicited many questions from the audience who were more familiar with the pre-silicon tools than the post-silicon testers. Verification languages were an issue for those who had never used the Mindstorm or other NI graphic tools suits. I’m sure we’ll learn more on this potential partnership between NI and Cadence tool suites.

III. Visionary Talk by Wally Rhines, CEO, Mentor Graphics (prior to the afternoon keynote):

The title described it all; “EDA Grows by Solving New Problems.” Wally’s vision focused on how EDA industry will grow even with the constraints on its relatively flat revenue. As he noted back in the 2004 DAC keynote, the largest growth with EDA tools is associated with the adoption of new methodologies, e.g., ESL, DFM, and FPGAs. Further, tools that support new methodologies have been the main drives of growth in the PCB and semiconductor worlds.

“EDA need to tap into new budgets … for emulation, embedded software … and in new markets,” explained Rhines. “The automotive industry is at the same stage of development as was the chip design industry in the 1970s. Their development process will have to be automated and with new tools.”

Another growth market will be hardware cyber security.

Target Breach Highlights IP Indifference

Wednesday, January 29th, 2014

The good news is that large amounts of IP go into the design of smart-card chips and RFID tags. The bad news is that the general public isn’t really interested.

Read the story on the “IP Insider.”

DAC – Video Latency; Platform as a Service; 262626; and ARM-12

Tuesday, June 4th, 2013

My Tuesday at DAC involved CAST IP, Mentor Graphics, Dassault Systemes, Chipestimate.com, and Globalfoundries-ARM. 

Here are but a few of the companies, hallway discussions, and presentations that I enjoyed during Tuesday at DAC:

> Performance is a function of latency and power, as Gary Smith noted in his pre-DAC EDA and IP trends presentation. One example of the need to balance latency and power is in the application of real-time video streaming (e.g., H.264 video encoders). Latency is the delay that occurs between the processing and transmission of live video. A simple way to initially gauge latency is by waving your hand quickly in front of the camera and watching for blurring of the image on the display. I saw none during my demo.

 

Other news from CAST highlighted a joint announcement with IP company Beyond Semiconductor concerning an ultra-low-power, 32-bit BA21 embedded processor.

 

 

 

> Hallway chat with Mentor’s M&A expert, Serge Leef:

Software as a Service (SaaS) for EDA cloud-based applications seems passé. Platform as a Service (PaaS) is the new “black.” The key driver in this change seems to be the push by next-generation chip designers for a more robust user experience (UE; see “Experience Required,” http://chipdesignmag.com/sld/blog/2013/05/30/experience-required/). Serge sees the trend to user-experience designs as essential to the evolution of EDA tools. He even believes them to be a source of revenue in terms of a micro-business model.

 

> Dassault Systemes offered several interesting technology demos. While their Netvibes product provides for intelligent dashboarding, Tuscany’s PinPoint enables tracking progress from synthesis to GDSII.

http://www.tuscanyda.com/

> IP protection and management includes the synchronization of databases and documentation. In this way, a close partnership with Magillem is proving very useful. (More about this in the near future.)

> Simulation Lifecycle Management (SLM) for semiconductor verification and validation (V&V) flows may evolve quickly into a framework. The effort in the automotive industry via ISO262626 may establish a working model for the EDA industry.

 

> Globalfoundries presentation at Chipestimate.com, “IP Talks” – Subi Kerngeri, VP of the Advanced Technology Division, talked briefly about many things, mostly centering on the need to offer a combination of device technology design and SoC manufacturing expertise.  But this need is fraught with challenges. (Reference: “Modular FinFET Increases Planar-to-Non-Planar IP Reuse”)

http://www.chipestimate.com/blogs/IPInsider/?p=1264   He noted that Globalfoundries was the first fab to optimize for the newly announced ARM Cortex-A12 CPU – POP IP combined with Globalfoundries’ 28-SLP process. Also, Kerngeri emphasized the success of Fully-Depleted SOI technology at 28 nm, saying that it was pretty much like bulk CMOS for designers. STMicro is their partner in FD-SOI. This technology has enabled 0.63 v at 1-GHz performance in a dual A-9 implementation.

 

 

 

 

Semiconductor Leaders Respond at Common Platform Technology Q&A

Friday, March 8th, 2013

Will Extreme Ultraviolet (EUV) lithography ever come to pass? When will nanotube technology hit the market? Will the cost of chips continue to go down? These were just a few of the questions covered during the press lunch at the 2013 Common Platform Technology Forum. The panelists included (seated, left to right): Michael Cadigan, General Manager of IBM’s Microelectronics Division; Gary Patton, VP, IBM’s Semiconductor R&D Center; KH Kim, Executive VP for Samsung Electronics’ Foundry Business; and Mike Noonen, Executive VP of Global Sales and Marketing for GLOBALFOUNDRIES. What follow are excerpts of that discussion.

Question: When will nanotube technology hit the market?

Patton: FinFET structures will last a decade, maybe longer. Moving beyond silicon to III-V materials will also help to extend existing designs. (Editor’s note: The III-V compound semiconductors come from combining group III elements (essentially Al, Ga, and In) with group V elements (essentially N, P , As, and Sb) of the periodic table. This results in 12 possible combinations. The most important ones are probably GaAs, InP, GaP, and GaN.)

Question: Will EUV ever come to pass?

Patton: EUV requires real physics changes. At the recent SEMI Industry Strategy Symposium (ISS), someone said that EUV is hard work. No, it is hard physics. The industry is trying to extend immersion and double patterning, but  no one wants to move to quadruple patterning.

Question: What does “hard physics” mean? The scientific effort is 20% while the engineering portion is 80%?

Patton: I’ve never attached a percentage to it. Perhaps it would be 60% science and 40% engineering effort.

Cadigan: We had envisioned the entry point for EUV at the 10-nm-node geometry. Now, that point is 7 nm. If anyone has seen ASML’s EUV tool, they know it’s really tough.

Question: If you don’t have EUV at 7 nm, will you need triple or quad patterning?

Cadigan: Yes, we always have an alternative. For example, fully depleted (FD) silicon-on-insulator (FD-SOI) was ready at about the same time as FinFET technology. If FinFET had been late, FD-SOI was the backup plan.

Question: Costs continue to rise for chip design and manufacturing. Will Moore’s Law end soon?

Noonen: Cost is where the rubber meets the road. Fabs must make money, but need to offer designers the right mix of power, performance, and cost (i.e., they must right-size to the right solutions). This goes beyond one metric, beyond a geometry.

Question: Lowering the cost of chips is a maturation of process. Is that maturation taking more time?

Noonen: We are working on 28-nm to 14-nm geometries all at once, accelerating the process to bring forth multiple nodes. This is breaking the typical two-year duty cycle between nodes from previous years.

Cadigan: I use the phrase time-to-market (TTM) instead of maturation. Our partners want earlier involvement to bring their technology to market at a faster pace. The model is shifting in 2013 – we all must work faster. For us (IBM), that shift means moving more quickly from the Albany facility to Fishkill to our customers to shorten the time for development – and hence TTM.

Science is nice, but cost is critical. We need to drive the cost out of the technology. For example, we are leveraging what we learn in Fishkill – which is not high-volume –  along with Globalfoundries and Samsung to leverage the total cost point.

Question: Will 450-mm wafers be available in the latter part of this decade?

Cadigan:  The Global G450 Consortium now has a consensus that 450 mm is happening. But I don’t know the timing of 450 mm. Volume production will probably come at the end of the decade. The challenge is that the timing of 450-mm wafers will depend upon lithography technology – back to the EUV question. But EUV will come to market for both 300 mm and 450 mm (see “CNSE Readying NFX Fab for G450C, EUV Efforts”).

Question: Will the tools at 10 nm reduce the need for triple and quadruple patterning?

Patton: We’ve extended immersion for a long time. Programmable light-source work is ongoing with ASML. Directed self-assembly (DSA) could be used to avoid quadruple (4) patterning.

Question: Broadcom’s CEO is quoted as saying that the benefits for cost on scaling will not continue. Cost benefits of scaling have gone away. Do you agree?

Patton: Comparisons between 20-nm to 14-nm nodes are not good, since those are not full nodes. You need to compare cost scaling between full nodes. In the past, 50% scaling provided 20% cost savings. Those ratios will change.

Question: The original idea of the Common Platform Alliance was to share fabs. Is that still possible?

Cadigan:  That was the original idea – release a design into two different fabs using the same kits (PDKs). As we evolved, we realized that only a few companies would do that. Samsung will tune its process slightly off of our common platform base. Or Globalfoundries will have one or two large clients who want a tuning. Our goal is still common-based foundational content. Now, it’s okay to personalize it.  That’s why we are doing more in Albany instead of Fishkill.



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Modular FinFET Increases Planar-to-Non-Planar IP Reuse

Friday, January 11th, 2013

At IEDM, Globalfoundries explained why its 14-nm-class Fin with a 20-nm back-end combination would increase planar IP portability to non-planar FinFETs.

Often, the best questions are asked and answered after the main event. A case in point was the press roundtable that convened after Globalfoundries CEO Ajit Manocha’s luncheon keynote during the 2012 International Electron Devices Meeting (IEDM). Manocha (center seat) was joined by the following senior executives: Suresh Venkatesan (left seat), Senior Vice President of Technology Development, and Subramani Kengeri (right seat), Vice President of Advanced Technology Architecture (see Figure 1). What follows is an edited version of that question-and-answer session. – JB

 

Figure 1: Pictured are the Globalfoundries CEO and senior executives at the IEDM press roundtable. Jason Goross, Communications Manager, is shown standing.

Question: What about new technologies, like Extreme-Ultra-Violet (EUV) lithography and directed self-assembly?

Manocha: We’re working on EUV technology as well as immersion scanners for double patterning (see Figure 2). The jury is still out on commercial EUV, especially since suppliers remain 9 months or so out.

We are not working on directed self-assembly (DSA; a manufacturing process to improve both optical and EUV). Thus far, it is not a prime consideration for 7-nm-node technology. However, we have been talking with KLA-Tencore as part of our open collaboration approach to deciding the right thing to do.

As I mentioned in my keynote, at least one big company (IDM/foundry) is under 50% utilization capacity. We need a way to keep it going by living on 28-nm with silicon-on-insulator (SOI) and other technologies.

Figure 2: In his IEDM 2012 keynote, Globalfoundries CEO Ajit Manocha talked about the challenges facing the semiconductor manufacturing industry.

Question: Is Globalfoundries FinFET-friendly?

Manocha: We are mitigating the risk of mobile systems-on-a-chip (SoCs) by incorporating a 20-nm back end with a 14-nm front end.

Kengeri: Globalfoundries wants to leverage all of its 20-nm investment. That includes reusing models on the technical side. For example, there are 7000 ground rules. We want to carry those rules over, only changing the device. On the design side, people are used to 20-nm design rules. We want to keep that design infrastructure.

Editor’s Note: As announced in Sept. 2012, GlobalFoundries is taking a “modular Fin” approach with its bulk FinFET offering, dubbed 14nm-XM (see Figure 3). This approach combines a 14-nm-class Fin with its 20-nm back-end-of-line (BEOL) interconnect flow. It includes  ‘Fin-Friendly Migration’ (FFM) rules to allow the fast porting of planar intellectual- property (IP) designs to FinFET. The company predicts 40% to 60% improved battery life and 20% to 55% higher performance (depending on operating voltage) vs. other 20-nm, 2D planar transistors. (See “GlobalFoundries Rolls Out 14nm finFET Process.”)

Figure 3: Shown is Globalfoundries' 14nm-XM FinFET structure.

Question: Regarding the IP side, won’t changing the device cause changes in the IP?

Kengeri: Yes, we do need to redo the IP (for 14nm-XM), but not as much as before.  We don’t need the 2x change that is traditionally needed between major node jumps. There is where the ecosystem engagement comes in. The IP is being designed because the 14nm-XM design kit (PDK) is already complete.

In addition, there is concurrent IP development within our ecosystem (e.g., ARM), since the physical design rules are already there.

Venkatesan: Let me add a quick comment. We have done the physical design, electrical characterization, and optimizing of the IP.  The physical design rules for 20 nm are complete, so the IP development has started. IP developers can be assured that no big changes will happen. There may be changes in the electrical characteristics, but that just needs retiming, etc. – not the same level of pain and suffering as the PDK development. [Note: The PDK contains descriptions of the basic building blocks of the process including FinFET (Spice) models, advanced extraction,  double patterning, DFM, FFM, Ref flows, P&R…]

Editor’s Note: In this short video, Sean O’Kane from Chipestimate.TV and I talk with ARM’s John Heinlein about the coming challenges faced by IP designers using FinFET structures.

TSMC OIP 2012: ARM’s John Heinlein is interviewed about IP and FinFETs.

Originally published on “IP Insider.”


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STMicroelectronics Pushes SOI While Leaving the Mobile Space

Thursday, December 20th, 2012

Why is one of Europe’s leading semiconductor IDMs pushing into leading-edge, 28-nm FD-SOI technology while leaving a market where such technology might be useful?

It was a chance meeting that made me wonder about two recent announcements from one of the world’s largest semiconductor companies.

Last week, I attended an IEDM briefing in which STMicroelectronics presented silicon-verified data to further confirm the manufacturability of its 28-nm Fully Depleted Silicon-on-Insulator (FD-SOI) technology (see “FinFETs or FD-SOI?“). Ed Sperling, Editor-in-Chief for SemiMD, summed it up this way:

“What’s particularly attractive about FD-SOI is that it can be implemented at the 28-nm node for a boost in performance and a reduction in power. The mainstream process node right now is 40 nm. And while Intel introduced its version of a finFET transistor called Tri-Gate at 22 nm, TSMC and GlobalFoundries plan to introduce it at the next node—whether that’s 16 nm or 14 nm. That leaves companies facing a big decision about whether to move all the way to 16/14 nm to reap the lower leakage of finFETs, whether to move to 20 nm on bulk, or whether to stay longer at 28 nm with FD-SOI.”

Joel Hartmann, Executive VP Front-End Manufacturing & Process R&D, STMicroelectronics, presents SoC-level, 28-nm Planar Fully Depleted silicon results at IEDM 2012.

I didn’t realize until later that week, but – on the same day as its 28-nm FD-SOI technology announcement – STMicroelectronics stated that it would curtail its presence in the mobile-handset space via the Ericsson partnership. As Chris Ciufo noted in his “All Things Embedded” blog, Ericsson will remain in only two market domains: Sense and Power and Automotive as well as Embedded Processing. “For the former, device categories include MEMS, sensors, power discretes, advanced analog, automotive powertrain, automotive safety (such as Advanced Driver Assistance Systems [ADASs]), automotive body, and the red-hot In-Vehicle Infotainment (IVI) category,” wrote Ciufo.

In the embedded processing market, the company will “focus on the core of the electronics systems” and ditch wireless broadband. Target areas include microcontrollers, imaging, digital consumer, application processors, and digital ASICs.

Considered together, these two announcements beg the following question: If STMicroelectronics is only interested in the sensor, automotive, and “embedded” markets, why does the company need to work at leading-edge process nodes – like 28 nm on FD-SOI? This question arose during a recent chance meeting with Juergen Jaeger, Sr. Product Manager at Cadence Design Systems.

Jaeger suggested a possible answer by noting that Moore’s Law generally provides a cost savings with power and performance benefits at lower processing nodes. “This makes sense for both automotive infotainment and networking technologies,” explained Juergen. “But it doesn’t make too much sense for gearbox, engine, anti-lock brakes, or steering systems, since they need high reliability and tolerance.” Those requirements tend to restrict devices to fully tested, high-node geometries.

Jaeger reminded me that infotainment systems-on-a-chip (SoCs) are very complex devices requiring integrated network and wireless systems – in addition to an array of audio/video codecs that must drive multiple LCD screens within today’s cars.

Additionally, STMicroelectronics’ move to FD-SOI is one way to mitigate the risk facing leading-edge bulk CMOS processes. As Sperling observed, “At 28 nm and beyond, however, bulk has run out of steam, which is why Intel has opted for finFETs.” Meanwhile, FD-SOI offers power and performance benefits while staying on today’s planar-transistor manufacturing processes.

In the end, the push toward FD-SOI technology at exiting 28-nm nodes may play well into a number of low-power and high-performance chip markets. This is not a path without risk. But it does highlight the accelerating convergence of SOI and bulk CMOS at leading-edge nodes. And it should strengthen STMicroelectronics’ strong position in the automotive infotainment space.

Originally posted on “IP Insider.”

SOI Parity with CMOS Good News for IP Designers

Friday, July 13th, 2012

Soitec panel at Semicon West challenges both the IDM model and the dominance of bulk CMOS as material of choice for chips at 20 nm process nodes.

(Originally posted on “IP Insider“) During Semicon West 2012Soitec hosted a panel and celebration event to mark their 20th anniversary. The company and the Silicon-on-Insulator (SOI) industry as a whole had a great deal to celebrate with the onset of 20nm process node technology for System-on-Chip (SoC) design.

At the 20nm node, companies are looking to fully depleted (FD) SOI to match or even exceed parity with bulk CMOS in many areas, including power and physical effects. This parity, as applied to the future of mobile computing, was the subject of a lively panel that preceded Soitec’s celebration event. The panel consisted of well-known experts from UC Berkeley, IBM, ARM, GlobalFoundries, STMicroelectronics, the SOI Consortium and Soitec. (see, “SOI Becomes Essential At 20nm”)

Why is SOI finally a real alternative to bulk CMOS at 20nm? A recent SOI Industry Consortium benchmarked 28nm bulk vs. 28nm FD-SOI to compare silicon with similar processor (ARM) and memory controller IP blocks. The comparisons demonstrated that FD-SOI was comparable with the leakier ‘General Purpose’ technology, at better dynamic power, and dramatically better leakage power. (STMicroelectronics has a white paper )

What would be the impact to semiconductor intellectual property (IP) designs that move to fully depleted two-dimensional (FD-2D) SOI from traditional CMOS chips? Negligible, explained Steve Longoria, SVP of global strategic business development at Soitec. The FD-2D process uses existing IP libraries and design tools, so no changes in any of the fabless companies IP are needed. Further, Longoria notes that FD-2D is compatible with planar CMOS production lines, which mean no new equipment costs or retaining of staff.

Will the advantages of FD-SOI spell the end of bulk CMOS at lower process nodes? Probably not, as designers find new ways to work around power leakage and other challenges. But having an alternative should only encourage more innovation in the race to keep pace with Moore’s law.

Soitec’s 20th Anniversary Event in Pictures and Tweets

(Post during the event by jblyler @Dark_Faust)

Systems, Software and IP Merge at DAC

Monday, June 4th, 2012

Here’s the first day of DAC, captured in pictures and captions.

 

Interview with Globalfoundries about AMD-ATI

Thursday, March 22nd, 2012

John Blyler, editor-in-chief for Chip Design magazine, interviews Mike Noonen, Sr. VP of Worldwide Sales and Marketing at GLOBALFOUNDRIES during the Common Platform Technology Forum 2012 (courtesy Chipestimate.com TV).

As Summer Ends, Events Begin

Friday, August 27th, 2010

Ready or not, summer is symbolically nearing an end with the coming of the Labor Day weekend. But for those of us who cover high tech, there is one other activity that marks the end of the sunny season: a sudden, sharp increase in technical conferences.

Below are just a few of the upcoming shows for September:

Look for coverage of these show in Chip Design and our community portal – System Level Design and Low Power Engineering. Until then, I hope you enjoy the last few symbolic weeks of Summer 2010.

“Summer’s lease hath all too short a date.” -   William Shakespeare