Part of the  

Chip Design Magazine

  Network

About  |  Contact

Posts Tagged ‘EDA tools’

How can the Chip Community Improve the Industry for IOT Designers?

Monday, March 13th, 2017

Meeting the 20 billion IOT devices prediction by 2020 will require the semiconductor industry to streamline its processes for up and coming chip designers.

By John Blyler, Editorial Director, IOT Embedded Systems

Part I of this article covered the difficulties in designing System-on-Chip (SOC) devices for the Internet-of-Things (IOT) market, as explained by Jim Bruister, CEO of SOC Solutions, during his talk at the inaugural REUSE event. In Part II, we will examine ways for the semiconductor and electronics industries to improve the development process for the next generation of IOT designers. — JB

Quotable  Quotes:

  • … the semiconductor community needs to market outside of its traditional channels, for example, to the “Field and Stream” or perhaps the “Sports Illustrated” communities.”
  • … licensing agreements represent a real problem for buyers especially those that must buy IP from multiple vendors.
  • … a general contractor type of person is needed for the emerging IOT design industry.
  • … (could) open source be used to get IOT designers started especially with FPGAs? 

How, then, do we improve as an industry to ensure success for IOT chip designers? Bruister believes there are 5 pieces that need to be in place. First among those is a proactive ecosystem, one that consists of more than just a few companies getting together and sharing their names on websites.

Secondly, the ecosystem must consist of IP providers, design houses and even the foundries whose goal is to offer real SOC reference designs for the IOT community.

Information marketing focused on the IoT business channels is the third needed item. Bruister emphasized that the semiconductor community needs to market outside of its traditional channels, for example, to the “Field and Stream” or perhaps the “Sports Illustrated” communities. The semiconductor world needs to reach out to those places where the next generation of SOC designers will live.

Fourthly, a general contractor type of position is needed in the IOT SOC ecosystem. By analogy, a general contractor is the person that helps you build a house. The general contractor has the experience and connections to bring in and coordinate the activities of the framer, electrician, plumber and others needed to build a house. The same type of person is need for IOT designers.

At this point in the presentation, an attendee from the audience noted the general contractor should probably own all of the tools for the “building of a house” analogy to work. Bruister looked at the problem differently, explaining that the general contractor for a house doesn’t typically own all the tools.

“I see the general contractor (for IOT design) more like a consultant that selects the design house and helps you pick the IP,” explained Bruister. There are design houses that play that role, but it’s not a smooth flow of activities from start to finish for doing an IOT design. That’s where I think a general contractor or coordinator could help.”

The last thing needed for improvement in the IOT design process was one stop shopping with a common licensing model. Today, there is no standard licensing model and there will probably never be one, said Bruister. But the licensing agreements represent a real problem for buyers especially those that must buy IP from multiple vendors. Current models take way too long to license the IP, get it in-house and evaluate the IP. There needs to be a consolidation on how IP is licensed. Bruister suggested a boiler plate IP license that could contain 90% of the common elements required in a license.

Bruister concluded by saying that the semiconductor industry needs to figure out a way to simplify the whole IOT design process. This statement prompted a question about the use of open source tools and IP as a possible solution. The questioner noted that open source could be used to get IOT designers started especially with FPGAs.

Bruister wondered if there were enough open source folks that would significantly help with the 20 billion predicted IOT devices by 2020. Nikos Zervas, CEO of CAST, who was in the audience, noted that relying on open source may be problematic with the millions of dollars involved in chip design. He question who would stand behind the open source tools in such a case.

But the questioner was persistent, saying that even major chip IP providers like ARM don’t pay for the blunders of the chip designer. He cited software as another example were nothing is really warranted, in his opinion.

Bruister tried to address the question by looking at the big picture. For the coming IOT design challenges, there will be one camp of providers who believe that one hundred different designs types will be good for all devices. The opposing camp will believe that each design situation will require some customization, e.g., to include energy harvesting capabilities, etc. Both groups will be large and vocal. The IOT device market will be so big that it will have lots variability.

“But the common thread is that it takes way too long to design IOT devices,” said Bruister. “There is no way we can reach that many devices with such a long design and long IP licensing processes. Expensive tools are always going to be an issue. I don’t think you can get away from that unless the big EDA vendors decide to go with a “pay as you design” model. They have resisted that for years.”

It may be difficult to simplify the process for less SOC experienced IOT designers, but we must try if the IOT market is to realize it’s potential.

Has The Time Come for SOC Embedded FPGAs?

Tuesday, August 30th, 2016

Shrinking technology nodes at lower product costs plus the rise of compute-intensive IOT applications help Menta’s e-FPGA outlook.

By John Blyler, IP Systems

 

The following are edited portions of my video interview the Design Automation Conference (DAC) 2016 with Menta’s business development director, Yoan Dupret. – JB

John Blyler's interview with Yoan Dupret from Menta

Blyler: You’re technology enables designers to include an FPGA almost anywhere on a System-on-Chip (SOC). How is your approach unique from others that purport to do the same thing?

Dupret: Our technology enables placement of an Field Programmable Gate Array (FPGA) onto a silicon ASIC, which is why we call it an embedded FPGA (e-FPGA). How are we different from others? First, let me explain why others have failed in the past while we are succeeding now.

In the past, the time just wasn’t right. Further, the cost of developing the SOC was still too high. Today, all of those challenges are changing. This has been confirmed by our customers and from GSA studies that explain the importance of having some programmable logic inside an ASIC.

Now, the time is right. We have spent the last few years focusing on research and development (R&D) to strengthen our tools, architectures and to build out competencies. Toolwise, we have a more robust and easier to use GUI and our architecture has gone through several changes from the first generation.

Our approach uses standard cell-based ASICs so we are not disruptive to the EDA too flow of our customers. Our hard IP just plugs into the regular chip design flow using all of the classical techniques for CMOS design. Naturally, we support testing with standard scan chain tests and impressive test coverage. We believe our FPGA performance is better than the competitions in terms of numbers of lookup tables per of area, of frequencies, and low power consumption.

Blyler:  Are you targeting a specific area for these embedded FPGAs, e.g., IOT?

Dupret: IOT is one of the markets we are looking at but it is not the only one. Why? That’s because the embedded FPGA fabric can actually go anywhere you have RTL, which is intensively parallel programming based (see Figure 1). For example, we are working on a cryptographic algorithms inside the e-FPGA for IOT applications. We have tractions on the filters for digital radios (IIR and FLIR filters), which is another IOT application. Further, we have customers in the industrial and automotive audio and image processing space

Figure 1: SOC architecture with e-FPGA core, which is programmed after the tape-out. (Courtesy of Menta)

Do you remember when Intel bought Altera, a large FPGA company? This acquisition was, in part, for Intel’s High Performance Computing (HPC) applications. Now they have several big FPGAs from Altera just next to very high frequency processing cores. But there is another way to do achieve this level of HPC. For example, a design could consists of a very big parallel intensive HPC architecture with a lot of lower frequency CPUs and next to each of these CPUs you could have an e-FPGa.

Blyler: At DAC this year, there are a number of companies from France. Is there something going on there? Will it become the next Silicon Valley?

Dupret: Yes, that is true. There are quite some companies doing EDA. Others are doing IP, some of which are well known. For example, Dolphin, is based in Grenoble and it is also part of the ecosystem there.

Blyler: That’s great to see. Thank you, Yoan.

To learn more about Menta’s latest technology: “Menta Delivers Industry’s Highest Performing Embedded Programmable Logic IP for SoCs.”