JB’s Circuit

OK, I’ve just got to get this off my mind: What is a workable definition of a blog? Or more to the point, when is a blog not a blog?

Consider the following:

> John Cooley now labels his compilations (insightful as they are) as a “blog.” Yet John himself didn’t really think he was a blogger during the discussion at the recent DaC’08 Blogger BoF.

> Just found out that Cadence has a blog site with a ton of bloggers. When did that happen? (Personal note to Cadence: Your registration process for blog commenters is too lengthy and cumbersome. Compare it to Synopsys, which has been going for the last year or so and is very easy to leave comments.)

What’s my point? It’s the point I was trying to make at the Dac Blogger BoF event, namely: What is the basic definition, the minimal acceptance criteria for a blog site? Simple enough question, but difficult to answer since it spawns a number of related questions such as:

> Is a blog just the aimless ramblings of its author, or is it a vehicle for the free exchange of ideas without filtering or compilation and in a timely manner?

> What is the difference between a company blog and a blog on an independent publishing site (such as Chip Design or EDN)? Yes, there really is a difference.

Well, that’s all for now. I feel much better for getting this down. Been on my mind for a while. Nite, all.

The question often begins as follows: “Do you know of any ESL-like tools that would apply to a larger system that incorporates mechanical, electrical, HW, and SW.”

Great question! One that probably can not be answer by an EDA person, or anyone else that has a niche view. Likewise, it’s not a question that can be answered by the high-level, domain-independent tools, that is, System Engineering Tools like Slate, Core, Doors, etc. It’s analogous to the challenges - in our EDA world - of linking the worlds of algorithmic and RTL development. It’s a problem of too many layers of abstraction.

In the case of high level systems engineering tools like Slate, Core, and others, the problem is that all you can do at such a high level is establish an overall architecture then drill down with point tools for rqmts, hw-sw partitioning, etc. This was one of the problem that I faced many years ago while working for the DoE superfund clean-up site: How to go from a very high level problem discussions and perceptions from stakeholders, general public, lawyers, etc, to a traceable/verifiable solution implementation in hardware, software, peopleware, mechanical systems, etc. I should really talk more about that experience, since it’s very applicable here. But I don’t want to stray too far afield for this blog entry, that is , I want to focus on implementations that result in HW and SW.

To that end, earlier this year I directed my iDesign editor (Clive Maxfield) to focus exclusively on chip-package-board issues, more from an electronics viewpoint than a hw-sw division. Max wrote a great piece to initiate the new chip-package-board direction for iDesign.

This issue of subsystem views and tools (i.e., chip vs board vs module vs complete product) remains a challenge. EDA companies like Cadence, Synposys and Mentor are all trying to find ways to address chip-package-board level designs, but this is already the domain of big companies like Autodesk and Dassault Systems, among others:

“An acquisition of Cadence by AutoDesk - makers of AutoCAD - does make sense. Cadence makes several good point tools that would complement AutoCAD’s existing product engines, e.g., in the aircraft, automotive and multimedia markets. AutoCAD has all the 3D modeling, rendering and packaging tools that are coveted by the major EDA companies. AutoCAD is truly a big fish with around $4 ½ B in sales and a market cap of $9B. This makes AutoCAD roughly four times the size of Cadence. So an acquisition of Cadence makes both technical and financial sense.”

The problem of chip-package-board design is a big one - bigger than ESL. But the need for a solution is just as pressing. Any thoughts?

“Beauty is in the eye of the beholder” — Greek, 3rd century BC

The pictures of the impurities that cause chip failures can be amazing. Below is a sample of an AL-based flower like crystalline impurity. For more, visit the IEEE Online - The Art of Failure.

My former publisher, Penton Media, continues to struggle through the challenges that are facing all publishers: “John French released an internal memo today announcing that he is stepping down as CEO of Penton Media.”

Recently I learned that RF Design magazine folded - part of the consolidation of pubs after the Prism purchased Penton last year. This consolidation made sense as RF Design magazine competed with Penton’s Microwaves and RF book. Hope that Ashok Bindra, the Editor-in-Chief of RD Design, has been able to find work.

Also note that Dan Harris, the digital editor at Electronic Design, has also left Penton.  And so the collective editorial talent pool continues to decline - not a good sign for the industry or the engineers that rely on independent technology and news coverage.

On a happier note, I see that Nancy Friedrich - my old friend and colleague at Penton - has become the Editor-in-Chief of Microwaves and RF magazine. Believe that the former EiC of the pub - Jack Browne - is still around as well. Congrats, Nancy!

Well, not quite - but close. Here’s what I mean: Software virtual prototypes can be used to verify hardware designs before the hardware even exists. So what, you say? That’s been possible for years. But did you know that newer virtual models allow the software engineers to tweak memory size and processor-memory interconnects in order to optimize their applications run time and power usage. These “tweaks” can then be fed-back to the hardware team to optimize the SOC - before the SoC has been produced. Before the first respin!

For a case in point, consider Virtutech’s recent announcement concerning the Freescale QorIQ P4080 multicore process, one that won’t even be available until later this year. Virtual models of the processor SoC, created using Virtutech’s Simics tool, are being used now by direct processor customers and even their customers. The feedback from these software teams will help verify and even change the design of the final SoC.

Thanks to Michel Genard, Virtutech Vice president of Marketing, for explaining the importance of this emerging process in the hardware-dominated world of EDA tools and chip design. Watch for more coverage soon.

Did you know there is an active open source CAD community? Not freeware or shareware CAD programs, which have been available for some time, but Open Source CAD community! Very cool site, with lots of applications for electronics design that include: schematic capture, bill of materials generation, netlisting, analog and digital simulation and PCB layout. The apps are released under the terms of the GNU General Public License.

[Interesting note: I started using GNU software back in 1995 with a lovely little program called “Ghostscript.” Anyone remember Ghostscript?]

BTW: Don’t get excited when you visit the Open Source CAD website and see the term gEDA. It doesn’t mean chip level design tools, as in Cadence-Mentor-Synopsys equivalent – just board-level tools. Which shouldn’t be surprising, since a quick surf over to Wiki reminds us of the true meaning of EDA:

Electronic design automation (EDA) is the category of tools for designing and producing electronic systems ranging from printed circuit boards (PCBs) to integrated circuits. This is sometimes referred to as ECAD (electronic computer-aided design) or just CAD.

Why am I mentioning this bit of trivia? To call everyone’s attention – especially local Portland Tech’ers – to the following presentation at next week’s Open Source Conference (OSCON):

“Creating Open Source Electronic Hardware with Open Source Software”
Tom Anderson (Agilent Technologies)
11:35am - 12:20pm Friday, 07/25/2008
Tom Anderson works as a design automation scientist for Agilent Technologies. His current work project is to invent new circuit simulation capabilities for Agilent engineers. On his own time he builds electronics projects and is an author for MAKE magazine, and creates Open Source Hardware for Quaketronics.
See you there!

The problem with hostile take-over attempts is that they expose the aggressor to (perhaps) unwanted attention. I’ll explain the “perhaps” emphasis shortly. But first, consider this scenario which was shared with me by a friend on the financial side of this misadventure.

Cadence is trying to forcibly acquire Mentor. Others are debating whether the move is based on business strategy – namely, to acquire Mentor’s very profitable Calibre tool product line – or to distract Cadence’s investors from recent disappointing earnings. Regardless, the takeover bid has exposed Cadence’s financial position to the larger investment and corporate world.

Some big players in the investment market are now wondering if a bigger fish, like AutoDesk or Dassault Systèmes, will make a play for Cadence. Here’s the reasoning: Cadence had to show their hand in order to make the bid for Mentor. While strong in some regards, Cadence’s financial position is not as firm as many might think. From a financial standpoint, they are under-performing. Twice this year they have pulled back their estimates and are currently revising their guidance for the rest of the year. Perhaps most telling was that Cadence seemed to lack enough of their own cash reserves to secure the $1.6B take-over price offered to Mentor. Apparently, the company is floating $1.1B of the $1.6B by way of a bond aimed at off-shore investors. If true, that means that Cadence is using only $500m of its own money for the takeover.

Now, $500 million is still a nice chunk of walking-around money. Plus Cadence has a reasonably healthy client base. The cash flow needs some help, but that can be improved – in the short term by a take-over of Mentor. All of these factors are catching the attention of several big multinational firms, like AutoDesk and Dassault Systèmes. The big ERP companies – such as SAP or Oracle – are less likely to be interested in EDA companies like Cadence since they already make a mint from the semiconductor fab side of the market.

An acquisition of Cadence by AutoDesk - makers of AutoCAD - does make sense. Cadence makes several good point tools that would complement AutoCAD’s existing product engines, e.g., in the aircraft, automotive and multimedia markets. AutoCAD has all the 3D modeling, rendering and packaging tools that are coveted by the major EDA companies. AutoCAD is truly a big fish with around $4 ½ B in sales and a market cap of $9B. This makes AutoCAD roughly four times the size of Cadence. So an acquisition of Cadence makes both technical and financial sense.

As I wrote before: This summer promises to be a “fun” time for the usually quiet world of EDA tools! Watch out Cadence.

In the last few days, I’ve run across several stories – one in the local paper and others in blogs – that seem to suggest that Mentor deserves no sympathy in its attempt to fend off the hostile takeover by Cadence since Mentor is itself in a hostile takeover bid for a smaller company called Flometrics. [BTW: Daniel Payne's "EDA Thoughts" blog first raised the issue of Mentor's attempted acquisition of Flowmetrics back in early May.]

This seems like an overly simplistic argument. Let’s face it: Like it or not, hostile takeovers are a way of life in a capitalistic market. They are just another business tool. Instead of focusing on such emotional issues as which company has the nicer CEO or the more engineering-friendly environment, serious journalists and bloggers should try to answer such questions as:

• Why is a hostile takeover technique being used? Have other options been exhausted?
• Why is the takeover being initiated now instead of 6 months ago?
• Is the goal of the takeover to secure market share or intellectual property that clearly fits into the business strategy of the aggressor company?
• Or is the takeover being used to hide diminished earnings or other financial problems, i.e., is the takeover a diversionary tactic to divert attention from a lack of innovation, decreased market share or price share of the aggressor?

Just because a company engages in hostile takeovers doesn’t make it a bad company… or a good one. What makes the aggressor a bad or good company is the reasons behind the takeover bid as well as the past history of similar takeovers.

Testing out the use of my new Flip camcorder. Small, light, very easy to use. In this clip - taken mid-way through the conference - I’m getting grief from Jenna Johnson, my marketing manager. Jenna was running the Flip while I talked to her and Karen Popp, our sales director.

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We can all share a collective sigh of relieve that Mentor has rejected the take-over bid from Cadence. In their response, Mentor’s CEO - Walden Rhines - cited reasons of undervaluation and risk of not gaining regulatory approval for rejecting the offer.

The web has been unusually busy this morning with every voice imaginable questioning the wisdom in Cadence’s take-over bid. Even Portland’s own business report - Aliza Earnshaw - has chimed in with comments directly from Mr. Fister.

Not all comments have been public ones. Several semi-private forums in which I participate have also been unusually active, like the Portland High-Tech google group. Here’s a few highpoints from that group:

I agree with both Daniel and Gabe. I can’t see how this merger is good for anyone and Cadence investors should be outraged. The product overlap is just too great.

Sadly, investors aren’t always known for making strategic business decisions. Many myopically follow the short term bottom line. Hope I’m wrong, since such an acquisition would spell the end of Mentor as we know it. - JB

For the sake of discussion, I’ll take a contrarian view. I agree from an organizational standpoint the merger could be bungled, and that similar past acquisitions have reduced employment. Given the recent struggles that both Cadence and Mentor have had to become profitable, though, one could argue that separately they would each be hemmhoraging jobs anyway, and that the combined company could be healthier in the long run.

I also wonder whether the comments about product overlap are overstated. Several of the product overlap areas noted in Daniel’s blog include area where either Cadence or Mentor has a razor-thin slice of the market share pie chart — e.g., Cadence is much bigger in custom IC design, and while Mentor dominates DRC. The big, honking areas of overlap are PCB design, logic simulation and emulation … and with PCB being one of the least profitable EDA businesses, would it be so bad for the combined company to hand off some of that business to someone else? One could make the argument that even in logic simulation that Mentor dominates FPGA but is a relatively small player in ASIC.

Having said all that, if I were a Cadence shareholder (and I’m not - for my job I don’t directly hold any EDA stocks), I’d be pretty uneasy about this. The disclosed excerpts from Mr. Fister’s letter lacked any specificity that would address a shareholder’s concerns.

[JB] Are both companies really “hemmhoraging” jobs?

[Anon] Maybe “hemmhoraging” is too strong a word, but I have heard of incremental layoffs at both companies over the last 3 months. I’m not aware of wholesale cuts of entire product development teams, though.

[JB] System-level design is another area were Cadence would benefit from acquiring Mentor, tho such tools don’t yet seem very profitable.
[Anon] Mentor has been investing in system design tools in various areas including ESL verification and synthesis. Due to Mentor’s financial reporting format it’s difficult to tell how much they make in this business — for instance, their “New & Emerging Products” category includes test products, embedded software, IP, etc. As for Cadence, they have appeared to steer clear of systems design for some time. Cadence licensed SPW to CoWare earlier this decade and since then has not announced any system design products that I’m aware of.