Archive for the 'The Profession' Category

Dec 12 2011

RF Telescope at Arecibo Picks up Dr. Who

Published by under The Profession

Yes – it’s a fake story. Still, it would be interesting to see the mathematics showing the reflected signal strength from 25 light years away.

Why is this story fake? As pointed out on Skeptic Friends, the first clue was the date: April 1 2009. Secondly, the story site looked like a BBC webpage the URL was hosted at rimmel.com, not BBC.

Still, I thought it was real enough to write the following post: “Set the Way-Back machine for 41 MHz, Mr. Peabody. I’m going to listen to 50 year old Dr Who reruns from 25 light years away! (Thx to Paula for pointing this out.)”

47 Year Old Television Signals Bouncing Back to Earth

“While searching deep space for extra-terrestrial signals, scientists at the Arecibo Observatory in Puerto Rico have stumbled across signals broadcast from Earth nearly half a century ago.”

It’s too bad that the story is fake AND that it cited Arecibo, an important U.S. assest that is struggling for funding. Here’s a story from my first visit to this remarkable and remote research facility: “Remote RF Telescope Bring Sci-Fi To Reality

RF Telescope at Arecibo, Puerto Rico.


 

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Oct 31 2011

Technology Gives Way to Spooky Readings

Published by under The Profession

Alright – I admit it! Last night wasn’t spent working on story about silicon manufacturing variability below 20nm. Instead, I snuck out with my better half and attended … must I confess? A poetry reading!

 

But true to the season, it was a soul satisfying recitation of terrifying tales with unexpected endings. The readers, well versed in their craft, were actors from the “Bag and Baggage” company. All told, it was memorable evening made all the better with the right company and a few goblets of Renaissance wine at Orenco Station.  What better way to prepare for tonight’s festivities on the eve before Hallowmas?

 

Although my time is timeless on this earth,
I still recall when days of gold turned cold
and how we all believed this new year’s birth
was eve that spirits roamed; bad ones grew bold!

 

 

Grisly Reminder

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Jun 30 2011

Blacker Boxes Lie Ahead

Published by under General,The Profession

Few pundits have addressed the system engineering development implications of the recent EDA and semiconductor company’s move toward platforms that include both chip hardware with associated firmware software.

Niche industries are notoriously myopic. They have to be, since excelling in a highly specific market segment usually requires a sharp focus on low-level details. A good example of a niche market is the semiconductor Electronic Design Automation (EDA) tools industry, that fine group of highly educated professionals who create the tools that allow today’s atom-sized transistors to be designed and manufactured.

The EDA industry has long talked about the importance of software (mostly firmware) as a critical complement to the design of processor-intensive hardware ASICs. While the acknowledgement of the importance of software is nothing new, it has only been in the last few years that actual hardware-software platforms have been forthcoming by the industry.

What does this trend really mean, i.e., the move to include firmware (devices drivers) in the System-in-Chip integrated circuits (ICs)? To date, the result is that companies offer a platform that contains both the SOC hardware and accompanying software firmware. In some cases, like Mentor, the platform also includes a Real-Time Operating System (RTOS) and embedded code optimization and analysis capabilities.

One could argue that this move to include software with the chips is an inevitable step in upward abstraction, driven by the commoditization of processor chips. Others argue that end users are demanding it, as time-to-market windows shrink in the consumer market.

But rather than follow the EDA viewpoint, let’s approach this trend from the standpoint of the end-user. I define the end-user as the Systems Engineer who is responsible for the integration of all the hardware and software into a workable end-system or final product (see figure). Note the big “S” in SE, meaning the system beyond the hardware or software subsystems.

The integration phase of the typical Systems Engineering V diagram is just as critical as the design phase for hardware-software systems.

What is the end-system or final product? It might be a digital camera or tablet; or perhaps a heads-up display for commercial or military aircraft; or even a radiation detector for a homeland security devicen. Regardless of the end system or product, the role of the Systems Engineer is changing as he/she receives software supported ICs from the chip supplier, courtesy of the EDA industry. In essence, the “black box” that traditionally consisted of a black package chip just got a bit blacker.

Some might say that the systems engineer now has less to worry about. No longer will the SE have to manage the hardware and software co-design and co-verification of the chip. Traditionally, that would mean long meetings and significant time spent in “discussions” with the chip designers and the firmware developers over interface issues. Today, that job has effectively been done by the EDA company and the chip supplier as the latest generation of chips come with the needed firmware, e.g., the first offering from Cadence’s multi-staged EDA360 strategy.

On the embedded side, the chip-firmware package might also include an RTOS and tools for software developers to optimize and analyze their code. Mentor is leading this area among EDA tool suppliers.

But how does this happy union of chip hardware and firmware affect the work of a module or product level SE? Does it make his/her job easier? That is certainly the goal, e.g., to greatly reduce co-design and co-verification issues between the silicon development and associated software while including hooks into upper level application development. Now, companies claim that many of these issues have been taken care of for a variety of processor systems.

One should note that these chip hardware-software platforms don’t yet really extend to the analog side of the business. This is hardly surprising since the software requirement is far less than on the digital processor side. Still, software is needed for such things as communication protocol stacks (thing PHY and MAC layers).

Yet, even on the digital side of the platform space, important considerations remain. How does hardware and software intellectual property (IP) fit into all of this? Has the new, higher abstracted blacker box that SEs receive been fully verified? The answer to this question might be partially addressed by the emergence of IP subsystems (“IP Subsystem – Milestone or Flashback“).

Other questions remain. How will open system code and tools benefit or hinder the hardware chip and firmware platforms? From an open systems angle, the black box may be less black but is still opaque to the System Engineer.

What will be the new roles and responsibilities for systems engineers during design and – perhaps more importantly – during the hardware and software integration phase? Will he/she have to re-verify the work of the chip hardware-software vendors, just to be sure that everything is working as required? Will the lower-level SE, formerly tasked with integrating chip hardware and firmware, now be out of a job?

If history is any indication, then we might look back to the early days of RTL synthesis for clues. With the move to include chip hardware and firmware, the industry might expect a shifting of job responsibilities. Also, look for a slew of new interface and process standards to deal with issues of integration and verification. New tool suites will probably emerge.

How will the new chip hardware and firmware platforms affect the integration System Engineer is not yet certain. But SE’s are very adaptable. A black box – even a blacker one – still has inputs and outputs that must be managed between variant teams throughout the product life cycle. At least that activity won’t change.

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Jun 07 2011

DAC Hits for Tuesday!

Published by under The Profession

Having a bit of trouble with the upload. Please check back shortly. Thx, all. – John

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Jun 06 2011

DAC Hits for Monday!

Published by under The Profession

There is so much to cover at DAC, but so little time to cover it.  Below are my highlights for Monday (6/6). — JB

 

 

JB’s DAC Bits for Monday (6/6/11):

My colleague, Ed Sperling, wrote a great piece on this panel. “Just having a cheaper or faster product isn’t good enough; tips for not losing the company to investors…or worse.” – Ed Sperling

 

I talked briefly with Jingwen Yuan, Synopsys Strategic Alliance Manager for the IPL Alliance. For updates and roadmap on their analog custom iPDKs, visit:

 

This company provides a cloud deployment platform that allows users to test out tools from leading EDA vendors. Xuropa uses the Amazon cloud platform. Harry Gries, well known EDA blogger and Xuropa’s Director of Customer Support, provided me with a great demo.

 

  • ARM Pushes Smarter Systems at DAC

I stopped to listen’s to Dr. John Heinlein’s opening presentation at the DAC “IP Talks” sessions.

 

Check out their booth! Its huge and well laid out. I met with Jim Ballingall, Ph.D. and VP of Marketing, as well as Jason Gorss, Technology PR Manager. Lots going on at Globalfoundries, including the new 28nm fab in Albany, NY and the synchronization of all of their world-wide fabs and partner facilities at the full planar, 28nm node. Their ecosystem is amazing.

Bob Durstenfeld, Director MarCom at GLOBALFOUNDRIES, talkes with DAC members.

This company is the “sleeper” at DAC. Their main message at DAC is one of PLM tools, which are essential for chip design and IP reuse as it evolves into the packaging, board and software market. But this company is also into augmented reality, megatronic systems and full-up systems engineering development tools. Rick Stanton, Director of Industry Market Development for ENOVIA (global semiconductor market) provided me with a first-class tour of the company – which I have mentioned from different angles in the past.

 

Karen Bartelson runs this popular technology focused social media site. I spoke with panelist to highlight Tuesday’s Verification panel: Verification: What’s in Your Wallet?

 

Here, I met with Shyam Chander, Applications Manager. My interest was in the company’s ASIC prototyping tools. More on that later.

 

Craig Cochran, VP of Marketing and Business Development, provided a sucincct overview of the sign-off verification in the age of complex multicore SoCs.

 

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May 20 2011

Embedded Software Developers Need Their Space

Published by under The Profession

By John Blyler

Improvements to several IDEs should make life a bit easier for time-constrained, globally separated, and processor-centric embedded-software developers.

At this year’s Embedded Systems Conference (ESC) event, software-development environments took center stage for both a prominent electronic-design-automation (EDA) tool and an integrated-circuit (IC) hardware company. In fact, the EDA-systems tool vendor, Mentor Graphics, won an award for its efforts to improve integrated development environments (IDEs) for embedded designers.

During ESC 2011, VDC Research Group, Inc. (VDC) gave the annual best-in-show “Embeddy” software award to Mentor Graphics’ Embedded Sourcery System Analyzer. The Embeddy is given to the company that’s announcing the most cutting-edge product or service for embedded-software developers and system engineers.

According to Mentor, the System Analyzer tool is designed to help embedded-software developers “visualize and analyze system data to identify and debug or decode problem areas easily and improve design performance.” System Analyzer is part of the Embedded Sourcery Codebench suite, an IDE based upon the open-source GNU tool chain. The IDE supports the embedded development of specific processors including NetLogic Microsystems’ XLP multicore processor, Freescale’s Kinetis, and Xilinx’s Zynq.

The traditional approach to debugging software code relies on breakpoints. They’re used to set aside troublesome code blocks and printf() statements in order to examine the data stored up to the breakpoints. System Analyzer improves this process by collecting trace and profile data from a variety of sources within the system. This information is plotted against a timeline as well as in relationship to other system activity. As a result, embedded developers should be able to debug code problems with greater ease and efficiency.

Although Microchip didn’t win an award at ESC for improving its software-development environment, the company was given the 2010 EDN Innovation Award for its human-machine-interface technology—specifically, the mTouch Metal-Over-Capacitive touch-sensing technology.

The company’s open-source MPLAB X IDE improvements are noteworthy because of the addition of several features including the following:

  • Team-collaboration tools for bug tracking and source-code control
  • Support for multiple, simultaneous compiler versions
  • Code completion and context menus via advanced editor

 

MPLAB X is based on the Oracle-sponsored, open-source NetBeans platform, which has a wide range of third-party plug-ins. The company’s IDE platform supports all of its 8-, 16-, and 32-bit microcontrollers and related digital signal controllers and memory devices.

Today’s software developers rely on IDEs to do their jobs. Thanks to EDA and IC companies, those workspaces just got an improved view.

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May 06 2011

Impressions from ESC 2011

Published by under The Profession

By John Blyler

Here are my rough impressions from the last four days of attendance at the Embedded Systems Conference.

The weather was warm and inviting as is shined through the large windows at the San Jose McEnery Conference Center. Inside, the show floor was full with exhibitions.

Attendance to the show floor felt a bit light, but it was consistently even through each day. The training and educations sessions were reportedly well attended.

The main draw on the show floor was the huge museum-like, skeletal display of a T-Rex.  The dinosaur exhibition, provided by Green Hills Software, was very cool but did seem a tad out of place.

By contrast, the many robots located throughout and sometimes roaming the show floor was also cool. They were definitely in place for an embedded conference.

Since I spend a large amount of my time in meetings, I missed the main keynote event delivered by Steve Wozniak, Co-Founder – Apple Computer, Inc. No matter, since Wozniak is also the keynote speaker at next month’s Design Automation Conference. I’ll hear his message at DAC.

Let me stay on the DAC-ish theme of EDA companies to cover their announcements at this week’s ESC event.

Most of the press – well, those of us left standing after the great changes in the media and publication world – were in attendance at Cadence’s in-booth press conference. The purpose of the gathering was to announce the next installment of the company’s EDA360 strategy, namely, “System Realization.”

The words described a need and approach for hardware and software SoC co-design and co-verification. The facts seemed to be the integration of Cadence’s very successful emulation platform (Palladium) with their higher level FPGA and virtual prototyping systems. As I listened to Senior VP and CMO John Bruggeman’s flawless delivery of the message, I couldn’t help but think back to the days of Cadence earlier attempts at co-design, namely, with ESL and SPW. It didn’t help that the ESC announcement was short on specific details, since the “System Realization” activities were still in early engagements with customers.

Not quite as spectacular(1) but still note-worthy was Mentor’s announcements of improvements in their long term goal of owning the system space. Here, system encompasses SoC design, manufacturing, packaging, board design and manufacturing through mechatronics. The company’s announcement focused on the software side of the system, namely, a new integrated development environment base on the open industry GNU tool chain.

Synopsys had a small booth at ESC, but provided no major announcements at the show.

But who goes to ESC to learn about the latest news from the EDA community? It’s the embedded space that counts. I’ll report details about all the embedded news later next week.

(1) What I meant to write was “Not quite the spectacle…” Even editors make misteaks. I mean, mistakes. — JB

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Apr 28 2011

Impossible Astronaut and Supercomputers in the Desert

Published by under The Profession

By John Blyler

The premier of a science fiction favorite and the start of a supercomputing competition all take place in a landscape rich in secret labs and alien sightings.

Have you ever noticed how coincidences and connections complement one another? It’s almost a “chicken and egg” relationship in terms of which comes first. Do seemingly unrelated, coincidental bits of information come first, sparking the imagination to make connections? Or do seemingly loosely coupled connections suggest a coincidental alignment at certain points in time?

Consider the following loosely coupled sequence of events. Last Saturday was the premier episode of the new science fiction season of Dr Who. The following Monday, the US National Nuclear Security Administration (NNSA) announced a new supercomputing website which highlights a competition taking place in New Mexico.

The Dr Who story line dealt with strange meetings with a lake-bound astronaut and aliens cowering in tunnels (see Figure 1). This episode – “The Impossible Astronaut” – was unique because it was the first time in the series 48 year history that an episode was filmed in the US, specifically in Utah. Together, the landscapes in Utah and New Mexico help form the Great Basin Desert, which some call the Navajoan Wilderness.

Figure 1: "Impossible Astronaut" from Spring 2011 episode of BBC's Dr Who.

The Great Basin Desert shares the same mystic intonations as its neighbors; the Chihuahua, Mojave and Sonoran Deserts.

The sheer barrenness of these wastelands provides fertile ground for the imagination, from lost cities of gold and ancient petroglyphic carvings to UFO sightings. Interesting, these vast areas are also the hubs for some of the most hidden and high-tech facilities known to man, from Area-51 to secret military-university R&D operations stretching throughout all of these deserts.

Let’s return to the seemingly coincidental supercoming event in New Mexico, located at the Los Alamos National Laboratory (LANL). In stark contrast to the 130F temperatures of the outside desert, the inside of the LANL is maintained at in the mid-60s. Such cave-like inside temperatures is needed to cool the monolith high performance supercomputers which owe their existence to the world of semiconductor, chip and EDA innovation (see Figure 2).

Figure 2: The unusual slant to BlueGene/L's cabinets is a necessary design element to keep cooled air flowing properly around each cabinet's processors.

During this one week in April, select middle- and high- school students have the, “opportunity to work on the most powerful computers in the world…” Teams of students work throughout the year to complete science projects worthy to be run on the high-performance supercomputers.

Not surprisingly, past successful projects have come from computational problems in Astronomy, Geology, Physics, Ecology, Mathematics, Economics, Sociology, and Computer Science. The one restriction is that the problem being addressed deals with a measurable “real world” rather than imaginary challenge.

Yet, it was probably the imaginary challenge from a sci-fi show like Dr Who that originally sparked the scientific and engineering interest of these young students.

There are strange things done in the desert sun by the men (and women) that moil for gold. (My apologies to Robert Service).

Is it by random chance that the intersecting paths of coincidence and connections and of science fiction and hard science meet in the vast, seemingly barren deserts of America?

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Apr 15 2011

R&D Focuses on Low Power and Stacked Die

Published by under The Profession

By John Blyler

Atrenta collaborated with the French laboratory CEA/LETI in a research and development effort to advance power reduction and 3D stacked die EDA tools.

This is an important story that I meant to cover earlier.

Figure 1: Geneviève Fioraso (Member of Parliament, Deputy Mayor, City of Grenoble & President, SEM MINATEC Enterprises) addressing the audience at the DATE 2011 reception.

One evening last month at DATE, a reception marked the opening of Atrenta’s new research and development facility located at the Micro and Nanotechnologies Innovation Center (MINATEC) campus (see Figure 1). Atrenta had been involved with MINATEC for over 10 years. That relationship was strengthened with the hiring of several Ph.Ds on the campus. These additional professionals will be part of the Atrenta R&D team in Grenoble.

The DATE reception was sponsored by both Atrenta and CEA/LETI, the electronics and information technology laboratory of the French Atomic Energy Commission. The R&D effort will focus on EDA software tools in the emerging markets of advanced power reduction and 3D stacked die design. 

The speakers at the reception formed a veritable “Who’s Who” of the European electronics industry (see Figure 2).

I couldn’t attend DATE this year, held in Grenoble, France. I’m told that the MINATEC center is located in the northern part of the city with spectacular views of Alpine mountain peaks.

Peggy Aycinena, a fellow editor who did attend DATE, provided a complete and colorful description of the Atrenta and CEA/LETI event on her “Superheros of SoC” site: “Atrenta Inaugural in Grenoble

Figure 2: Speakers at the event: From left to right - Philippe Magarshack (Group Vice-President Technology R&D, STMicroelectronics) , Ajoy Bose (Chairman, President and CEO of Atrenta), Loïc Liétar (Executive Vice-President & Chief Strategy Officer, STMicroelectronics & Chairman, Minalogic), Geneviève Fioraso (Member of Parliament, Deputy Mayor, City of Grenoble & President, SEM MINATEC Enterprises) and Jean-René Lèquepeys (VP, Architecture, IC Design & Embedded Software Division, CEA/LETI).

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Apr 08 2011

Altium Pins Hopes on China

Published by under The Profession

By John Blyler

Rumors are flying as to why Altium is relocating its global headquarters from Sydney, Australia to Shanghai, China.  The relocations have already resulted in the loss of a large portion of the company’s development team in Sydney. Key R&D developers will be retained with some moving to Shanghai. The company hopes to combine the key developers with local talent from Shanghai to grow its development, sales and support activates within the Chinese market.

Some have speculated that Altium may be pressured into the move by China in order to commercialize local Chinese IP into its product.

Other observers point to economics as the real reason for the move to Shanghai.  A quick look at the company’s annual reports shows a 3 year decline of roughly 10% per year.

The official word from the company – via a press release – states that the, “primary motivation for the move is … that China represents the best location and opportunity for the execution of Altium’s plan for … (transforming customer) businesses from product-based models to a service-based approach where web-based ecosystems enable direct relationships between device end-users and device manufacturers.”

In a recent interview with Electronic News, Altium’s Head of Corporate Communications, Alan Smith, stated that “China is investing a trillion dollars in building an indigenous design sector so that ‘made in China’ will become ‘designed in China’. The centre of gravity of the electronics industry is moving to the country and we have made a decision to be part of that shift.”

A differing viewpoint on the focus of China’s electronics industry is offered by one of Altium’s competitors. Mentor Graphic’s PAD product line competes with Altium Designer for the lower end products that involve a single user or small group of designers building FPGA-based printed circuit board assembly.

John Isaac, Director of Systems Market Development at Mentor, suggested that today’s China is focusing on high-tech, high performance, large system products. “Some Chinese companies are competing directly with more advanced US companies, such as the way Hauwei (pronounced WAWAY) competes directly with US-based Cisco,” notes Isaac. “There seems to be a real shift in China from designing low end, more simple products to designing really high-end products.”

If this is true, then China may not hold as much potential for Altium as company executive’s hope.

Adventures at DesignCon – Twitter Logs and a Gold Stocking Woman

Happier times for Altium at DesignCon 2009, when they made a big push into the American market.

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