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Changing EDA-IP Relationships

Who is really your customer? Competitor? Well-known EDA analyst Gary Smith forecasts the future.

Gary Smith began his annual pre-DAC overview by reminding his audience that in the world of system design (see Figure 1), the OEM was not necessarily a “manufacturer”. In today’s dynamic semiconductor world, the OEM can range from a company buying the platform design, manufacturing the system-on-chip (SoC) at a foundry, wrapping plastic around it and taking it to market (e.g., low end cell phones), to a vertically integrated company that outsources manufacturing (e.g., high-end Apple cell phones).

“With such a range of possible OEM scenarios, you need to understand who is your customer and who is your competitor,” explained Smith. “And the relationships almost change day by day. The key is to develop an ecosystem as stable as ARM’s in this changing world of relationship.”

Figure 1: System design consists of a large continuum, as Smith reminded his EDA audience with his slide from 1996.

System Design (note the capitals) refers to the larger design effort that includes many domains, i.e., hardware, software, electronic, mechanical and more. For the chip design community, system design requires new skills, new marketing and a new organization to participate in the system-level markets that include industrial, consumer, telecom, EDA/Computing, automotive and Mil-Aero. Gary mentioned that, of the big three EDA companies, only Mentor Graphics was actively participating in these markets – for now.

To successfully perform system design across these major markets, serious players must have an expert or multiple experts for each vertical or subset of that vertical. “The expert – most likely a geeky engineer and not a marketing person, drives product definition, but more importantly market access,” said Smith. Not surprisingly, these experts must come from the industry you are addressing.

What role does intellectual property play in this world of system design? “IP” is the key to productivity, therefore low cost design? Or is “IP” a meaningless buzzword used to impress Wall Street?

It’s both, explained Smith. Back in 2011, his analysis showed that “IP” lowered the cost of design by 44% in 2011! But IP is also a hot topic on Wall Street since it seems synonymous with patents. According to Smith, it all started with an EDA marketing person referred to low-level functions as IP. Then other EDA marketing people notice that Wall Street took notice when you mentioned IP and the rest is history.

That’s why one must understand the different kinds of IP. Smith categories ten types of “IP” in his famous wall chart. Each IP type is meant for a different market and has different value and sources:

  • Physical “IP” (2,400 to 74,999 gates)
  • Library “IP”  (“IP” bundles with tools)
  • DesignWare “IP”
  • Large “IP” (75,000 to 999,999 gates) – These designs include hardware, software, and verification IP -  SW, HW and verification IP. It all goes together. (see next bullet)
  • Verification “IP”- Very Large “IP” – Software “IP” (1 million +)

Designing with IP requires a platform. Smith provided a detailed description of the basic platform types, including functional (compute, NoC, etc); Foundation (Snapdragon, i.MX, etc.); and Application (Audio. GPS, etc.) (Editor’s Note: Reference 2012 Presentation: SoC Costs Cut by Multi-Platform Design )

Application Platforms have a short life,” noted Smith. “They are usually integrated into the Foundation Platforms within a few generations. Foundation Platforms are developed by today’s System Providers. Whereas Functional Platforms need a solid ecosystem to survive.”

Moving on to the design process, Smith proclaimed that we now ESL flow at which emulation is the heart. He cautioned that a problem still existed between the system architect and the ESL design group (see Figure 2). “Once the architect hands the design to the ESL group, then they lose control. There are standards for behavioral SystemC. This means that, while the hardware and software guys can use emulators pass things between one another, they can not pass those results back up to the architect.”

Figure 2: ESL flow is real but still has a few challenges.

Some argue that emulation is too expense. But Smith suggests that the real question should be; How does it impact the design cost?  Then short answer is that, in the long run, the impact is small as emulators are being used for many activities beside design (see Figure 3), e.g., bug finder, verification, etc. As companies find multiple uses for emulation, there long term costs will go down. As a consequency, the budget for future emulators will come from a decrease in respins. “If you can save $30 million form one respin, you have the budget to invest $5 million for emulation,” explained  Smith.

Figure 3: Percent HW and SW costs impacted by emulation.

Finally, Smith presented his obligatory 2014 forecast showing a healthy industry getting close to the $10 Billion mark after 2018 (see Figure 4).

 

Figure 4: The Q2 2014 forecast.

 

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