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Archive for June, 2014

Our Day at DAC – Day 2 (Tuesday)

Monday, June 2nd, 2014

Here are the brief observations on noteworthy presentations, cool demonstrations and hall-way chats from the Chip Design editorial staff covering DAC 2014.

Report from Gabe Moretti:

EDA is Alive and Ready for Another Year of Growth

The second day of DAC was a very busy one for me. I met with Dassault Systeme that showed me an impressive approach to EDA based on project management system that provides different views of the state of the project depending on the viewer position in the project. For example, project manager, individual engineer, verification engineer, and so on. I met with Verific and Invionics two different companies that have found a symbiotic way to expand the market they serve without competing with each other.
Synopsys described their approach to the automotive market. The presentation described almost perfectly my 2014 Lincoln MKZ hybrid. It is impressive to see technology becoming reality as I write.
Carbon is growing, revenues were up 46% last year and diversifying. They were not quite ready for a big announcement at DAC but I was told it would be made before the end of this month.

Much work is going on in formal verification embolden by Cadence acquisition of Jasper Design.
More meetings are scheduled for tomorrow and I promise a final impression of what DAC meant for me.

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Report from Hamilton Carter:

DAC Meanderings, 51st DAC (6/3)

 

The day started early with the Accelera breakfast.  The food was excellent.  There were “Fluffy scrambled eggs”, bacon, sausage and a variety of pastries. For the first half hour or so folks straggled in, slowly orienting themselves after the first night of DAC parties. The proceedings kicked off with the handling of a few business issues.  Shishpal Rawat, the current Accelera chairman outlined the achievement of the prior year and the goals and schedule of the ensuing one. The last order of business was the presentation of the Accelera Leadership Award for 2014 to Yatin Trivedi, (pictured).

A few moments later, Doulos’ John Ainsley, ever-spry, bounded onto the stage to introduce the members of his UVM roundtable.

John played devil’s advocate to keep the panel lively. He first asked what the members’ general feelings on System Verilog were. When all the panelists agreed that they were generally happy, John then prodded each of them to find out how happy they were, why, and what challenges they were still having. The general consensus seemed to be as follows:

  • Asking designers to adopt object oriented class-based solution was a hard sale.
  • Finally having a uniform standard offered by all the vendors was very, very nice.
  • There were hiccups and burps along the way as internal libraries needed to be converted to the new standard and IP vendors tended not to have adopted the standard yet.

From the Accelera breakfast a brief walk brought me to the first time exhibitors’ interviews.

Silicon Cloud
Marc Edwards, presenting for Silicon Cloud, described his vision of moving the engineering flow into the cloud.  Allowing startups and others to avert the expense of large hardware box purchases.  Silicon Cloud offers a solution that moves all design tools, licenses, and IP into a server space they maintain and monitor.  The places 1000s of virtual machines at the disposal of design engineers who access the cloud via Chrome books that have been walled from the rest of the internet.  All transactions that touch the design, IP, or tools are recorded.  In addition to providing valuable information on the process flow and the usage of tools and IP, Silicon Cloud also watches for nefarious and/or non-conformal behavior with regards to the management of IP.

Imperas
Larry Lapides presented Imperas’ services and product portfolio.  The company is focusing on software verification in the embedded realm.  Their portfolio of over 140 open access processor and peripheral models allows their customers to bring up their software ahead of design completion.  The models run at millions of cycles per seconds allowing very comprehensive software scenarios.  Automotive and medical embedded applications, where software failure is not an option, are adopting Imperas’ testing and system reliability tools and methodology.

Plunify
Harnhua Ng presented Plunify’s FPGA-build optimizing solution.  Their tool watches FPGA builds. which can take days to not converge, and provides early warning that non-convergence is imminent.  The tool also points out the likely causes of the non-convergence within the design so that a successful build can be achieved next time.  In addition to its dynamic build-watching features, the tool also has a static facility that scans the design-to-be-built and warns of known issues before the build begins.

OPTIC2connect
Jason Png, OPTIC2connect’s founder and CEO, gave a brief presentation of his company’s optical interconnect prototyping services.  He said they don’t intend to replace design engineers, just make their jobs much simpler.   OPTIC2connect has helped their customers move their prototyping cycles for optically enabled bus infrastructures from six months to three weeks.

Synopsys is back in the Formal Verification Market
From a round of interviews with the new guard of EDA, I proceeded to an interview with one of the older names in EDA, Synopsys.  Synopsys is announcing their new entry into the formal/static verification market at this year’s DAC.  The all new tool introduces capabilities for formal verification, clock domain crossing, and low power static checking with other features on the way soon.  The tool can load in chip level, fully-flattened RTL designs to facilitate proper low power and interconnect checking.  It also sports simplified and compressed error output.  Gone are the days of day long design checks followed by searching through gigabytes of data for the error that matters.  The tool bundles errors up to their root cause which is reported along with the count of other errors that are attributed to the root.  For those that sill want to get into the gory details for themselves, an API is provided for teasing every last bit of available data out of a formal/static verification run.

Jasper’s food truck party
Jasper brought three busloads of engineers and semiconductor industry aficionados to Treasure Island earlier today to partake of the delicious wares of five different food trucks.

Entertainment was provided by Rat-Pack styled musicians, a magician, a juggler, and a lawyer turned professional bubble maker.

A great time was had by all, and CEO Jasper CEO Kathryn Kranen, thanked the Jasper team for their excellent work.

Our Day at DAC – Day 1 (Monday)

Monday, June 2nd, 2014

Here are the brief observations on noteworthy presentations, cool demonstrations and hall-way chats from the editorial staff covering “Day 1″ at DAC 2014 – John Blyler, Gabe Moretti and Hamilton Carter.

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DAC Report from Hamilton Carter:

Puuurrrple, so much purple!  The stage at the packed Synopsys, Samsung, ARM briefing this morning was backed by ceiling to floor Synopsys-purple curtains.  The Samsung vision video played on the two large screens on either side of the stage.  To steal a phrase from “Love Actually”, Samsung’s vision is that “touch-screens are… everywhere” .  Among the envisioned apps were a touch screen floor for your kids’ room, complete with planetarium app; a touchscreen window for your Town-Car so you can adjust the thermostat in the car as your driver taxis you to your destintion; and finally a touchscreen gadget for the kitchen that when laid flat weighs the food and registers the number of calories in the amount you’ve sliced off on its cutting board tough screen, displays the recipe you’re using when upright, and finally, get ready for it… checks the ‘safety’ of your food displaying an all clear icon complete with a rad safe emblem.  Apparently the future isn’t completely utopian!

Phil Dworsky, director of strategic alliances, for Synopsys introduced the three featured speakers, Kelvin Low, of Samsung, Glenn Dukes of Synopsys, and Rob Aitken from ARM, and things got under way.  The key impetus of the presentation was that the Samsung/Synopsys/ARM collaboration on 14 nm 3D finfet technology is ready to go.  The technology has been rolled out on 30 test chips and 5 customer chips that are going into production.

Most of the emphasis was on the 14 nm process nodes, but the speakers were also quick to point out that the 28 nm node wasn’t going away anytime soon  With its single patterning, and reduced power consumption, it’s seen as a perfect fit for mobile devices that don’t need the cutting edge of performance yet.

Interesting bits:

  • It was nice to visit with Sanjay Gupta, previously of IBM Austin, who is now at Qualcomm, San Diego.
  • While smart phones have been outshipping PCs for a while, tablets are now predicted to outship PCs starting in 2015.
  • Bryan Bailey of verification fame was one of the raffle winners.  He’s now a part of the IoT!
  • IoT predictions are still in the Carl Sagan range, there will be ‘billions and billions’.
  • Samsung GLOBALFOUNDRIES has a fab, Fab8, in Saratoga, NY.
  • Last year’s buzzword was ‘metric driven’, this year’s is ‘ecosystem’ so far.  The vision being plugged is collaborations of companies and/or tools that work as a ‘seamless, [goes without saying], ecosystem’.

Catching up with Amiq

I got to catch up with Christian from Amiq this morning.  Since they’re planted squarely in the IDE business, Amiq gets the fun job of working directly with silicon design and verification engineers.  There products on display this year include their Eclipse based work environment, with support for e, and SystemVerilog built in, their verification-code-centric linting tool Verissimo, and their documentation generation system Specador.

IC Manage

I’m always drawn in by a good ‘wrap a measurable, or at least documentable flow around your design process story’, so I dropped by the IC Manage booth this morning.

Their product encapsulates many of the vagaries of the IC development flow into a configuration management tool.  The backbone of the tool can be customized to the customer’s specific flow via scripts, and it provides a real-time updated HTML based view of what engineers are up to as project development unfolds.

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DAC Report from Gabe Moretti:

Power Management and IP

Moscone South is all about IP and low power.  This is the 51st DAC and my 34th.  Time flies.  The most intimidating thing is that the Apple Developers Forum is going on at the same time, and they have TV trucks and live interview on the street.  We of course do not.  It was nice to hear Antun Domic as one of the two keynote speakers this morning  His discussion on how the latest EDA tools are used to produce designs fabricated with processes as old as 180 nanometers was refreshing.  In general people equate the latest EDA tools with the latest semiconductor process.  Yet one needs to manage power even at 180 nanometers.

Chip Estimate runs a series of talks from IP developers in its booth.  I listened to Peter Mc Guiness of Imagination Technologies talk about advances in image processing.  it was interesting to hear him talk about lane departure warning as an automotive feature employing such technology.  Now I know how it works in one of my cars.  On the other hand to hear how the retail industry is planning to use facial recognition to choose for me what I should be interested in purchasing is not so reassuring.  But, on the other hand, its use in robotics applications is fashinating.

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DAC Report from John Blyler:

I. IP Panel: The founders for several successful private IP companies shared their experiences with an audience of near 50 attendees. The panelist included CAST, IPExtreme, Methods2Business, and Recore Systems. The main takeaways were that starting an IP company takes passion and a plan.  But neither will work if you don’t have some product to offer and a few key relationships in the industry. (Warren said you need 3 key customers to start.) I’ll write more about this panel later. Here’s a link to a pre-DAC position statements from the panelist.

II. NI and Cadence – The Best of Both Worlds

George Zafiropoulos, VP, Solutions Marketing at National Instruments (NI)-AWR, has brought his many years of chip design and verification experience from the EDA industry to NI. He spoke at the DAC Cadence Theater about post- and pre-silicon verification being the best of both worlds. Those worlds consist of NI, which has traditionally been used for post-silicon verification testing, and Cadence, which is known for pre-silicon design and verification. George has proposed the use of NI test hardware and software to do pre-silicon verification in combination with Cadence’s emulation tools, i.e, Palladium. This proposed combination of tools elicited many questions from the audience who were more familiar with the pre-silicon tools than the post-silicon testers. Verification languages were an issue for those who had never used the Mindstorm or other NI graphic tools suits. I’m sure we’ll learn more on this potential partnership between NI and Cadence tool suites.

III. Visionary Talk by Wally Rhines, CEO, Mentor Graphics (prior to the afternoon keynote):

The title described it all; “EDA Grows by Solving New Problems.” Wally’s vision focused on how EDA industry will grow even with the constraints on its relatively flat revenue. As he noted back in the 2004 DAC keynote, the largest growth with EDA tools is associated with the adoption of new methodologies, e.g., ESL, DFM, and FPGAs. Further, tools that support new methodologies have been the main drives of growth in the PCB and semiconductor worlds.

“EDA need to tap into new budgets … for emulation, embedded software … and in new markets,” explained Rhines. “The automotive industry is at the same stage of development as was the chip design industry in the 1970s. Their development process will have to be automated and with new tools.”

Another growth market will be hardware cyber security.

Changing EDA-IP Relationships

Sunday, June 1st, 2014

Who is really your customer? Competitor? Well-known EDA analyst Gary Smith forecasts the future.

Gary Smith began his annual pre-DAC overview by reminding his audience that in the world of system design (see Figure 1), the OEM was not necessarily a “manufacturer”. In today’s dynamic semiconductor world, the OEM can range from a company buying the platform design, manufacturing the system-on-chip (SoC) at a foundry, wrapping plastic around it and taking it to market (e.g., low end cell phones), to a vertically integrated company that outsources manufacturing (e.g., high-end Apple cell phones).

“With such a range of possible OEM scenarios, you need to understand who is your customer and who is your competitor,” explained Smith. “And the relationships almost change day by day. The key is to develop an ecosystem as stable as ARM’s in this changing world of relationship.”

Figure 1: System design consists of a large continuum, as Smith reminded his EDA audience with his slide from 1996.

System Design (note the capitals) refers to the larger design effort that includes many domains, i.e., hardware, software, electronic, mechanical and more. For the chip design community, system design requires new skills, new marketing and a new organization to participate in the system-level markets that include industrial, consumer, telecom, EDA/Computing, automotive and Mil-Aero. Gary mentioned that, of the big three EDA companies, only Mentor Graphics was actively participating in these markets – for now.

To successfully perform system design across these major markets, serious players must have an expert or multiple experts for each vertical or subset of that vertical. “The expert – most likely a geeky engineer and not a marketing person, drives product definition, but more importantly market access,” said Smith. Not surprisingly, these experts must come from the industry you are addressing.

What role does intellectual property play in this world of system design? “IP” is the key to productivity, therefore low cost design? Or is “IP” a meaningless buzzword used to impress Wall Street?

It’s both, explained Smith. Back in 2011, his analysis showed that “IP” lowered the cost of design by 44% in 2011! But IP is also a hot topic on Wall Street since it seems synonymous with patents. According to Smith, it all started with an EDA marketing person referred to low-level functions as IP. Then other EDA marketing people notice that Wall Street took notice when you mentioned IP and the rest is history.

That’s why one must understand the different kinds of IP. Smith categories ten types of “IP” in his famous wall chart. Each IP type is meant for a different market and has different value and sources:

  • Physical “IP” (2,400 to 74,999 gates)
  • Library “IP”  (“IP” bundles with tools)
  • DesignWare “IP”
  • Large “IP” (75,000 to 999,999 gates) – These designs include hardware, software, and verification IP -  SW, HW and verification IP. It all goes together. (see next bullet)
  • Verification “IP”- Very Large “IP” – Software “IP” (1 million +)

Designing with IP requires a platform. Smith provided a detailed description of the basic platform types, including functional (compute, NoC, etc); Foundation (Snapdragon, i.MX, etc.); and Application (Audio. GPS, etc.) (Editor’s Note: Reference 2012 Presentation: SoC Costs Cut by Multi-Platform Design )

Application Platforms have a short life,” noted Smith. “They are usually integrated into the Foundation Platforms within a few generations. Foundation Platforms are developed by today’s System Providers. Whereas Functional Platforms need a solid ecosystem to survive.”

Moving on to the design process, Smith proclaimed that we now ESL flow at which emulation is the heart. He cautioned that a problem still existed between the system architect and the ESL design group (see Figure 2). “Once the architect hands the design to the ESL group, then they lose control. There are standards for behavioral SystemC. This means that, while the hardware and software guys can use emulators pass things between one another, they can not pass those results back up to the architect.”

Figure 2: ESL flow is real but still has a few challenges.

Some argue that emulation is too expense. But Smith suggests that the real question should be; How does it impact the design cost?  Then short answer is that, in the long run, the impact is small as emulators are being used for many activities beside design (see Figure 3), e.g., bug finder, verification, etc. As companies find multiple uses for emulation, there long term costs will go down. As a consequency, the budget for future emulators will come from a decrease in respins. “If you can save $30 million form one respin, you have the budget to invest $5 million for emulation,” explained  Smith.

Figure 3: Percent HW and SW costs impacted by emulation.

Finally, Smith presented his obligatory 2014 forecast showing a healthy industry getting close to the $10 Billion mark after 2018 (see Figure 4).

 

Figure 4: The Q2 2014 forecast.