Part of the  

Chip Design Magazine

  Network

About  |  Contact

DAC – Video Latency; Platform as a Service; 262626; and ARM-12

My Tuesday at DAC involved CAST IP, Mentor Graphics, Dassault Systemes, Chipestimate.com, and Globalfoundries-ARM. 

Here are but a few of the companies, hallway discussions, and presentations that I enjoyed during Tuesday at DAC:

> Performance is a function of latency and power, as Gary Smith noted in his pre-DAC EDA and IP trends presentation. One example of the need to balance latency and power is in the application of real-time video streaming (e.g., H.264 video encoders). Latency is the delay that occurs between the processing and transmission of live video. A simple way to initially gauge latency is by waving your hand quickly in front of the camera and watching for blurring of the image on the display. I saw none during my demo.

 

Other news from CAST highlighted a joint announcement with IP company Beyond Semiconductor concerning an ultra-low-power, 32-bit BA21 embedded processor.

 

 

 

> Hallway chat with Mentor’s M&A expert, Serge Leef:

Software as a Service (SaaS) for EDA cloud-based applications seems passé. Platform as a Service (PaaS) is the new “black.” The key driver in this change seems to be the push by next-generation chip designers for a more robust user experience (UE; see “Experience Required,” http://chipdesignmag.com/sld/blog/2013/05/30/experience-required/). Serge sees the trend to user-experience designs as essential to the evolution of EDA tools. He even believes them to be a source of revenue in terms of a micro-business model.

 

> Dassault Systemes offered several interesting technology demos. While their Netvibes product provides for intelligent dashboarding, Tuscany’s PinPoint enables tracking progress from synthesis to GDSII.

http://www.tuscanyda.com/

> IP protection and management includes the synchronization of databases and documentation. In this way, a close partnership with Magillem is proving very useful. (More about this in the near future.)

> Simulation Lifecycle Management (SLM) for semiconductor verification and validation (V&V) flows may evolve quickly into a framework. The effort in the automotive industry via ISO262626 may establish a working model for the EDA industry.

 

> Globalfoundries presentation at Chipestimate.com, “IP Talks” – Subi Kerngeri, VP of the Advanced Technology Division, talked briefly about many things, mostly centering on the need to offer a combination of device technology design and SoC manufacturing expertise.  But this need is fraught with challenges. (Reference: “Modular FinFET Increases Planar-to-Non-Planar IP Reuse”)

http://www.chipestimate.com/blogs/IPInsider/?p=1264   He noted that Globalfoundries was the first fab to optimize for the newly announced ARM Cortex-A12 CPU – POP IP combined with Globalfoundries’ 28-SLP process. Also, Kerngeri emphasized the success of Fully-Depleted SOI technology at 28 nm, saying that it was pretty much like bulk CMOS for designers. STMicro is their partner in FD-SOI. This technology has enabled 0.63 v at 1-GHz performance in a dual A-9 implementation.

 

 

 

 

Leave a Reply