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Gary Smith’s Sunday Night, Pre-DAC Forecast

Building on last year’s multi-platform design focus, EDA luminary Gary Smith busts the myth of the $170M SoC design cost.

The Design Automation Conference’s (DAC’s) unofficial kick-off starts with Gary Smith’s Sunday night forecast about the latest trends in the semiconductor, EDA, and IP industries. To understand this year’s analysis, it’s best to review the 2012 predictions (see “SoC Costs Cut by Multi-Platform Design”). 

Last year, Smith adjusted his earlier claim that SoC design costs were near $75M. He found that a better number for IDMs and fabless companies was around $50M. For start-ups, it was closer to $25M. In fact, several IDMs were creating SoCs at $40M and less. How? Through the reuse of software, the reuse of verifiable design IP, and by reducing SoC core blocks below the typical five blocks. Taken together, these combinations of activities constitute the multi-platform-based design approach.

In essence, this approach is based on the integration of existing platforms enhanced with a new application level to add a competitive advantage. The greatest cost savings was realized from the reduction of new core designs.

So what has changed in a year’s time? Well, not a whole lot. But hindsight provides amazing clarity. This year, Smith focused on the evolving meaning of performance, cost constraints, and the importance of integrated silicon and virtual platforms. (One clarification: The term “platform” is sometimes used synonymously with IP subsystems.)

Smith opened his presentation by listing the evolving definitions of performance in SoC design. The old view was that “Frequency = Performance.”  Today’s view is that “Performance = Latency + Power.” However, customers take a slightly different view – namely, that “Performance = Available Applications.” This translates almost directly to gate count.

Perhaps it’s a subtle point, but performance is a function of power. And power budgets for mobile smartphones are 5 W max! This is nothing new, but the design community has been developing lots of tools to improve power’s impact on the design (see Figure 1). Pay special attention to the prototype design tools (e.g., software and silicon virtual prototypes – you’ll see more on those shortly). The other term that caught my eye was the “System-Level Design Automation” (SDA) tool/methodology, predicted to be ready by 2025.

Figure 1: Courtesy of Garysmith.eda

Smith displayed several great slides that plotted gate count against frequency within a 5-W design constraint for the $50M (3.22B gates) and $25M (3B gates) SoC design-cost targets (see Figure 2).

Figure 2: Courtesy of Garysmith.eda

The conclusion was that cost remains the main constraint. According to Smith, this means –among other things – that the more apps you have on your phone, the better chance you’ll have a competitive edge. But they must be the right apps for the still abundant 3 billion gates. Using those gates wisely will be more important than the total quantity.

Smith explained why the predictions that designs will cost $170M “are just wrong.” Aside from a custom design by Intel or other IDMs, no SoC will cost that much. This is good news for start-ups, which will now be able to compete – as long as they pick their product carefully with a smart design.

The discussion then turned to progress in the ESL design flows. Smith gave a nod to Atrenta in acknowledging its silicon virtual prototype (SVP). He predicted that there would be two more SVPs by DAC 2014. Transactional accelerators and emulation boxes also helped ESL flows.

The numbers supporting these ESL claims look good for 2013 (see Figure 3). Total software virtual prototypes (SWVPs) used in both design and verification are 326,747 while silicon virtual prototypes (SVPs) – again, in both design and verification – are at 129,346.

Figure 3: Courtesy of Garysmith.eda

Smith issued a warning to EDA tool vendors, especially in the FPGA community: You can give away your tools, but don’t give away your models. What do these models look like?

The main model platforms focused on silicon and software virtual (IP) systems. Smith stated that the introduction of virtual platforms and the adoption of the multi-platform-based design (recall last year’s forecast) are combining to drive an explosion in SoC design. The lowering of SoC design cost is allowing more design starts as well as a jump in gate count for leading-edge designs.

Further, the adoption of virtual prototypes is allowing design creation to be detached from the design-realization portion of the design cycle, allowing a proliferation of design groups throughout the world, explained Smith (see Figure 4). He concluded that the shackles are off of the design community as we enter the brave new world of SoC design!

Figure 4: Courtesy of Garysmith.eda

 

Reference notes:

1. SOC Realization

Building a Bridge to New Markets and Renewed Growth Takes a Team Approach

By Ajoy Bose, Chairman, President, and CEO, Atrenta Inc.

The term SoC Realization was originally defined by Cadence Design Systems in its 2010 White Paper, “EDA360: The Way Forward for Electronic Design.”  It has since become an important trend for semiconductors and EDA… SoC Realization represents the highest point of leverage between a design that is too abstract to make intelligent choices and a design that is too far into implementation to fix problems easily… SoC Realization is more of an ecosystem than a set of tools. It is the umbrella over all of the things that designers can do to make it easier to design SoCs.

 

2. EDA Spins into the Realm of Software

By Ed Sperling & John Blyler

A year ago, it was all about developing hardware at the leading edge of Moore’s Law. Now, the focus is on developing software.

One Response to “Gary Smith’s Sunday Night, Pre-DAC Forecast”

  1. Gary Dare (@GaryDare) Says:

    JB, with respect to the question on ESL adoption and Gary Smith’s answer on the proliferation of virtual prototyping, Gary also mentioned that he saw RTL as remaining dominant for another 10-15 years. Did you recall that?

    That lead me to wonder if we’re seeing the manifestation of lack of innovation in electronics design, as pointed out by Accenture in another publication just before DAC:

    http://www.eetimes.com/electronics-blogs/food-for-thought/4415331/Innovation-gap-calls-for-new-processes–survey-shows

    (Yes, that’s me in the blog discussion.)

    It makes me wonder if EDA is too dependent on RTL revenues to let its customers go to higher levels of abstraction (n.b., RTL design won’t disappear but will be a major downstream component; we still have people doing layout, clock tree design, custom, etc.) in a bigger way? And/or encouraging RTL design camps within their customers to continue doing so …

    G

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