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Archive for May, 2013

Dr. Stan Krolikoski’s Words and Award

Friday, May 31st, 2013

A look back at Stan’s blogs and a look forward to his award.

At this year’s Design Automation Conference, Dr. Stan Krolikoski was honored with the 2013 Accellera Systems Initiative Leadership Award for his vision and contributions to EDA and IP standards.

Dr. Krolikoski has a long list of technical and business achievements. He has held vice president positions at EDA giant Cadence and start-ups like ChipVision, where he was the CEO. He has been a welcome presence in various standard communities throughout his career. (Here’s just one example: “Interview with Stan Krolikoski at DVCon 2011 –  SystemC Day” – Discussion on Verification IP (VIP), SystemC, IEEE 1666 Standard).

Chipestimate.TV's Sean O'Kane interviews Stan Krolikoski at DVCon 2011 - SystemC Day.

On a more personal basis, I was proud to have Stan as a blogger on Chip Design magazine, where he covered standards and the people behind them for many years. What follows is a brief listing of those blogs:

Looking at DVCon 2012

DVCon 2012 ended yesterday, March 1.  Rather than recap the entire conference, I’d like to focus on the “high energy” surrounding the event, starting with the vendor exhibitions.

John Aynsley and the IEEE SystemC LRM

The Accellera Systems Initiative has announced that John Aynsley, the CTO of Doulos, will be awarded that organization’s Technical Achievement Award for his “contributions to SystemC”…How, then, was any technical process managed, when there was only one technical meeting?  Simply put, almost all progress was made as the result of discussions held via the group’s email reflector.

Get Ready ‘Cause Here It Comes: Accellera Systems Initiative Day @ DVCon

Lots of ink has been spilt (in a good cause) in reporting on the new Accellera Systems Initiative organization.  However, many of you may still wonder how you can get an in-depth view of what is happening in this new organization, which resulted from the merger of Accellera and the Open SystemC Initiative (OSCI).

Why the OSCI-Accellera Merger?

By now, most of you will have heard and read about the merger of Accellera and OSCI into the Accellera Systems Initiative. A question that may linger after reading various press accounts is, “Why a merger?”

Larry, Larry, Larry!

On Sunday, December 4, Larry Saunders received the Ron Waxman award from the IEEE Design Automation Standards Committee (DASC) for extraordinary service to the DASC.

Ada-C redux

In a recent post on the DeepChip website, Gary Smith states that Fortran and Ada are superior to C and its variants, but notes that “…unless there is a major revolt among Embedded Programmers, we are stuck with C and SystemC.”

The Deaths of Two Tech Giants

All of you undoubtedly noted the passing of Steve Jobs on October 5.  What you might have missed is the passing of another high-technology giant, viz., Dennis Ritchie a few days later.  Ritchie was the father of the C language and one of the main forces behind the development of UNIX®.

OSCI-Accellera: Cue Mr. Peabody’s WABAC Machine

As most of you will have seen by now, Accellera and OSCI have announced their intention to form a new EDA standards organization, which will cover the design flow roughly from gate-level up through the system-level.  This may seem to be a natural move to most people, and one that could easily have happened years ago.

DVCON & DATE 2011: A Retrospective

The last two months since my last post have been extremely busy for me—several weeks out of the office and new responsibilities at work.  In this post, I’d like to briefly look at the two conferences, DVCon and DATE, that I attended during this period.

Reflections on UVM 1.0

As you may have already seen in the blogosphere and in the tweetdom, the Accellera Board today approved the release of UVM 1.0.  This release is a major accomplishment from a technical standpoint, but it also represents a triumph of the collective will of the electronics/EDA industry.

Thoughts On SystemC Users’ Groups

I ate breakfast a few weeks ago with Gabe Moretti of GabeOnEDA fame—always a pleasant event.  During our discussion, Gabe opined that the Open SystemC Initiative (OSCI) was superior to other front-end standards organization because of its SystemC Users’ Groups like NASCUG, ESCUG, the Taiwan SystemC users’ Group, SystemC Japan, and so forth.

SystemVerilog in Japan

During the EDSF show held in Yokohama in late January, there were several meetings between members of JEITA and members of the IEEE Design Automation Standards Committee (DASC): Hamaguchi-san (SystemVerilog WG Chair, Panasonic), Kojima-san (JEITA Fellow, NECST), Imai-san (SystemC WG Chair, Toshiba).

Standards– This Time It’s Personal

On Sunday evening, December 6, I came face-to-face with part of my past.  The window to my past was opened by meeting (after a very long hiatus) with two of the “founding fathers” of the EDA standards world, Hal Carter and Ron Waxman, at the IEEE Standards Association Awards Banquet in New Brunswick, NJ.

Another Standard Forthcoming in 2011

In my most recent post, I highlighted two standards that are scheduled to be released in 2011, viz., UVM from Accellera and SystemC from the IEEE P1666 Working Group (WG).  In this post, I’ll focus on another standard that will be put to a vote (and presumably approved) in 2011.  This standard is the “e” language standard developed by the IEEE P1647 WG, chaired by Darren Galpin.

New & Updated EDA Standards Coming In 2011

I have not posted in a few weeks, but not because things have been quiet in the standards world.  Rather, too much has been happening, and it has been hard to find time to sit down and summarize for those who might not be intently following such things.

Planning For IEEE Standards Association Corporate Membership

With the 2011 corporate budget planning cycle about to begin in many companies, I thought it appropriate to review the IEEE Standards Association (SA) corporate membership plan, including both its costs and benefits. 

Standards & Reference Implementations

In a previous blog entry, I spoke about the relationship between standards and open-source software, concluding that “open-source standard” was an oxymoron.

DVCon 2011 Is Open For Business

DVCon 2011, sponsored by Accellera, is now open for paper abstracts and proposals for panels/sponsored tutorials.

The Importance of Front-End Standards

It was recently announced that Shishpal Rawat has been elected Chair of Accellera, a key “Front End” (i.e., RTL and above) EDA standards organization.  This by itself is a fine development, since I have absolutely no doubt that Accellera will prosper under Shishpal’s leadership.

The “Open Source Standard” Oxymoron

Recently, I explained why the forthcoming Accellera UVM Standard will not be released under an open-source license. UVM will have an open-source reference implementation associated with it, but the actual UVM Standard will not be open source.

Gary Smith’s Sunday Night, Pre-DAC Forecast

Friday, May 31st, 2013

Building on last year’s multi-platform design focus, EDA luminary Gary Smith busts the myth of the $170M SoC design cost.

The Design Automation Conference’s (DAC’s) unofficial kick-off starts with Gary Smith’s Sunday night forecast about the latest trends in the semiconductor, EDA, and IP industries. To understand this year’s analysis, it’s best to review the 2012 predictions (see “SoC Costs Cut by Multi-Platform Design”). 

Last year, Smith adjusted his earlier claim that SoC design costs were near $75M. He found that a better number for IDMs and fabless companies was around $50M. For start-ups, it was closer to $25M. In fact, several IDMs were creating SoCs at $40M and less. How? Through the reuse of software, the reuse of verifiable design IP, and by reducing SoC core blocks below the typical five blocks. Taken together, these combinations of activities constitute the multi-platform-based design approach.

In essence, this approach is based on the integration of existing platforms enhanced with a new application level to add a competitive advantage. The greatest cost savings was realized from the reduction of new core designs.

So what has changed in a year’s time? Well, not a whole lot. But hindsight provides amazing clarity. This year, Smith focused on the evolving meaning of performance, cost constraints, and the importance of integrated silicon and virtual platforms. (One clarification: The term “platform” is sometimes used synonymously with IP subsystems.)

Smith opened his presentation by listing the evolving definitions of performance in SoC design. The old view was that “Frequency = Performance.”  Today’s view is that “Performance = Latency + Power.” However, customers take a slightly different view – namely, that “Performance = Available Applications.” This translates almost directly to gate count.

Perhaps it’s a subtle point, but performance is a function of power. And power budgets for mobile smartphones are 5 W max! This is nothing new, but the design community has been developing lots of tools to improve power’s impact on the design (see Figure 1). Pay special attention to the prototype design tools (e.g., software and silicon virtual prototypes – you’ll see more on those shortly). The other term that caught my eye was the “System-Level Design Automation” (SDA) tool/methodology, predicted to be ready by 2025.

Figure 1: Courtesy of Garysmith.eda

Smith displayed several great slides that plotted gate count against frequency within a 5-W design constraint for the $50M (3.22B gates) and $25M (3B gates) SoC design-cost targets (see Figure 2).

Figure 2: Courtesy of Garysmith.eda

The conclusion was that cost remains the main constraint. According to Smith, this means –among other things – that the more apps you have on your phone, the better chance you’ll have a competitive edge. But they must be the right apps for the still abundant 3 billion gates. Using those gates wisely will be more important than the total quantity.

Smith explained why the predictions that designs will cost $170M “are just wrong.” Aside from a custom design by Intel or other IDMs, no SoC will cost that much. This is good news for start-ups, which will now be able to compete – as long as they pick their product carefully with a smart design.

The discussion then turned to progress in the ESL design flows. Smith gave a nod to Atrenta in acknowledging its silicon virtual prototype (SVP). He predicted that there would be two more SVPs by DAC 2014. Transactional accelerators and emulation boxes also helped ESL flows.

The numbers supporting these ESL claims look good for 2013 (see Figure 3). Total software virtual prototypes (SWVPs) used in both design and verification are 326,747 while silicon virtual prototypes (SVPs) – again, in both design and verification – are at 129,346.

Figure 3: Courtesy of Garysmith.eda

Smith issued a warning to EDA tool vendors, especially in the FPGA community: You can give away your tools, but don’t give away your models. What do these models look like?

The main model platforms focused on silicon and software virtual (IP) systems. Smith stated that the introduction of virtual platforms and the adoption of the multi-platform-based design (recall last year’s forecast) are combining to drive an explosion in SoC design. The lowering of SoC design cost is allowing more design starts as well as a jump in gate count for leading-edge designs.

Further, the adoption of virtual prototypes is allowing design creation to be detached from the design-realization portion of the design cycle, allowing a proliferation of design groups throughout the world, explained Smith (see Figure 4). He concluded that the shackles are off of the design community as we enter the brave new world of SoC design!

Figure 4: Courtesy of Garysmith.eda

 

Reference notes:

1. SOC Realization

Building a Bridge to New Markets and Renewed Growth Takes a Team Approach

By Ajoy Bose, Chairman, President, and CEO, Atrenta Inc.

The term SoC Realization was originally defined by Cadence Design Systems in its 2010 White Paper, “EDA360: The Way Forward for Electronic Design.”  It has since become an important trend for semiconductors and EDA… SoC Realization represents the highest point of leverage between a design that is too abstract to make intelligent choices and a design that is too far into implementation to fix problems easily… SoC Realization is more of an ecosystem than a set of tools. It is the umbrella over all of the things that designers can do to make it easier to design SoCs.

 

2. EDA Spins into the Realm of Software

By Ed Sperling & John Blyler

A year ago, it was all about developing hardware at the leading edge of Moore’s Law. Now, the focus is on developing software.

Long Standards, Twinkie IP, Macro Trends, and Patent Trolls

Friday, May 10th, 2013

In Part II, IP Extreme’s Savage reveals why IP standards take so long while discussing brand values, macro trends, and changes wrought by patent trolls.

Blyler: Last time we talked, we covered the ongoing development of a soft IP standard. Should we expect an update in the near future?

Savage: The standard is in draft form and being reviewed among the technical contributors at Accellera. It’s just a matter of getting consensus within the EDA community and with the equipment manufacturers, who will need a mechanism to read the soft IP. What helps a lot is that this standard is based on the existing one for hard IP tagging. There are just a few extra things that needed to be added (to the soft IP standard).

Blyler: Please tell us more about those “extra things.”

Savage: One of the extra things proposed in the soft IP standard is the inclusion of export control information in the tag. That’s important in IP. For example, if the semiconductor IP has an Export Control Classification Number (ECCN), that information could be placed in the tag. It could then be discovered later on an actual device – perhaps in a (geographic) location where it shouldn’t be.

Blyler: Some have complained that the soft IP standard is taking too long to ratify. Any comments?

Savage: Things just move slowly in the semiconductor IP world – especially when you have interoperability with the EDA community. The challenge is that you need a handshake between the IP developers, the EDA companies who create the tools (that will need to make the [soft IP] machine-readable), and finally the semiconductor companies (who will actually be using the tools). You have to get all of those constituencies lined up. Like any standard, it takes a number of years before everyone agrees on the details and then gets the standard into widespread industry use.

Blyler: Has that process been made easier with all of the consolidations taking place in the EDA community? Do things move faster now because there are fewer players?

Savage: Surprisingly, the consolidation probably works against that. The problem is assessing a dollar value gain (to the soft IP). How much more can I charge if I support this standard? If you can’t answer that question, there is not a lot of motivation for EDA companies to invest in these things – especially in comparison to developing features for which people will pay extra money.

Blyler: Any other trends that you see?

Savage: We work with many companies to help create external channels for their internal IP. Lots of semiconductor companies talk with us about how to efficiently manage both their internal and external IP.

There is a nice video that Kevin Kline from Freescale did for us at our recent user event. One of his key points was that the value of the internal IP is worth more than the market cap of the company itself. It is analogous toHostess Twinkies in that the value of the brand is worth way more than the Hostess factories. It’s similar with IP at large semiconductor companies.

I’ve had analysts call me to ask about the value of a specific company IP portfolio in relation to the competition. It seems that an increasing number of semiconductor companies are taking a more strategic view of their IP – beyond just the raw material and resources point of view. Within the next five years, I think that companies will think completely differently about their IP. This is a big macro trend – a new way of looking at IP.

Blyler: How do companies determine the real marketplace value of their IP? Is there an accepted benchmark or other means of open comparison?

Savage: The situation is very fluid. Look at the activities of Google and Motorola, where companies were being bought just for their IP. But their IP became a lot more valuable once Apple and Google started fighting it out in the marketplace (i.e., iOS vs. Android). A company’s IP may not have much value until something happens in the market. Then it becomes extraordinarily valuable. The big problem facing most companies is that they don’t know what IP they have. They might have this big opportunity because the market shifts and they are suddenly sitting on a treasure trove that they didn’t know they had.

Blyler: What about patent and IP trolls? I’ve seen companies that announced partnerships with certain patent houses and then, a month later, sued a competitor for patent infringement. I’m wondering what effect that has on innovation. Do you think patent trolls slow down innovation in favor of quick financial returns?

Savage: Most people have a pretty negative view of patent trolls – like the modern version of the highwayman. The troll analogy is quite good, as they seem to wait for someone interesting to appear. Then they pop out and ask for “your money or your life.” Inevitably, the industry will be heading for some kind of legislation to put some brakes on that activity – especially since there are a lot of people trying to get rich quick by specifically setting up practices to do patent trolling. It’s an extremely negative thing. But that is another reason why companies need to be on top of what IP they have. In these situations, you might have cross-licensing and such.

Blyler: Thank you.



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